[U-Boot-Users] Intel Flash CFI initialisation failure

[U-Boot-Users] Intel Flash CFI initialisation failure

[Miroslaw Dach]

Dear All,

            I am having the problem with Intel Flash TE28F640 J3C120 on my
avnet evaluation board (xilinx based with Virtex-4). I have compiled
successfully u-boot-1.2.0 and it run well without FLASH support.
Eventually I want to store u-boot in Flash but when I compile u-boot with
Flash support the u-boot fails during Flash initialization.

My Flash memory is:
type:    TE28F640 J3C120  (http://www.datasheets.org.uk/datasheet.php?article=3266188) 
vendor:  Intel
spec:    NOR FLASH 64 Blocks 64 Mbits x8/x16
 

To support Flash memory I have configured u-boot with the following settings:

#define CFG_FLASH_BASE                     0xFF800000              
#define CFG_MAX_FLASH_BANKS                1 
#define CFG_MAX_FLASH_SECT                 64
#define CFG_FLASH_CFI                      1 
#define CFG_FLASH_CFI_DRIVER               1 
 
The u-boot was compiled successfully but when I booted it I have got the 
error messages when it came to the Flash initialization:

U-Boot 1.2.0 (Sep  6 2007 - 17:56:34)

### No HW ID - assuming ML403
DRAM:  32 MB
Top of RAM usable for U-Boot at: 02000000
Reserving 138k for U-Boot at: 01fdd000
Reserving 129k for malloc() at: 01fbcc00
Reserving 120 Bytes for Board Info at: 01fbcb88
Reserving 48 Bytes for Global Data at: 01fbcb58
Stack Pointer at: 01fbcb38
New Stack Pointer is: 01fbcb38
Now running in RAM - U-Boot at: 01fdd000
FLASH: flash detect cfi
fwc addr ff800000 cmd 0 0 8bit x 8 bit
fwc addr ff800055 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff800010 is= 0 51
fwc addr ff800555 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff800010 is= 0 51
fwc addr ff800000 cmd 0 0000 16bit x 8 bit
fwc addr ff8000aa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= 0051 5151
fwc addr ff800aaa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= 0051 5151
fwc addr ff800000 cmd 0 0000 16bit x 16 bit
fwc addr ff8000aa cmd 98 0098 16bit x 16 bit
is= cmd 51(Q) addr ff800020 is= 0051 0051
is= cmd 52(R) addr ff800022 is= 0052 0052
is= cmd 59(Y) addr ff800024 is= 0059 0059
ushort addr is at ff800050 info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x2
addr[2] = 0x0
addr[3] = 0x0
retval = 0x2
device interface is 2
found port 2 chip 2 port 16 bits chip 16 bits
ushort addr is at ff800026 info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x1
addr[2] = 0x0
addr[3] = 0x0
retval = 0x1
fwc addr ff800000 cmd ff 00ff 16bit x 16 bit
fwc addr ff800000 cmd 90 0090 16bit x 16 bit
fwc addr ff800000 cmd ff 00ff 16bit x 16 bit
fwc addr ff8000aa cmd 98 0098 16bit x 16 bit
ushort addr is at ff80002a info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x31
addr[2] = 0x0
addr[3] = 0x0
retval = 0x31
ff800020 : 00 51 00 52 00 59 00 01 00 00 00 31 00 00 00 00  .Q.R.Y.....1....
ff800030 : 00 00 00 00 00 00 00 27 00 36 00 00 00 00 00 08  .......'.6......
ff800040 : 00 08 00 0b 00 00 00 02 00 02 00 03 00 00 00 17  ................
ff800050 : 00 02 00 00 00 05 00 00 00 01 00 3f 00 00 00 00  ...........?....
ff800060 : 00 02 00 50 00 52 00 49 00 31 00 31 00 ce 00 00  ...P.R.I.1.1....
ff800070 : 00 00 00 00 00 01 00 01 00 00 00 33 00 00 00 01  ...........3....
ff800080 : 00 80 00 00 00 03 00 03 00 03 00 00 00 00 00 00  ................
ff800090 : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff  ................
manufacturer is 1
manufacturer id is 0x89
device id is 0x17
device id2 is 0x0
cfi version is 0x3131
size_ratio 1 port 16 bits chip 16 bits
found 1 erase regions
long addr is at ff80005a info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x3f
addr[2] = 0x0
addr[3] = 0x0
addr[4] = 0x0
addr[5] = 0x0
addr[6] = 0x0
addr[7] = 0x2
erase_region_count = 64 erase_region_size = 131072
Bus Fault @ 0x01fe4424, fixup 0x00000000
Machine check in kernel mode.
Caused by (from msr): regs 01fbc978 Data parity signal
NIP: 01FE4424 XER: 20000000 LR: 01FE43D8 REGS: 01fbc978 TRAP: 0200 DAR: 
00000000MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 00000000 01FBCA68 C01FC950 01FFF8D0 00000001 01FBCA70 00000001 00000006 
GPR08: 00000000 FFC00004 01FBCA73 00000003 01FBC860 30000000 02001600 00000000 
GPR16: 00020000 00000001 0000002D 00000000 00000020 00000040 0000002D FFC20000 
GPR24: 01FFF950 00000001 00000020 00000004 01FFF8D0 01FBCB58 02001A94 FFC00000 
Call backtrace: 
machine check
NIP: FFFFFFFC XER: 00000000 LR: 01FED864 REGS: 01fbc868 TRAP: 0700 DAR: 
00000001MSR: 00000000 EE: 0 PR: 0 FP: 0 ME: 0 IR/DR: 00


Does anybody have an idea what could be wrong?

Best Regards

Mirek

 
=============================================================================
          Miroslaw Dach (Miroslaw.Dach at psi.ch) - SLS/Controls Group 
                PSI - Paul Scherrer Institut CH-5232 Villigen
=============================================================================

[U-Boot-Users] Intel Flash CFI initialisation failure

[Wolfgang Denk]

In message <Pine.LNX.4.44.0709071639130.13688-100000@slslc02.psi.ch> you wrote:
> 
>             I am having the problem with Intel Flash TE28F640 J3C120 on my
> avnet evaluation board (xilinx based with Virtex-4). I have compiled
...

Why are you posting the same stuff twice here? Please don't do that,

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Men will always be men -- no matter where they are.
	-- Harry Mudd, "Mudd's Women", stardate 1329.8

[U-Boot-Users] Intel Flash CFI initialisation failure

[Miroslaw Dach]

Hi Wolfgang,


> Why are you posting the same stuff twice here? Please don't do that,
>
> Best regards,
>
> Wolfgang Denk

	I have sent the same post twice since first time when I have tried 
to send it via: www.nabble.com it was not accepted by the 
lists.sourceforge.net. I have verified it on the lists.sourceforge.net web 
page and it indeed was not there so I have tried to send it directly.

Best Regards

Mirek

=============================================================================
          Miroslaw Dach (Miroslaw.Dach at psi.ch) - SLS/Controls Group 
                PSI - Paul Scherrer Institut CH-5232 Villigen
=============================================================================

[U-Boot-Users] Intel Flash CFI initialisation failure

[Miroslaw Dach]

Dear All,

	After some tests I have found out few things which caused the 
problem with my Flash:

1. The erase_region_size variable gets twice bigger number (ie. 131072 
instead of 65536) than it should:

File:        ./drivers/cfi_flash.c
function:     flash_get_size(ulong base, int banknum)

	erase_region_size =
			(tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;


When I reduced the erase_region_size by 2 the u-boot initialization 
went to the successful end. Next What I did I have tried to read, write 
and erase memory/sectors. The Read/erase function worked fine but when 
writing to the memory I have got a time out:

---------------- u-boot output --------------------------------
=> flinfo

Bank # 1: CFI conformant FLASH (16 x 16)  Size: 8 MB in 64 Sectors
  Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x17
  Erase timeout: 16384 ms, write timeout: 2 ms
  Buffer write timeout: 2 ms, buffer size: 32 bytes

=> cp.w 0x400000  FF860000 0x49
Copy to Flash... fwc addr ff860000 cmd 50 0050 16bit x 16 bit
fwc addr ff860000 cmd e8 00e8 16bit x 16 bit
flash_is_busy: 0
fwc addr ff860000 cmd f 000f 16bit x 16 bit
fwc addr ff860000 cmd d0 00d0 16bit x 16 bit
flash_is_busy: 1
long addr is at ff860000 info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x80
addr[2] = 0x0
addr[3] = 0x80
addr[4] = 0x0
addr[5] = 0x80
addr[6] = 0x0
addr[7] = 0x80
Flash buffer write timeout at address ff860000 data 80808080
fwc addr ff860000 cmd ff 00ff 16bit x 16 bit
fwc addr ff860000 cmd ff 00ff 16bit x 16 bit
Timeout writing to Flash

-----------------------------------------------------------------------

I thought that maybe it is set wrongly the processor speed so I have set in 
the include/configs/ml403.h 
#define CONFIG_SYS_CLK_FREQ 100000000

since my PPC405 works with the frequency 100 MHZ
but unfortunately it did not help so I have modified in the:

File:        ./drivers/cfi_flash.c
function:    flash_status_check( ) 

tout *= 10;

The factor 10 was obtained after some experiments.
The time passage when booting u-boot is roughly speaking fine since the
count down from 10 - 0 sec. reflect this what I measure with normal watch 
so the timeout problem refers to something else? 

3. My third observation is that when I refer to the wrong memory location
(ie. md 0x2000000 which is beyond RAM or Flash) than u-boot crashes and I
get:

=> md 0x2000000
02000000:Bus Fault @ 0x01fe84b0, fixup 0x00000000
Machine check in kernel mode.
Caused by (from msr): regs 01fbc620 Data parity signal
NIP: 01FE84B0 XER: 20000000 LR: 01FE8480 REGS: 01fbc620 TRAP: 0200 DAR: 00000004
MSR: 00029000 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 01FE8480 01FBC710 C01FC950 00000000 00000000 00000010 00000001 00000007 
GPR08: 00000001 40600004 00000000 01FBC4D6 01FBC4D8 30000000 02000F00 017DD000 

Is it somehow possible to restrict in u-boot memory regions which are valid 
for RAM and Flash and reject other regions.

Best Regards

Mirek

[U-Boot-Users] Intel Flash CFI initialisation failure

[Miroslaw Dach]

Hi All,

	Unfortunately I did not solve completely the problem which I had 
with the Flash memory. It seems to be that in u-boot there is a problem 
with 16 bits long data access. 

My memory has the size of 64 Mbits. In my configuration it should be 
accessed in x16 bits mode so it means that under each memory location 
there are 16 bits. In u-boot it seems to be that all is seen in bytes and 
under one memory location there is seen only one byte instead of two.

Is it somehow possible to change that by some define statements?

Best Regards

Mirek

=============================================================================
          Miroslaw Dach (Miroslaw.Dach at psi.ch) - SLS/Controls Group 
                PSI - Paul Scherrer Institut CH-5232 Villigen
=============================================================================

[U-Boot-Users] Intel Flash CFI initialisation failure

[Jerry Van Baren]

Miroslaw Dach wrote:
> Hi All,
> 
> 	Unfortunately I did not solve completely the problem which I had 
> with the Flash memory. It seems to be that in u-boot there is a problem 
> with 16 bits long data access. 
> 
> My memory has the size of 64 Mbits. In my configuration it should be 
> accessed in x16 bits mode so it means that under each memory location 
> there are 16 bits. In u-boot it seems to be that all is seen in bytes and 
> under one memory location there is seen only one byte instead of two.
> 
> Is it somehow possible to change that by some define statements?
> 
> Best Regards
> 
> Mirek

Trying to understand, are you saying your hardware has the CFI flash 
hooked up 16 bits wide on 32 bit boundaries (every 32 bit word has 16 
bits of garbage and 16 bits of CFI flash data)?

Thanks,
gvb

[U-Boot-Users] Intel Flash CFI initialisation failure

[Miroslaw Dach]

Hi Jerry,

> Trying to understand, are you saying your hardware has the CFI flash 
> hooked up 16 bits wide on 32 bit boundaries (every 32 bit word has 16 
> bits of garbage and 16 bits of CFI flash data)?

I use Intel Flash CFI compliant and it has two modes of operation x8/x16.
The hardware is configured to operate in x16 mode so it means that under 
each address there are 16 bits. In u-boot it seems to be only 8 bits 
visible/visible. 

Best Regards

Mirek

-- 
=============================================================================
          Miroslaw Dach (Miroslaw.Dach at psi.ch) - SLS/Controls Group 
                PSI - Paul Scherrer Institut CH-5232 Villigen
=============================================================================

[U-Boot-Users] Intel Flash CFI initialisation failure

[David Hawkins]

Hi Mirek,

> Unfortunately I did not solve completely the problem which I had 
> with the Flash memory. It seems to be that in u-boot there is a problem 
> with 16 bits long data access. 
> 
> My memory has the size of 64 Mbits. In my configuration it should be 
> accessed in x16 bits mode so it means that under each memory location 
> there are 16 bits. In u-boot it seems to be that all is seen in bytes and 
> under one memory location there is seen only one byte instead of two.
> 
> Is it somehow possible to change that by some define statements?

Perhaps the board has LA[n:31] connected to the address bus
of the Flash rather than the correct LA[n:30] signals.

If so, its a hardware error, and there is not much you can
do. Even if the chip has a BYTE# pin you can change modes
with, a 16-bit Flash usually has a DQ15/A-1 pin that LA[31]
would then connect to.

Just a thought ...

Cheers,
Dave

[U-Boot-Users] Intel Flash CFI initialisation failure

[Scott Mann]

I just ran into this problem also and posted to the list (but got no responses).

After a couple days of sorting through the cfi_flash.c, I noticed that the CFG_FLASH_BANKS_LIST seemed to be the pertinent #define. You need to set this to an address that is beyond the region of flash in which you have stored your u-boot and environment variables. Otherwise, the first thing that the CFI code does is erase it!

Take the following example:


#define CFG_FLASH_PROTECTION    1      /* Real (hardware) sectors protection */
#define CFG_FLASH_BASE          0xFE000000
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks       */
#define CFG_MAX_FLASH_SECT      32      /* max num of sects on one chip */
#define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Monitor */

#define CFG_ENV_IS_IN_FLASH

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE       (64 * 1024) /* Reserve 64 kB for env */
#define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_PROTECTED_SIZE      (CFG_MONITOR_LEN + CFG_ENV_SECT_SIZE)
#define CFG_FLASH_BANKS_LIST    { (CFG_FLASH_BASE + CFG_PROTECTED_SIZE) }
#endif /* CFG_ENV_IS_IN_FLASH */

What I've done is added CFG_PROTECTED_SIZE as just an intermediate parameter (it will probably go away). It represents the space reserved for U-Boot (256K) + the space reserved for ENV (64K). Just use this as an offset to the CFG_FLASH_BASE and assign that to CFG_FLASH_BANKS_LIST (and it is only that element since you only have one flash bank).

I'm not sure whether you want CFG_FLASH_PROTECTION or not in your environment (I'm pretty sure it doesn't have an effect on the problem you've encountered).

Hope this helps. If anyone sees a flaw in this approach, please let me know!

Scott


----- Original Message ----
From: Miroslaw Dach <miroslaw.dach@psi.ch>
To: u-boot-users at lists.sourceforge.net
Sent: Friday, September 7, 2007 8:43:38 AM
Subject: [U-Boot-Users] Intel Flash CFI initialisation failure

Dear All,

            I am having the problem with Intel Flash TE28F640 J3C120 on my
avnet evaluation board (xilinx based with Virtex-4). I have compiled
successfully u-boot-1.2.0 and it run well without FLASH support.
Eventually I want to store u-boot in Flash but when I compile u-boot with
Flash support the u-boot fails during Flash initialization.

My Flash memory is:
type:    TE28F640 J3C120  (http://www.datasheets.org.uk/datasheet.php?article=3266188) 
vendor:  Intel
spec:    NOR FLASH 64 Blocks 64 Mbits x8/x16
 

To support Flash memory I have configured u-boot with the following settings:

#define CFG_FLASH_BASE                     0xFF800000              
#define CFG_MAX_FLASH_BANKS                1 
#define CFG_MAX_FLASH_SECT                 64
#define CFG_FLASH_CFI                      1 
#define CFG_FLASH_CFI_DRIVER               1 
 
The u-boot was compiled successfully but when I booted it I have got the 
error messages when it came to the Flash initialization:

U-Boot 1.2.0 (Sep  6 2007 - 17:56:34)

### No HW ID - assuming ML403
DRAM:  32 MB
Top of RAM usable for U-Boot at: 02000000
Reserving 138k for U-Boot at: 01fdd000
Reserving 129k for malloc() at: 01fbcc00
Reserving 120 Bytes for Board Info at: 01fbcb88
Reserving 48 Bytes for Global Data at: 01fbcb58
Stack Pointer at: 01fbcb38
New Stack Pointer is: 01fbcb38
Now running in RAM - U-Boot at: 01fdd000
FLASH: flash detect cfi
fwc addr ff800000 cmd 0 0 8bit x 8 bit
fwc addr ff800055 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff800010 is= 0 51
fwc addr ff800555 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff800010 is= 0 51
fwc addr ff800000 cmd 0 0000 16bit x 8 bit
fwc addr ff8000aa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= 0051 5151
fwc addr ff800aaa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= 0051 5151
fwc addr ff800000 cmd 0 0000 16bit x 16 bit
fwc addr ff8000aa cmd 98 0098 16bit x 16 bit
is= cmd 51(Q) addr ff800020 is= 0051 0051
is= cmd 52(R) addr ff800022 is= 0052 0052
is= cmd 59(Y) addr ff800024 is= 0059 0059
ushort addr is at ff800050 info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x2
addr[2] = 0x0
addr[3] = 0x0
retval = 0x2
device interface is 2
found port 2 chip 2 port 16 bits chip 16 bits
ushort addr is at ff800026 info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x1
addr[2] = 0x0
addr[3] = 0x0
retval = 0x1
fwc addr ff800000 cmd ff 00ff 16bit x 16 bit
fwc addr ff800000 cmd 90 0090 16bit x 16 bit
fwc addr ff800000 cmd ff 00ff 16bit x 16 bit
fwc addr ff8000aa cmd 98 0098 16bit x 16 bit
ushort addr is at ff80002a info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x31
addr[2] = 0x0
addr[3] = 0x0
retval = 0x31
ff800020 : 00 51 00 52 00 59 00 01 00 00 00 31 00 00 00 00  .Q.R.Y.....1....
ff800030 : 00 00 00 00 00 00 00 27 00 36 00 00 00 00 00 08  .......'.6......
ff800040 : 00 08 00 0b 00 00 00 02 00 02 00 03 00 00 00 17  ................
ff800050 : 00 02 00 00 00 05 00 00 00 01 00 3f 00 00 00 00  ...........?....
ff800060 : 00 02 00 50 00 52 00 49 00 31 00 31 00 ce 00 00  ...P.R.I.1.1....
ff800070 : 00 00 00 00 00 01 00 01 00 00 00 33 00 00 00 01  ...........3....
ff800080 : 00 80 00 00 00 03 00 03 00 03 00 00 00 00 00 00  ................
ff800090 : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff  ................
manufacturer is 1
manufacturer id is 0x89
device id is 0x17
device id2 is 0x0
cfi version is 0x3131
size_ratio 1 port 16 bits chip 16 bits
found 1 erase regions
long addr is at ff80005a info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x3f
addr[2] = 0x0
addr[3] = 0x0
addr[4] = 0x0
addr[5] = 0x0
addr[6] = 0x0
addr[7] = 0x2
erase_region_count = 64 erase_region_size = 131072
Bus Fault @ 0x01fe4424, fixup 0x00000000
Machine check in kernel mode.
Caused by (from msr): regs 01fbc978 Data parity signal
NIP: 01FE4424 XER: 20000000 LR: 01FE43D8 REGS: 01fbc978 TRAP: 0200 DAR: 
00000000MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 00000000 01FBCA68 C01FC950 01FFF8D0 00000001 01FBCA70 00000001 00000006 
GPR08: 00000000 FFC00004 01FBCA73 00000003 01FBC860 30000000 02001600 00000000 
GPR16: 00020000 00000001 0000002D 00000000 00000020 00000040 0000002D FFC20000 
GPR24: 01FFF950 00000001 00000020 00000004 01FFF8D0 01FBCB58 02001A94 FFC00000 
Call backtrace: 
machine check
NIP: FFFFFFFC XER: 00000000 LR: 01FED864 REGS: 01fbc868 TRAP: 0700 DAR: 
00000001MSR: 00000000 EE: 0 PR: 0 FP: 0 ME: 0 IR/DR: 00


Does anybody have an idea what could be wrong?

Best Regards

Mirek

 
=============================================================================
          Miroslaw Dach (Miroslaw.Dach at psi.ch) - SLS/Controls Group 
                PSI - Paul Scherrer Institut CH-5232 Villigen
=============================================================================



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[U-Boot-Users] Intel Flash CFI initialisation failure

[Miroslaw Dach]

Hi Scott,

	Thank you very much for your answer to my post. I am relatively
new user of u-boot and I did not get so far the concept of Flash memory
initialization when using cfi_flash driver. I understood from your post
that during initialization the data which is stored in the CFI Flash
memory might be deleted (erased) if I do not protect it by the macro
CFG_PROTECTED_SIZE in combination with CFG_FLASH_BANKS_LIST. Am I right?

I was trying to find something in the README about Flash usage but I did 
not find much about that.

My aim is just to  make Flash memory available for u-boot to read and writ 
from it but I do not want to erase any thing during initialization.

I thought that following settings are sufficient:

#define CFG_FLASH_BASE                     0xFF800000              
#define CFG_MAX_FLASH_BANKS                1
#define CFG_MAX_FLASH_SECT                 64
#define CFG_FLASH_CFI                      1
#define CFG_FLASH_CFI_DRIVER               1 
 
I do not get clearly the concept with MONITOR . What is that used for?


I have tried your idea to use CFG_PROTECTED_SIZE and CFG_FLASH_BANKS_LIST 
and what I see that whatever I set to the CFG_FLASH_BANKS_LIST I get 
something like below:

U-Boot 1.2.0 (Sep 10 2007 - 12:07:00)

### No HW ID - assuming ML403
DRAM:  32 MB
Top of RAM usable for U-Boot at: 02000000
Reserving 139k for U-Boot at: 01fdd000
Reserving 129k for malloc() at: 01fbcc00
Reserving 120 Bytes for Board Info at: 01fbcb88
Reserving 48 Bytes for Global Data at: 01fbcb58
Stack Pointer at: 01fbcb38
New Stack Pointer is: 01fbcb38
Now running in RAM - U-Boot at: 01fdd000
FLASH: flash detect cfi
fwc addr ff802000 cmd 0 0 8bit x 8 bit
fwc addr ff802055 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff802010 is= 0 51
fwc addr ff802555 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff802010 is= 0 51
fwc addr ff802000 cmd 0 0000 16bit x 8 bit
fwc addr ff8020aa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff802020 is= 0000 5151
fwc addr ff802aaa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff802020 is= 0000 5151
fwc addr ff802000 cmd 0 0000 16bit x 16 bit
fwc addr ff8020aa cmd 98 0098 16bit x 16 bit
is= cmd 51(Q) addr ff802020 is= 0000 0051
fwc addr ff802aaa cmd 98 0098 16bit x 16 bit
is= cmd 51(Q) addr ff802020 is= 0000 0051
fwc addr ff802000 cmd 0 00000000 32bit x 8 bit
fwc addr ff802154 cmd 98 98989898 32bit x 8 bit
is= cmd 51(Q) addr ff802040 is= 00000000 51515151
fwc addr ff803554 cmd 98 98989898 32bit x 8 bit
is= cmd 51(Q) addr ff802040 is= 00000000 51515151
fwc addr ff802000 cmd 0 00000000 32bit x 16 bit
fwc addr ff802154 cmd 98 00980098 32bit x 16 bit
is= cmd 51(Q) addr ff802040 is= 00000000 00510051
fwc addr ff803554 cmd 98 00980098 32bit x 16 bit
is= cmd 51(Q) addr ff802040 is= 00000000 00510051
fwc addr ff802000 cmd 0 00000000 32bit x 32 bit
fwc addr ff802154 cmd 98 00000098 32bit x 32 bit
is= cmd 51(Q) addr ff802040 is= ffff0000 00000051
fwc addr ff803554 cmd 98 00000098 32bit x 32 bit
is= cmd 51(Q) addr ff802040 is= ffff0000 00000051
fwrite addr ff802000 cmd 0 0000000000000000 64 bit x 8 bit
fwrite addr ff8022a8 cmd 98 9898989898989898 64 bit x 8 bit
is= cmd 51(Q) addr ff802080 is= 0000000000000000 5151515151515151
fwrite addr ff804aa8 cmd 98 9898989898989898 64 bit x 8 bit
is= cmd 51(Q) addr ff802080 is= 0000000000000000 5151515151515151
fwrite addr ff802000 cmd 0 0000000000000000 64 bit x 16 bit
fwrite addr ff8022a8 cmd 98 0098009800980098 64 bit x 16 bit
is= cmd 51(Q) addr ff802080 is= 0000000000000000 0051005100510051
fwrite addr ff804aa8 cmd 98 0098009800980098 64 bit x 16 bit
is= cmd 51(Q) addr ff802080 is= 0000000000000000 0051005100510051
fwrite addr ff802000 cmd 0 0000000000000000 64 bit x 32 bit
fwrite addr ff8022a8 cmd 98 0000009800000098 64 bit x 32 bit
is= cmd 51(Q) addr ff802080 is= ffff0000ffff0000 0000005100000051
fwrite addr ff804aa8 cmd 98 0000009800000098 64 bit x 32 bit
is= cmd 51(Q) addr ff802080 is= ffff0000ffff0000 0000005100000051
fwrite addr ff802000 cmd 0 0000000000000000 64 bit x 64 bit
fwrite addr ff8022a8 cmd 98 0000000000000098 64 bit x 64 bit
is= cmd 51(Q) addr ff802080 is= ffff0000ffff0000 0000000000000051
fwrite addr ff804aa8 cmd 98 0000000000000098 64 bit x 64 bit
is= cmd 51(Q) addr ff802080 is= ffff0000ffff0000 0000000000000051
not found
## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB
*** failed ***
### ERROR ### Please RESET the board ###

It seems to be that my chip was not recognised. If I do not set 
CFG_FLASH_BANKS_LIST I get the failure as in my first post.

Best Regards

Mirek





On Fri, 7 Sep 2007, Scott Mann wrote:

> I just ran into this problem also and posted to the list (but got no responses).

After a couple days of sorting through the cfi_flash.c, I noticed that the CFG_FLASH_BANKS_LIST seemed to be the pertinent #define. You need to set this to an address that is beyond the region of flash in which you have stored your u-boot and environment variables. Otherwise, the first thing that the CFI code does is erase it!

Take the following example:


#define CFG_FLASH_PROTECTION    1      /* Real (hardware) sectors protection */
#define CFG_FLASH_BASE          0xFE000000
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks       */
#define CFG_MAX_FLASH_SECT      32      /* max num of sects on one chip */
#define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Monitor */

#define CFG_ENV_IS_IN_FLASH

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE       (64 * 1024) /* Reserve 64 kB for env */
#define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_PROTECTED_SIZE      (CFG_MONITOR_LEN + CFG_ENV_SECT_SIZE)
#define CFG_FLASH_BANKS_LIST    { (CFG_FLASH_BASE + CFG_PROTECTED_SIZE) }
#endif /* CFG_ENV_IS_IN_FLASH */

What I've done is added CFG_PROTECTED_SIZE as just an intermediate parameter (it will probably go away). It represents the space reserved for U-Boot (256K) + the space reserved for ENV (64K). Just use this as an offset to the CFG_FLASH_BASE and assign that to CFG_FLASH_BANKS_LIST (and it is only that element since you only have one flash bank).

I'm not sure whether you want CFG_FLASH_PROTECTION or not in your environment (I'm pretty sure it doesn't have an effect on the problem you've encountered).

Hope this helps. If anyone sees a flaw in this approach, please let me know!

Scott


----- Original Message ----
From: Miroslaw Dach <miroslaw.dach@psi.ch>
To: u-boot-users at lists.sourceforge.net
Sent: Friday, September 7, 2007 8:43:38 AM
Subject: [U-Boot-Users] Intel Flash CFI initialisation failure

Dear All,

            I am having the problem with Intel Flash TE28F640 J3C120 on my
avnet evaluation board (xilinx based with Virtex-4). I have compiled
successfully u-boot-1.2.0 and it run well without FLASH support.
Eventually I want to store u-boot in Flash but when I compile u-boot with
Flash support the u-boot fails during Flash initialization.

My Flash memory is:
type:    TE28F640 J3C120  (http://www.datasheets.org.uk/datasheet.php?article=3266188) 
vendor:  Intel
spec:    NOR FLASH 64 Blocks 64 Mbits x8/x16
 

To support Flash memory I have configured u-boot with the following settings:

#define CFG_FLASH_BASE                     0xFF800000              
#define CFG_MAX_FLASH_BANKS                1 
#define CFG_MAX_FLASH_SECT                 64
#define CFG_FLASH_CFI                      1 
#define CFG_FLASH_CFI_DRIVER               1 
 
The u-boot was compiled successfully but when I booted it I have got the 
error messages when it came to the Flash initialization:

U-Boot 1.2.0 (Sep  6 2007 - 17:56:34)

### No HW ID - assuming ML403
DRAM:  32 MB
Top of RAM usable for U-Boot at: 02000000
Reserving 138k for U-Boot at: 01fdd000
Reserving 129k for malloc() at: 01fbcc00
Reserving 120 Bytes for Board Info at: 01fbcb88
Reserving 48 Bytes for Global Data at: 01fbcb58
Stack Pointer at: 01fbcb38
New Stack Pointer is: 01fbcb38
Now running in RAM - U-Boot at: 01fdd000
FLASH: flash detect cfi
fwc addr ff800000 cmd 0 0 8bit x 8 bit
fwc addr ff800055 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff800010 is= 0 51
fwc addr ff800555 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff800010 is= 0 51
fwc addr ff800000 cmd 0 0000 16bit x 8 bit
fwc addr ff8000aa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= 0051 5151
fwc addr ff800aaa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= 0051 5151
fwc addr ff800000 cmd 0 0000 16bit x 16 bit
fwc addr ff8000aa cmd 98 0098 16bit x 16 bit
is= cmd 51(Q) addr ff800020 is= 0051 0051
is= cmd 52(R) addr ff800022 is= 0052 0052
is= cmd 59(Y) addr ff800024 is= 0059 0059
ushort addr is at ff800050 info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x2
addr[2] = 0x0
addr[3] = 0x0
retval = 0x2
device interface is 2
found port 2 chip 2 port 16 bits chip 16 bits
ushort addr is at ff800026 info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x1
addr[2] = 0x0
addr[3] = 0x0
retval = 0x1
fwc addr ff800000 cmd ff 00ff 16bit x 16 bit
fwc addr ff800000 cmd 90 0090 16bit x 16 bit
fwc addr ff800000 cmd ff 00ff 16bit x 16 bit
fwc addr ff8000aa cmd 98 0098 16bit x 16 bit
ushort addr is at ff80002a info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x31
addr[2] = 0x0
addr[3] = 0x0
retval = 0x31
ff800020 : 00 51 00 52 00 59 00 01 00 00 00 31 00 00 00 00  .Q.R.Y.....1....
ff800030 : 00 00 00 00 00 00 00 27 00 36 00 00 00 00 00 08  .......'.6......
ff800040 : 00 08 00 0b 00 00 00 02 00 02 00 03 00 00 00 17  ................
ff800050 : 00 02 00 00 00 05 00 00 00 01 00 3f 00 00 00 00  ...........?....
ff800060 : 00 02 00 50 00 52 00 49 00 31 00 31 00 ce 00 00  ...P.R.I.1.1....
ff800070 : 00 00 00 00 00 01 00 01 00 00 00 33 00 00 00 01  ...........3....
ff800080 : 00 80 00 00 00 03 00 03 00 03 00 00 00 00 00 00  ................
ff800090 : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff  ................
manufacturer is 1
manufacturer id is 0x89
device id is 0x17
device id2 is 0x0
cfi version is 0x3131
size_ratio 1 port 16 bits chip 16 bits
found 1 erase regions
long addr is at ff80005a info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x3f
addr[2] = 0x0
addr[3] = 0x0
addr[4] = 0x0
addr[5] = 0x0
addr[6] = 0x0
addr[7] = 0x2
erase_region_count = 64 erase_region_size = 131072
Bus Fault @ 0x01fe4424, fixup 0x00000000
Machine check in kernel mode.
Caused by (from msr): regs 01fbc978 Data parity signal
NIP: 01FE4424 XER: 20000000 LR: 01FE43D8 REGS: 01fbc978 TRAP: 0200 DAR: 
00000000MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 00000000 01FBCA68 C01FC950 01FFF8D0 00000001 01FBCA70 00000001 00000006 
GPR08: 00000000 FFC00004 01FBCA73 00000003 01FBC860 30000000 02001600 00000000 
GPR16: 00020000 00000001 0000002D 00000000 00000020 00000040 0000002D FFC20000 
GPR24: 01FFF950 00000001 00000020 00000004 01FFF8D0 01FBCB58 02001A94 FFC00000 
Call backtrace: 
machine check
NIP: FFFFFFFC XER: 00000000 LR: 01FED864 REGS: 01fbc868 TRAP: 0700 DAR: 
00000001MSR: 00000000 EE: 0 PR: 0 FP: 0 ME: 0 IR/DR: 00


Does anybody have an idea what could be wrong?

Best Regards

Mirek

 
=============================================================================
          Miroslaw Dach (Miroslaw.Dach at psi.ch) - SLS/Controls Group 
                PSI - Paul Scherrer Institut CH-5232 Villigen
=============================================================================



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> 

-- 
=============================================================================
          Miroslaw Dach (Miroslaw.Dach at psi.ch) - SLS/Controls Group 
                PSI - Paul Scherrer Institut CH-5232 Villigen
=============================================================================

[U-Boot-Users] Intel Flash CFI initialisation failure

[Mirek23]

Dear All,

            I am having the problem with Intel Flash TE28F640 J3C120 on my
avnet evaluation board
(xilinx based with Virtex-4). I have compiled successfully u-boot-1.2.0 and
it run well without FLASH support. Eventually I want to store u-boot in
Flash but when I compile u-boot with Flash support the u-boot fails during
Flash initialization.

My Flash memory is:
type:    TE28F640 J3C120 
(http://www.datasheets.org.uk/datasheet.php?article=3266188) 
vendor: Intel
spec:    NOR FLASH 64 Blocks 64 Mbits x8/x16
 

To support Flash memory I have configured u-boot with the following
settings:
#define CFG_FLASH_BASE                     0xFF800000              
#define CFG_MAX_FLASH_BANKS            1 
#define CFG_MAX_FLASH_SECT              64
#define CFG_FLASH_CFI                        1 
#define CFG_FLASH_CFI_DRIVER             1 
 
The u-boot was compiled successfully but when I booted it I have got the 
error messages when it came to the Flash initialization:

U-Boot 1.2.0 (Sep  6 2007 - 17:56:34)

### No HW ID - assuming ML403
DRAM:  32 MB
Top of RAM usable for U-Boot at: 02000000
Reserving 138k for U-Boot at: 01fdd000
Reserving 129k for malloc() at: 01fbcc00
Reserving 120 Bytes for Board Info at: 01fbcb88
Reserving 48 Bytes for Global Data at: 01fbcb58
Stack Pointer at: 01fbcb38
New Stack Pointer is: 01fbcb38
Now running in RAM - U-Boot at: 01fdd000
FLASH: flash detect cfi
fwc addr ff800000 cmd 0 0 8bit x 8 bit
fwc addr ff800055 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff800010 is= 0 51
fwc addr ff800555 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff800010 is= 0 51
fwc addr ff800000 cmd 0 0000 16bit x 8 bit
fwc addr ff8000aa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= 0051 5151
fwc addr ff800aaa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= 0051 5151
fwc addr ff800000 cmd 0 0000 16bit x 16 bit
fwc addr ff8000aa cmd 98 0098 16bit x 16 bit
is= cmd 51(Q) addr ff800020 is= 0051 0051
is= cmd 52(R) addr ff800022 is= 0052 0052
is= cmd 59(Y) addr ff800024 is= 0059 0059
ushort addr is at ff800050 info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x2
addr[2] = 0x0
addr[3] = 0x0
retval = 0x2
device interface is 2
found port 2 chip 2 port 16 bits chip 16 bits
ushort addr is at ff800026 info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x1
addr[2] = 0x0
addr[3] = 0x0
retval = 0x1
fwc addr ff800000 cmd ff 00ff 16bit x 16 bit
fwc addr ff800000 cmd 90 0090 16bit x 16 bit
fwc addr ff800000 cmd ff 00ff 16bit x 16 bit
fwc addr ff8000aa cmd 98 0098 16bit x 16 bit
ushort addr is at ff80002a info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x31
addr[2] = 0x0
addr[3] = 0x0
retval = 0x31
ff800020 : 00 51 00 52 00 59 00 01 00 00 00 31 00 00 00 00  .Q.R.Y.....1....
ff800030 : 00 00 00 00 00 00 00 27 00 36 00 00 00 00 00 08  .......'.6......
ff800040 : 00 08 00 0b 00 00 00 02 00 02 00 03 00 00 00 17  ................
ff800050 : 00 02 00 00 00 05 00 00 00 01 00 3f 00 00 00 00  ...........?....
ff800060 : 00 02 00 50 00 52 00 49 00 31 00 31 00 ce 00 00  ...P.R.I.1.1....
ff800070 : 00 00 00 00 00 01 00 01 00 00 00 33 00 00 00 01  ...........3....
ff800080 : 00 80 00 00 00 03 00 03 00 03 00 00 00 00 00 00  ................
ff800090 : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff  ................
manufacturer is 1
manufacturer id is 0x89
device id is 0x17
device id2 is 0x0
cfi version is 0x3131
size_ratio 1 port 16 bits chip 16 bits
found 1 erase regions
long addr is at ff80005a info->portwidth = 2
addr[0] = 0x0
addr[1] = 0x3f
addr[2] = 0x0
addr[3] = 0x0
addr[4] = 0x0
addr[5] = 0x0
addr[6] = 0x0
addr[7] = 0x2
erase_region_count = 64 erase_region_size = 131072
Bus Fault @ 0x01fe4424, fixup 0x00000000
Machine check in kernel mode.
Caused by (from msr): regs 01fbc978 Data parity signal
NIP: 01FE4424 XER: 20000000 LR: 01FE43D8 REGS: 01fbc978 TRAP: 0200 DAR:
00000000MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 00000000 01FBCA68 C01FC950 01FFF8D0 00000001 01FBCA70 00000001
00000006 
GPR08: 00000000 FFC00004 01FBCA73 00000003 01FBC860 30000000 02001600
00000000 
GPR16: 00020000 00000001 0000002D 00000000 00000020 00000040 0000002D
FFC20000 
GPR24: 01FFF950 00000001 00000020 00000004 01FFF8D0 01FBCB58 02001A94
FFC00000 
Call backtrace: 
machine check
NIP: FFFFFFFC XER: 00000000 LR: 01FED864 REGS: 01fbc868 TRAP: 0700 DAR:
00000001MSR: 00000000 EE: 0 PR: 0 FP: 0 ME: 0 IR/DR: 00


Does anybody have an idea what could be wrong?

Best Regards

Mirek






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