[U-Boot-Users] Debugging u-boot on a custom 8548 board

robert lazarski
2007-09-19T17:35:12Z

Hi all, been spending a few days with my board and I see no signs of
life from u-boot. I'm running my code in u-boot pulled from sept
18th's git repo - rc1 I think. I've tried:

/home/iksrazal/eldk2/usr/bin> ./ppc_85xx-gdb /home/iksrazal/u-boot/u-boot
GNU gdb Red Hat Linux (6.3.0.0-1.21_3rh)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "--host=i386-redhat-linux --target=ppc-linux".
The target architecture is set automatically (currently powerpc:e500)
..
(gdb) set verbose on
(gdb) target remote 10.101.43.42:2001
Remote debugging using 10.101.43.42:2001
0x00000000 in ?? ()
(gdb) mon break hard
(gdb) b board_init_f
Reading in symbols for board.c...done.
Breakpoint 1 at 0xfff896e8: file board.c, line 365.
(gdb) c
Continuing.

Where it just hangs. I've tried 'go' in the bdi to no avail. I see no
life on the serial port.
While I have 128MB of flash positioned at 0xf8000000 , I've loaded
u-boot to 0xff8000000 - the default boot rom location for the 8548. I
suppose one of the things to try is booting from low memory - but I
haven't figured out how to do that via the boot sequencer or another
register just yet. I also tried loading uboot to 0xf8000000 but it
didn't work either.

The first culprit is probably our memory - 1GB of DDR2 ram. The
hardware guys tell me our DDR2 is exactly like the MPC8548CDS
reference board. I have the memory mapped to 0x00000000 , and I can do
this:

ATUM>mmh 0x00000000 0xcafe
ATUM>mdh 0x00000000 1
0_00000000 : 0xcafe -13570 ..
ATUM>

I get the feeling that somehow that u-boot isn't being executed yet -
how can I verify that? Maybe setting a breakpoint in start.S ? Pins on
the 8548 ? Googling has turned up a few posts saying that perhaps my
bdi config could be the culprit. Since I can erase the flash and load
u-boot into it, and seemingly read and write the memory, I'm going to
post my latest bdi config version but its most definetly a work in
progress! Any help appreciated.

; - BDI2000 - Atum
;---------------------------------------------------
;
;
; 3 TLBs: 1 para CCSBAR - 1 para DDR (1GB) - 1 para Flash (1GB)
;

[INIT]

DELAY 5000
;

;#######################################################################
; Errata PCI-Ex 26 workaround
WM32 0xFF70A000 0x0000005C ;Clear bit 1 & 0 in Link Control &
Status Register
WM32 0xFF70A004 0x00000000 ;(PCIconfiguration space register at
offset 0x5C)
WM32 0xFF7E0F08 0x00000008 ;Clear bit 30 in the engineering only register
;(CCSR space register at offset 0xe0f08)
;#######################################################################

;#######################################################################
; use the following two lines for STARTUP HALT
;WSPR 63 0xffff0000 ;IVPR to boot core
;WSPR 415 0x0000f000 ;IVOR15 : Debug exception
;
;#######################################################################

;#######################################################################
; Move the L2SRAM to the initial MMU page
WM32 0xFF720E44 0x0000001C ;L2ERRDIS: disable parity error
WM32 0xFF720000 0x60010000 ;L2CTL - 0110 0000 0000 0001 0000 0000 0000 0000
WM32 0xFF720100 0x0FFF8000 ;L2SRBAR0: map to 0x0_FFF80000
WM32 0xFF720000 0xA0010000 ;L2CTL

; load and execute some boot code
WM32 0xfffffffc 0x48000000 ;loop
EXEC 0xfffffffc
;
;#######################################################################

;##################################################################################
;# MMU initialization
;#
;# MAS0: MMU read/write and replacement control
;# MAS1: descriptor context and configuration control
;# MAS2: EPN and page attributes
;# MAS3: RPN and access control
;# MAS4: Hardware replacement assist configuration

;----------------------------------------------------------------------------------
;# define 1MB TLB1 entry 1: 0x40000000 - 0x400FFFFF
;# for CCSR

WSPR 624 0x10010000 ;# MAS0
WSPR 625 0x80000500 ;# MAS1
WSPR 626 0x40000008 ;# MAS2
WSPR 627 0x4000003f ;# MAS3
WSPR 628 0x00000000 ;# MAS4

;# write tlb entry
WM32 0xFFFFF000 0x7C0007A4 ;# tlbwe
WM32 0xFFFFF004 0x4C00012C ;# isync
WM32 0xFFFFF008 0x7C0004AC ;# msync
WM32 0xFFFFF00C 0x38600055 ;# li r3, 0x55 to confirm the running
WM32 0xFFFFF010 0x48000000 ;# infinite loop
WM32 0xfffffffc 0xfffff000

EXEC 0xfffff000

;----------------------------------------------------------------------------------
;

;----------------------------------------------------------------------------------
;# define 1GB TLB1 entry 2: 0x00000000 - 0x3FFFFFFF
;# for DDR

WSPR 624 0x10020000 ;# MAS0
WSPR 625 0x80000A00 ;# MAS1 - 1000 0000 0000 0000 0000 1010 0000 0000
WSPR 626 0x00000000 ;# MAS2
WSPR 627 0x0000003f ;# MAS3

;# write tlb entry
WM32 0xfffffffc 0xfffff000
EXEC 0xfffff000
;----------------------------------------------------------------------------------

;----------------------------------------------------------------------------------
;# define 64MBytes TLB entry 3: 0xF8000000 - 0xFFFFFFFF
;# for FLASH bank #0 and bank #1

WSPR 624 0x10030000 ;# MAS0
WSPR 625 0x80000800 ;# MAS1
WSPR 626 0xF8000008 ;# MAS2
WSPR 627 0xF800003f ;# MAS3

;# write tlb entry
WM32 0xfffffffc 0xfffff000
EXEC 0xfffff000
;----------------------------------------------------------------------------------

;##################################################################################
;# move CCSR at 0xE0000000
;# CCSRBAR
;# bit 12 - 23 - BASE_ADDR

WM32 0xFF700000 0x000E0000
;
;##################################################################################

;##################################################################################
;# config BPTR register (Boot Page Translation Register)
;# remove the 4k boot page from 0xFFFFF000 address
;WM32 0xE0000020 0x00000000

;# Invalidate again BR0 to prevent flash data damage in case
;# the boot sequencer re-enables CS0 access
;WM32 0xE0005000 0x00001000
;##################################################################################

;##################################################################################
;# configure internal SRAM at 0x40100000
;# L2CTL
;# bit 0 = 0 - L2E: L2 SRAM disabled
;# bit 4-5 = 01 - L2BLKSZ: = 512KB
;# bit 13-15 = 001 - L2SRAM: Block 0 = SRAM 0
WM32 0xE0020000 0x00010000

;# L2SRBAR0
;# bit 0-17 = BASE addr: 0x40100000
WM32 0xE0020100 0x40100000

;# L2CTL
;# bit 0 = 1 - L2E: L2 SRAM enable
;# bit 4-5 = 01 - L2BLKSZ: = 512KB
;# bit 13-15 = 001 - L2SRAM: Block 0 = SRAM 0
WM32 0xE0020000 0x80010000
;##################################################################################

; Setup flash programming workspace in L2SRAM
WM32 0xE0020000 0x68010000 ;L2CTL
WM32 0xE0020100 0xf0000000 ;L2SRBAR0
WM32 0xE0020000 0xA8010000 ;L2CTL
WSPR 63 0xf0000000 ;IVPR to workspace
WSPR 415 0x0001500 ;IVOR15 : Debug exception
WM32 0xf0001500 0x48000000 ;write valid instruction

;##################################################################################
;#
;# Memory Windows
;#
;# 0x00000000 0x3ffffff LAW0 DDR
;# 0xc0000000 0xfffffff LAW1 Local Bus
;#
;##################################################################################

;##################################################################################
;# configure local access windows
;#
;# window 0: DDR = F
;# window 1: Local Bus = 4

;----------------------------------------------------------------------------------
;# LAWBAR0
;# bit 12 - 31 = 0x00000000 - base addr
WM32 0xE0000c08 0x00000000

;# LAWAR0
;# bit 1 = 1 - enable window
;# bit 8-11 = F - DDR
;# bit 26 - 31 = 1GB - size
WM32 0xE0000c10 0x80f0001D
;----------------------------------------------------------------------------------

;----------------------------------------------------------------------------------
;# LAWBAR1
;# bit 12 - 31 = 0xF8000000 - base addr
WM32 0xE0000c28 0x000F8000

;# LAWAR1
;# bit 1 = 1 - enable window
;# bit 8-11 = 4 - local bus
;# bit 26 - 31 = 256MB - size
WM32 0xE0000c30 0x8040001A ;- 1D
;----------------------------------------------------------------------------------
;###################################################################################

;###################################################################################
;#
;# DDR initalization
;#
;### Clocks: CPU: 990 MHz, CCB: 396 MHz, DDR: 198 MHz

;# DDR_SDRAM_CFG 0100 0011 0000 0000 0000 0000 0000 0000
;# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled
;# bit 1 = 1 - SREN enable self refresh during sleep
;# bit 2 = 0 - ECC_EN disable ECC interrupt generation
;# bit 3 = 0 - RD_EN unbuffered DIMMs
;# bit 6 - 7 = 2 - SDRAM_TYPE DDR2 SDRAM
;# bit 10 = 0 - DYN_PWR power management disabled

WM32 0xE0002110 0x43000000

;# configure the appropriate DDR controller registers

;# CS0_BNDS
;# bit 8-15 - starting address
;# bit 24-31 - ending address
WM32 0xE0002000 0x0000000f ; DDR CS0

;# CS0_CONFIG
WM32 0xE0002080 0x80000102

;# TIMING_CFG_0
WM32 0xE0002104 0x00260802

;# TIMING_CFG_1
WM32 0xE0002108 0x38355322

;# TIMING_CFG_2
WM32 0xE000210C 0x039048c7

;# DDR_SDRAM_MODE
WM32 0xE0002118 0x00000432

;# DDR_SDRAM_INTERVAL
WM32 0xE0002124 0x05150100

;# DDR_SDRAM_CFG2
WM32 0xE0002114 0x24000000

;# DDR_SDRAM_CLK_CNTL
WM32 0xE0002130 0x03000000

DELAY 200

;# enable the memory interface
;# DDR_SDRAM_CFG
;# enable the memory interface
WM32 0xE0002110 0xc3000000
;##################################################################################

;##################################################################################
;# configure local bus memory controller

;# CS0 - Flash Bank #0
WM32 0xE0005000 0xf8001001 ;# BR0 base address at 0xF8000000, port
size 16 bit, GPCM, valid
WM32 0xE0005004 0xf8006e65 ;# OR1 64MBytes flash size
;##################################################################################

;WM16 0xf8000AAA 0x5500 ;
;WM16 0xf8000554 0xAA00 ;
;WM16 0xf8000AAA 0x0100 ;
;WM16 0xf8000AAA 0x5500 ;
;WM16 0xf8000554 0xAA00 ;
;WM16 0xf8000AAA 0x0800 ;
;;WM16 0xfbffffff 0x0010 ;WM16 0xf8000000 0x0010 ;

;WM32 0xf8000AAA 0x00AA ;
;WM32 0xf8000554 0x0055 ;
;WM32 0xf8000AAA 0x00A0 ;
;DELAY 2000
;WM32 0xf8000F00 0x5555 ;

[TARGET]
CPUTYPE 8548 ;the CPU type
JTAGCLOCK 0 ;use 16 MHz JTAG clock
STARTUP HALT ;halt core while HRESET is asserted
BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE HWBP ;JTAG or HWBP, HWBP uses a hardware breakpointeraserase
WAKEUP 2000 ;give reset time to complete
POWERUP 5000 ;start delay after power-up detected in ms

[HOST]
IP 10.101.42.16
FILE uboot.bin
FORMAT BIN
LOAD MANUAL ;load code MANUAL or AUTO after reset
DUMP dump.bin
PROMPT ATUM>

[FLASH]
CHIPTYPE MIRRORX16 ;S29GL01GP
CHIPSIZE 0x8000000 ;The size of one flash chip in bytes
BUSWIDTH 16 ;The width of the flash memory bus in
bits (8 | 16 | 32)
;WORKSPACE 0xf0000000 ;workspace in L2SRAM
ERASE 0xf8000000 CHIP; erase chip

[REGS]
FILE $reg8548.def

Thanks!
Robert