[U-Boot-Users] MIPS question

[U-Boot-Users] MIPS question

[Vlad Lungu]

For those who know a little about U-Boot on MIPS:
in include/asm-mips/addrspace.h line 52, there is a

#define UNCACHED_SDRAM(a) PHYSADDR(a)

The question is: shouldn't we use KSEG1ADDR() instead of PHYSADDR()?
If not, this means we have to actually map KUSEG ?

Vlad

[U-Boot-Users] MIPS question

[Shinya Kuribayashi]

Vlad Lungu wrote:
> in include/asm-mips/addrspace.h line 52, there is a
> 
> #define UNCACHED_SDRAM(a) PHYSADDR(a)
> 
> The question is: shouldn't we use KSEG1ADDR() instead of PHYSADDR()?

I think we should. At least my target boards need that change.

http://www.nabble.com/MIPS-cache-management-%28and-build%29-questions.-tf4434068.html#a12651921

note: Wrt dcache_disable() part, please take into account
      Stefan's comment.

Anyway I seriously wonder whether other mips ports work as it is.

thanks,

    Shinya

[U-Boot-Users] MIPS question

[Vlad Lungu]

Shinya Kuribayashi wrote:
> Vlad Lungu wrote:
>   
>> in include/asm-mips/addrspace.h line 52, there is a
>>
>> #define UNCACHED_SDRAM(a) PHYSADDR(a)
>>
>> The question is: shouldn't we use KSEG1ADDR() instead of PHYSADDR()?
>>     
>
> I think we should. At least my target boards need that change.
>
> http://www.nabble.com/MIPS-cache-management-%28and-build%29-questions.-tf4434068.html#a12651921
>   
And what board would that be? Or it's not in the tree?
> note: Wrt dcache_disable() part, please take into account
>       Stefan's comment.
>
> Anyway I seriously wonder whether other mips ports work as it is.
>
>   
<comment mode="AOL"> me too </comment>

The RAM might be mapped at 0 too on some boards, that's why it works with PHYSADDR(). Or people are
simply bootelf-ing Linux, that's why the bug was not catched before (I think the only use of that 
macro is in lib_mips/mips_linux.c i.e. bootm). Note that the Au1x00 boards ( and another one, can't 
remember the name) do 0x20000000|a or something like that, which when you go from KSEG0 (0x8???????)
produces 0xa???????, an address in KSEG1.

Wolfgang, should I submit a patch on this for 1.3.0?

Vlad

[U-Boot-Users] MIPS question

[Tim Braun]

> From: Vlad Lungu <vlad@comsys.ro>
> Shinya Kuribayashi wrote:
> > Vlad Lungu wrote:
> >   
> >> in include/asm-mips/addrspace.h line 52, there is a
> >>
> >> #define UNCACHED_SDRAM(a) PHYSADDR(a)
> >>
> >> The question is: shouldn't we use KSEG1ADDR() instead of 
> PHYSADDR()?
> >>     
> >
> > I think we should. At least my target boards need that change.


> The RAM might be mapped at 0 too on some boards, that's why 
> it works with PHYSADDR(). ...

My code base is unchanged from U-Boot 1.1.1 :

#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
/* We use a 36 bit physical address map here and
   cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else	/* !CONFIG_AU1X00 */
#define UNCACHED_SDRAM(a) PHYSADDR(a)
#endif	/* CONFIG_AU1X00 */

Since the name is uncached, you want an uncached address, so I think we
want

#define UNCACHED_SDRAM(a) KSEG1ADDR(a)

In the Au1x00 based systems (like ours), the SDRAM is generally mapped
to 
physical address 0x80000000, so it works out as valid KSEG0 / KSEG1
addresses.

Tim Braun, Sr. Des. Eng.
LibreStream Technologies
200-55 Rothwell Rd, Winnipeg, R3P 2M5  http://www.librestream.com 

[U-Boot-Users] MIPS question

[Shinya Kuribayashi]

Vlad Lungu wrote:
> Shinya Kuribayashi wrote:
>> Vlad Lungu wrote:
>>  
>>> in include/asm-mips/addrspace.h line 52, there is a
>>>
>>> #define UNCACHED_SDRAM(a) PHYSADDR(a)
>>>
>>> The question is: shouldn't we use KSEG1ADDR() instead of PHYSADDR()?
>>>     
>>
>> I think we should. At least my target boards need that change.
>>
>> http://www.nabble.com/MIPS-cache-management-%28and-build%29-questions.-tf4434068.html#a12651921 
>>
>>   
> And what board would that be? Or it's not in the tree?

It's NEC mips custom board, and is not (will not be) in upstream.
These are VRcore-based or MIPScore-based, not Au1XXX-based.

>> note: Wrt dcache_disable() part, please take into account
>>       Stefan's comment.
>>
>> Anyway I seriously wonder whether other mips ports work as it is.
>>
>>   
> <comment mode="AOL"> me too </comment>
> 
> The RAM might be mapped at 0 too on some boards, that's why it works 
> with PHYSADDR(). Or people are

Hmm.. our board has system RAM physically mapped at zero, but never
works with PHYSADDR(). If TLB uninitialized, we encounter tlb address
error on 0x0 access. Am I miss something?

> simply bootelf-ing Linux, that's why the bug was not catched before (I 
> think the only use of that macro is in lib_mips/mips_linux.c i.e. 

Agreed.

> bootm). Note that the Au1x00 boards ( and another one, can't remember 
> the name) do 0x20000000|a or something like that, which when you go from 
> KSEG0 (0x8???????)
> produces 0xa???????, an address in KSEG1.

True, I think UNCACHED_SDRAM() works only with au1xxx for now.

> Wolfgang, should I submit a patch on this for 1.3.0?

Feel free to add my signed-off-by:

Singed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>

thanks,

    Shinya