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* [U-Boot-Users] [GIT PULL] MIPS updates
@ 2007-10-21 14:31 Shinya Kuribayashi
  2007-11-01 21:54 ` Wolfgang Denk
  0 siblings, 1 reply; 18+ messages in thread
From: Shinya Kuribayashi @ 2007-10-21 14:31 UTC (permalink / raw)
  To: u-boot

Dear Wolfgang,

please pull MIPS updates.

The following changes since commit 5441f61a3d8b7034f19fc1361183e936198e6dbb:
  Detlev Zundel (1):
        Fix two typos.

are available in the git repository at:

  git://www.denx.de/git/u-boot-mips.git master

Shinya Kuribayashi (5):
      [MIPS] u-boot.lds: Remove duplicated .sdata section
      [MIPS] u-boot.lds: Fix __got_start and __got_end
      [MIPS] Fix $gp usage
      [MIPS] u-boot.lds: Define _gp in a standard manner
      [MIPS] Add PIC-related switches to PLATFORM_{CPP,LD}FLAGS and cleanup

Vlad Lungu (1):
      [MIPS] Fix UNCACHED_SDRAM

 board/dbau1x00/u-boot.lds    |   14 +++++++-------
 board/gth2/u-boot.lds        |   14 +++++++-------
 board/incaip/u-boot.lds      |   14 +++++++-------
 board/pb1x00/u-boot.lds      |   14 +++++++-------
 board/purple/u-boot.lds      |   14 +++++++-------
 board/tb0229/u-boot.lds      |   14 +++++++-------
 cpu/mips/config.mk           |    2 +-
 cpu/mips/start.S             |   19 +++++++++++++------
 examples/mips.lds            |   14 +++++++-------
 include/asm-mips/addrspace.h |    2 +-
 mips_config.mk               |   25 +++++++++++++++++++++++++
 11 files changed, 89 insertions(+), 57 deletions(-)


thanks,

  Shinya

^ permalink raw reply	[flat|nested] 18+ messages in thread
* [U-Boot-Users] [GIT PULL] MIPS updates
@ 2007-11-17 12:15 Shinya Kuribayashi
  2007-11-18  0:28 ` Wolfgang Denk
  0 siblings, 1 reply; 18+ messages in thread
From: Shinya Kuribayashi @ 2007-11-17 12:15 UTC (permalink / raw)
  To: u-boot

Dear Wolfgang,

please pull MIPS updates. These patches contain build fixes, style
cleanups and trivial optimizations. I also note that the results of
MAKEALL mips/mips_el are good for the next release.


The following changes since commit 5947f6999aafa7c54c1390983d264a8463dfea8e:
  Wolfgang Denk (1):
        Update CHANGELOIG, prepare for -rc4

are available in the git repository at:

  git://www.denx.de/git/u-boot-mips.git master

Shinya Kuribayashi (9):
      [MIPS] u-boot.lds: Cleanup __u_boot_cmd_{start,end}
      [MIPS] pb1000: Replace obsolete memsetup.S with lowlevel_init.S
      MAKEALL: Added missing pb1000 board
      [MIPS] au1x00_eth.c: Fix au1x00_miiphy_{read,write} build error
      [MIPS] au1x00_eth.c: Fixed a warning on pb1000 build.
      [MIPS] gth2.c: Fix a warning on gth2 build.
      [MIPS] MIPS 4K core: Coding style cleanups
      [MIPS] Remove useless instructions for initializing $gp.
      [MIPS] cpu/mips/config.mk: Fix GNU assembler minor version picker

 MAKEALL                                      |    1 +
 board/dbau1x00/u-boot.lds                    |    9 +-
 board/gth2/gth2.c                            |    2 +-
 board/gth2/u-boot.lds                        |    8 +-
 board/incaip/u-boot.lds                      |    9 +-
 board/pb1x00/Makefile                        |    2 +-
 board/pb1x00/{memsetup.S => lowlevel_init.S} |    4 +-
 board/pb1x00/u-boot.lds                      |    8 +-
 board/purple/u-boot.lds                      |    9 +-
 board/tb0229/u-boot.lds                      |    9 +-
 cpu/mips/au1x00_eth.c                        |  118 +++++++++++++-------------
 cpu/mips/cache.S                             |   30 +++----
 cpu/mips/config.mk                           |    3 +-
 cpu/mips/cpu.c                               |    6 +-
 cpu/mips/start.S                             |   50 +++++------
 15 files changed, 133 insertions(+), 135 deletions(-)
 rename board/pb1x00/{memsetup.S => lowlevel_init.S} (99%)


thanks,

  Shinya

^ permalink raw reply	[flat|nested] 18+ messages in thread
* [U-Boot-Users] [GIT PULL] MIPS updates
@ 2008-01-16 23:42 Shinya Kuribayashi
  2008-01-23 13:38 ` Wolfgang Denk
  0 siblings, 1 reply; 18+ messages in thread
From: Shinya Kuribayashi @ 2008-01-16 23:42 UTC (permalink / raw)
  To: u-boot

Dear Wolfgang,

please pull MIPS updates. It's a interesting QEMU target.

The following changes since commit 4c9e98ace78e7de972adf7da7135a46ec0a4ee7e:
  Wolfgang Denk (1):
        Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xx

are available in the git repository at:

  git://www.denx.de/git/u-boot-mips.git master

Jean-Christophe PLAGNIOL-VILLARD (1):
      qemu-mips: active HUSH PARSER, AUTO_COMPLETE and CMDLINE_EDITING

Vlad Lungu (1):
      MIPS:Target support for qemu -M mips

 MAINTAINERS                     |    3 +
 MAKEALL                         |    1 +
 Makefile                        |    6 ++
 board/qemu-mips/Makefile        |   45 ++++++++++
 board/qemu-mips/README          |   11 +++
 board/qemu-mips/config.mk       |   10 +++
 board/qemu-mips/flash.c         |   40 +++++++++
 board/qemu-mips/lowlevel_init.S |   41 ++++++++++
 board/qemu-mips/qemu-mips.c     |   89 ++++++++++++++++++++
 board/qemu-mips/u-boot.lds      |   72 +++++++++++++++++
 include/configs/qemu-mips.h     |  169 +++++++++++++++++++++++++++++++++++++++
 11 files changed, 487 insertions(+), 0 deletions(-)
 create mode 100644 board/qemu-mips/Makefile
 create mode 100644 board/qemu-mips/README
 create mode 100644 board/qemu-mips/config.mk
 create mode 100644 board/qemu-mips/flash.c
 create mode 100644 board/qemu-mips/lowlevel_init.S
 create mode 100644 board/qemu-mips/qemu-mips.c
 create mode 100644 board/qemu-mips/u-boot.lds
 create mode 100644 include/configs/qemu-mips.h

^ permalink raw reply	[flat|nested] 18+ messages in thread
* [U-Boot-Users] [GIT PULL] MIPS updates
@ 2008-03-25 13:04 Shinya Kuribayashi
  0 siblings, 0 replies; 18+ messages in thread
From: Shinya Kuribayashi @ 2008-03-25 13:04 UTC (permalink / raw)
  To: u-boot

Dear Wolfgang,

please pull MIPS updates. These patches contain various fixes, headers'
update and cleanups. MAKEALL results is good (big-endian only).

The following changes since commit 0d48926c87ec96f974a6ac4034f4a2f2eab3255f:
  Yuri Tikhonov (1):
        lwmon5 SYSMON POST: fix backlight control

are available in the git repository at:

  git://www.denx.de/git/u-boot-mips.git master

Shinya Kuribayashi (13):
      [MIPS] Request for the 'mips_cache_lock()' removal
      [MIPS] asm headers' updates
      [MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macros
      [MIPS] Replace memory clearance code with f_fill64
      [MIPS] Fix I-/D-cache initialization loops
      [MIPS] Implement flush_cache()
      [MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init()
      [MIPS] Initialize CP0 Cause before setting up CP0 Status register
      [MIPS] Cleanup CP0 Status initialization
      [MIPS] Introduce _machine_restart
      [MIPS] Fix dcache_status()
      [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB
      [MIPS] Move gth2_config from ARM section to MIPS

 Makefile                     |   10 +-
 board/incaip/incaip.c        |    6 +
 board/incaip/lowlevel_init.S |    6 +
 board/purple/purple.c        |    8 +
 board/tb0229/tb0229.c        |    9 +-
 cpu/mips/cache.S             |  209 +++++++++++++--------
 cpu/mips/cpu.c               |   35 +++-
 cpu/mips/start.S             |   48 +++--
 include/asm-mips/asm.h       |  409 ++++++++++++++++++++++++++++++++++++++++++
 include/asm-mips/byteorder.h |   60 ++++++-
 include/asm-mips/cachectl.h  |   10 +-
 include/asm-mips/cacheops.h  |   78 ++++++--
 include/asm-mips/isadep.h    |    5 +-
 include/asm-mips/processor.h |  249 ++++++--------------------
 include/asm-mips/ptrace.h    |   67 ++++----
 include/asm-mips/reboot.h    |   14 ++
 include/asm-mips/reg.h       |  134 ++++++++++----
 include/asm-mips/regdef.h    |  126 +++++++++----
 include/asm-mips/types.h     |   30 +++-
 19 files changed, 1058 insertions(+), 455 deletions(-)
 create mode 100644 include/asm-mips/asm.h
 create mode 100644 include/asm-mips/reboot.h

^ permalink raw reply	[flat|nested] 18+ messages in thread
* [U-Boot-Users] [GIT PULL] MIPS updates
@ 2008-05-02  3:33 Shinya Kuribayashi
  2008-05-03 22:10 ` Wolfgang Denk
  0 siblings, 1 reply; 18+ messages in thread
From: Shinya Kuribayashi @ 2008-05-02  3:33 UTC (permalink / raw)
  To: u-boot

Dear Wolfgang,

please pull MIPS updates. 2 patches are there. One fixes a build failure
caused by absence of dcache_enable(). The other is for a better handling
of gas minor version (this isn't a kind of bug fix, but I'd like to push
this for 1.3.3 release. Ok?).

Each patch has not been posted to u-boot-users yet, so they will follow
this mail. Please review (and apply).

thanks,

  Shinya

---
The following changes since commit 50f93d30dae3c5d888aa244d964ccd77be9b1c0c:
  Wolfgang Denk (1):
        Merge branch 'master' of git+ssh://10.10.0.7/home/wd/git/u-boot/master

are available in the git repository at:

  git://git.denx.de/u-boot-mips.git master

Shinya Kuribayashi (2):
      [MIPS] cpu/mips/cache.S: Add dcache_enable
      [MIPS] cpu/mips/config.mk: Fix GNU assembler minor version picker

 cpu/mips/cache.S   |   16 ++++++++++++++++
 cpu/mips/config.mk |    2 +-
 2 files changed, 17 insertions(+), 1 deletions(-)

^ permalink raw reply	[flat|nested] 18+ messages in thread
* [U-Boot-Users] [GIT PULL] MIPS updates
@ 2008-05-06  4:34 Shinya Kuribayashi
  2008-05-09 20:20 ` Wolfgang Denk
  0 siblings, 1 reply; 18+ messages in thread
From: Shinya Kuribayashi @ 2008-05-06  4:34 UTC (permalink / raw)
  To: u-boot

Dear Wolfgang,

please pull MIPS update.
Patch attached below. This will fix build warnings on cache.S.

thanks,

  Shinya

---

The following changes since commit 908261f3fdb418091d8c60bfbd7eb85e5869b579:
  Wolfgang Denk (1):
        Merge branch 'master' of git+ssh://10.10.0.7/home/wd/git/u-boot/master

are available in the git repository at:

  git://git.denx.de/u-boot-mips.git master

Shinya Kuribayashi (1):
      [MIPS] cpu/mips/cache.S: Fix build warning

 cpu/mips/cache.S |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

---

[MIPS] cpu/mips/cache.S: Fix build warning

Some old GNU assemblers, such as v2.14 (ELDK 3.1.1), v2.16 (ELDK 4.1.0),
warns illegal global symbol references by bal (and jal also) instruction.
This does not happen with the latest binutils v2.18.

Here's an example on gth2_config:

mips_4KC-gcc  -D__ASSEMBLY__ -g  -Os   -D__KERNEL__ -DTEXT_BASE=0x90000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isy
stem /opt/eldk311/usr/bin/../lib/gcc-lib/mips-linux/3.3.3/include -pipe  -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4k
c -EB -c -o cache.o cache.S
cache.S: Assembler messages:
cache.S:243: Warning: Pretending global symbol used as branch target is local.
cache.S:250: Warning: Pretending global symbol used as branch target is local.

In principle, gas might be sensitive to global symbol references in PIC
code because they should be processed through GOT (global offset table).
But if `bal' instruction is used, it results in PC-based offset jump.
This is the cause of this warning.

In practice, we know it doesn't matter whether PC-based reference or GOT-
based. As for this case, both will work before/after relocation. But let's
fix the code.

This patch explicitly sets up a target address, then jump there.
Here's an example of disassembled code before/after this patch.

 90000668:       1485ffef        bne     a0,a1,90000628 <mips_cache_reset+0x20>
 9000066c:       ac80fffc        sw      zero,-4(a0)
 90000670:       01402821        move    a1,t2
-90000674:       0411ffba        bal     90000560 <mips_init_icache>
-90000678:       01803021        move    a2,t4
-9000067c:       01602821        move    a1,t3
-90000680:       0411ffcc        bal     900005b4 <mips_init_dcache>
-90000684:       01a03021        move    a2,t5
-90000688:       03000008        jr      t8
-9000068c:       00000000        nop
+90000674:       01803021        move    a2,t4
+90000678:       8f8f83ec        lw      t7,-31764(gp)
+9000067c:       01e0f809        jalr    t7
+90000680:       00000000        nop
+90000684:       01602821        move    a1,t3
+90000688:       01a03021        move    a2,t5
+9000068c:       8f8f81e0        lw      t7,-32288(gp)
+90000690:       01e0f809        jalr    t7
+90000694:       00000000        nop
+90000698:       03000008        jr      t8
+9000069c:       00000000        nop

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
---

 cpu/mips/cache.S |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)


diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 428d251..1b0efc3 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -240,14 +240,16 @@ NESTED(mips_cache_reset, 0, ra)
 	 */
 	move	a1, t2
 	move	a2, t4
-	bal	mips_init_icache
+	PTR_LA	t7, mips_init_icache
+	jalr	t7
 
 	/*
 	 * then initialize D-cache.
 	 */
 	move	a1, t3
 	move	a2, t5
-	bal	mips_init_dcache
+	PTR_LA	t7, mips_init_dcache
+	jalr	t7
 
 	jr	RA
 	END(mips_cache_reset)

^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [U-Boot-Users] [GIT PULL] MIPS updates
@ 2008-05-22 15:29 Shinya Kuribayashi
  0 siblings, 0 replies; 18+ messages in thread
From: Shinya Kuribayashi @ 2008-05-22 15:29 UTC (permalink / raw)
  To: u-boot

Dear Wolfgang,

please pull MIPS updates. nand_init and spi_init will be added.

---

The following changes since commit 2c8d41969b47eb0b973912830c58689b2ba0e50a:
  Wolfgang Denk (1):
        Merge branch 'master' of git://git.denx.de/u-boot-testing

are available in the git repository at:

  git://git.denx.de/u-boot-mips.git master

Jason McMullan (2):
      [MIPS] lib_mips/board.c: Add nand_init
      mips: If CONFIG_CMD_SPI is defined, call spi_init()

 lib_mips/board.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/lib_mips/board.c b/lib_mips/board.c
index 1645f2c..532550b 100644
--- a/lib_mips/board.c
+++ b/lib_mips/board.c
@@ -28,6 +28,8 @@
 #include <version.h>
 #include <net.h>
 #include <environment.h>
+#include <nand.h>
+#include <spi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -416,6 +418,17 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	}
 #endif
 
+#ifdef CONFIG_CMD_NAND
+	puts ("NAND:  ");
+	nand_init ();		/* go init the NAND */
+#endif
+
+#ifdef CONFIG_CMD_SPI
+	puts ("SPI:   ");
+	spi_init ();		/* go init the SPI */
+	puts ("ready\n");
+#endif
+
 #if defined(CONFIG_MISC_INIT_R)
 	/* miscellaneous platform dependent initialisations */
 	misc_init_r ();

^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [U-Boot-Users] [GIT PULL] MIPS updates
@ 2008-06-07  1:19 Shinya Kuribayashi
  2008-06-11 20:51 ` Wolfgang Denk
  0 siblings, 1 reply; 18+ messages in thread
From: Shinya Kuribayashi @ 2008-06-07  1:19 UTC (permalink / raw)
  To: u-boot

Please pull MIPS updates to pick up the following patches.

The following changes since commit 8155efbd7ae9c65564ca98affe94631d612ae088:
  Wolfgang Denk (1):
        Merge branch 'master' of ssh://mercury/home/wd/git/u-boot/master

are available in the git repository at:

  git://git.denx.de/u-boot-mips.git master

Shinya Kuribayashi (8):
      [MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros
      [MIPS] lib_mips/time.c: Fix udelay
      [MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routines
      [MIPS] Kill unused <version.h> inclusions
      [MIPS] mips_config.mk: Misc fixes
      [MIPS] Update <asm/addrspace.h> header
      [MIPS] Rename Alchemy processor configs into CONFIGO_SOC_*
      [MIPS] cpu/mips/Makefile: Split [CS]OBJS onto separate lines

 board/dbau1x00/lowlevel_init.S  |    1 -
 board/gth2/gth2.c               |    2 +-
 board/gth2/lowlevel_init.S      |    1 -
 board/incaip/incaip.c           |    2 +-
 board/incaip/lowlevel_init.S    |    1 -
 board/pb1x00/lowlevel_init.S    |    1 -
 board/purple/lowlevel_init.S    |    1 -
 board/purple/purple.c           |   14 ++--
 board/qemu-mips/lowlevel_init.S |    1 -
 board/tb0229/lowlevel_init.S    |    1 -
 board/tb0229/vr4131-pci.c       |   56 ++++++------
 cpu/mips/Makefile               |   15 ++--
 cpu/mips/asc_serial.c           |    3 -
 cpu/mips/au1x00_eth.c           |   12 +--
 cpu/mips/au1x00_serial.c        |    4 -
 cpu/mips/au1x00_usb_ohci.c      |    2 +-
 cpu/mips/cache.S                |    7 +-
 cpu/mips/incaip_wdt.S           |    1 -
 cpu/mips/start.S                |    1 -
 drivers/net/inca-ip_sw.c        |   28 +++---
 include/asm-mips/addrspace.h    |  173 +++++++++++++++++++++++++++++----------
 include/asm-mips/au1x00.h       |    6 +-
 include/asm-mips/io.h           |    4 +-
 include/configs/dbau1x00.h      |   14 ++--
 include/configs/gth2.h          |    8 +-
 include/configs/incaip.h        |    4 +-
 include/configs/pb1x00.h        |   12 ++-
 include/configs/purple.h        |    3 +-
 include/configs/qemu-mips.h     |    4 +-
 include/configs/tb0229.h        |    4 +-
 lib_mips/time.c                 |   57 ++++++-------
 mips_config.mk                  |    7 +-
 32 files changed, 263 insertions(+), 187 deletions(-)

diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
index 27b51f7..13e6bfc 100644
--- a/board/dbau1x00/lowlevel_init.S
+++ b/board/dbau1x00/lowlevel_init.S
@@ -1,7 +1,6 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index 9bc4d3f..3e56678 100644
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -36,7 +36,7 @@ static int wdi_status = 0;
 #define SDRAM_SIZE ((64*1024*1024)-(12*4096))
 
 
-#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096))
+#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
 
 void inline log_serial_char(char c){
 	char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S
index bf615c1..4c4f0eb 100644
--- a/board/gth2/lowlevel_init.S
+++ b/board/gth2/lowlevel_init.S
@@ -1,7 +1,6 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index c624b3d..dc51373 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -63,7 +63,7 @@ long int initdram(int board_type)
 
 		/* Can't probe for RAM size unless we are running from Flash.
 		 */
-	if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1))
+	if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
 	{
 		return max_sdram_size();
 	}
diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S
index 08f7f21..fe525ec 100644
--- a/board/incaip/lowlevel_init.S
+++ b/board/incaip/lowlevel_init.S
@@ -23,7 +23,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 
 
diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S
index 98bb394..b145e43 100644
--- a/board/pb1x00/lowlevel_init.S
+++ b/board/pb1x00/lowlevel_init.S
@@ -1,7 +1,6 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>
diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S
index b9d03fc..1bd3edb 100644
--- a/board/purple/lowlevel_init.S
+++ b/board/purple/lowlevel_init.S
@@ -23,7 +23,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 
 #define MC_IOGP	0xBF800800
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 89cb906..72d5734 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -85,16 +85,16 @@ static void sdram_timing_init (ulong size)
 			while (p4 < 32 && done == 0) {
 			    WRITE_MC_IOGP_1;
 
-			    for (addr = KSEG1 + 0x4000;
-				 addr < KSEG1ADDR (size);
+			    for (addr = CKSEG1 + 0x4000;
+				 addr < CKSEG1ADDR (size);
 				 addr = addr + 4) {
 					*(uint *) addr = 0xaa55aa55;
 			    }
 
 			    pass = 1;
 
-			    for (addr = KSEG1 + 0x4000;
-				 addr < KSEG1ADDR (size) && pass == 1;
+			    for (addr = CKSEG1 + 0x4000;
+				 addr < CKSEG1ADDR (size) && pass == 1;
 				 addr = addr + 4) {
 					if (*(uint *) addr != 0xaa55aa55)
 						pass = 0;
@@ -138,7 +138,7 @@ long int initdram(int board_type)
 	ulong	size	= (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
 	void (*  sdram_init) (ulong);
 
-	sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init);
+	sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
 
 	sdram_init(0x10000);
 
@@ -260,14 +260,14 @@ void copy_code (ulong dest_addr)
 	/* flush caches
 	 */
 
-	start = KSEG0;
+	start = CKSEG0;
 	end = start + CFG_DCACHE_SIZE;
 	while(start < end) {
 		cache_unroll(start,Index_Writeback_Inv_D);
 		start += CFG_CACHELINE_SIZE;
 	}
 
-	start = KSEG0;
+	start = CKSEG0;
 	end = start + CFG_ICACHE_SIZE;
 	while(start < end) {
 		cache_unroll(start,Index_Invalidate_I);
diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S
index 836e027..b0f7072 100644
--- a/board/qemu-mips/lowlevel_init.S
+++ b/board/qemu-mips/lowlevel_init.S
@@ -1,7 +1,6 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
 
diff --git a/board/tb0229/lowlevel_init.S b/board/tb0229/lowlevel_init.S
index df31806..5fce856 100644
--- a/board/tb0229/lowlevel_init.S
+++ b/board/tb0229/lowlevel_init.S
@@ -10,7 +10,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 
 
diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c
index 0ee4bf3..4c91923 100644
--- a/board/tb0229/vr4131-pci.c
+++ b/board/tb0229/vr4131-pci.c
@@ -13,34 +13,34 @@
 #include <pci.h>
 #include <asm/addrspace.h>
 
-#define VR4131_PCIMMAW1REG	(volatile unsigned int*)(KSEG1 + 0x0f000c00)
-#define VR4131_PCIMMAW2REG	(volatile unsigned int*)(KSEG1 + 0x0f000c04)
-#define VR4131_PCITAW1REG	(volatile unsigned int*)(KSEG1 + 0x0f000c08)
-#define VR4131_PCITAW2REG	(volatile unsigned int*)(KSEG1 + 0x0f000c0c)
-#define VR4131_PCIMIOAWREG	(volatile unsigned int*)(KSEG1 + 0x0f000c10)
-#define VR4131_PCICONFDREG	(volatile unsigned int*)(KSEG1 + 0x0f000c14)
-#define VR4131_PCICONFAREG	(volatile unsigned int*)(KSEG1 + 0x0f000c18)
-#define VR4131_PCIMAILREG	(volatile unsigned int*)(KSEG1 + 0x0f000c1c)
-#define VR4131_BUSERRADREG	(volatile unsigned int*)(KSEG1 + 0x0f000c24)
-#define VR4131_INTCNTSTAREG	(volatile unsigned int*)(KSEG1 + 0x0f000c28)
-#define VR4131_PCIEXACCREG	(volatile unsigned int*)(KSEG1 + 0x0f000c2c)
-#define VR4131_PCIRECONTREG	(volatile unsigned int*)(KSEG1 + 0x0f000c30)
-#define VR4131_PCIENREG		(volatile unsigned int*)(KSEG1 + 0x0f000c34)
-#define VR4131_PCICLKSELREG	(volatile unsigned int*)(KSEG1 + 0x0f000c38)
-#define VR4131_PCITRDYREG	(volatile unsigned int*)(KSEG1 + 0x0f000c3c)
-#define VR4131_PCICLKRUNREG	(volatile unsigned int*)(KSEG1 + 0x0f000c60)
-#define VR4131_PCIHOSTCONFIG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
-#define VR4131_VENDORIDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
-#define VR4131_DEVICEIDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
-#define VR4131_COMMANDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d04)
-#define VR4131_STATUSREG	(volatile unsigned int*)(KSEG1 + 0x0f000d04)
-#define VR4131_REVREG		(volatile unsigned int*)(KSEG1 + 0x0f000d08)
-#define VR4131_CLASSREG		(volatile unsigned int*)(KSEG1 + 0x0f000d08)
-#define VR4131_CACHELSREG	(volatile unsigned int*)(KSEG1 + 0x0f000d0c)
-#define VR4131_LATTIMERRG	(volatile unsigned int*)(KSEG1 + 0x0f000d0c)
-#define VR4131_MAILBAREG	(volatile unsigned int*)(KSEG1 + 0x0f000d10)
-#define VR4131_PCIMBA1REG	(volatile unsigned int*)(KSEG1 + 0x0f000d14)
-#define VR4131_PCIMBA2REG	(volatile unsigned int*)(KSEG1 + 0x0f000d18)
+#define VR4131_PCIMMAW1REG	(volatile unsigned int *)(CKSEG1 + 0x0f000c00)
+#define VR4131_PCIMMAW2REG	(volatile unsigned int *)(CKSEG1 + 0x0f000c04)
+#define VR4131_PCITAW1REG	(volatile unsigned int *)(CKSEG1 + 0x0f000c08)
+#define VR4131_PCITAW2REG	(volatile unsigned int *)(CKSEG1 + 0x0f000c0c)
+#define VR4131_PCIMIOAWREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c10)
+#define VR4131_PCICONFDREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c14)
+#define VR4131_PCICONFAREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c18)
+#define VR4131_PCIMAILREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c1c)
+#define VR4131_BUSERRADREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c24)
+#define VR4131_INTCNTSTAREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c28)
+#define VR4131_PCIEXACCREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c2c)
+#define VR4131_PCIRECONTREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c30)
+#define VR4131_PCIENREG		(volatile unsigned int *)(CKSEG1 + 0x0f000c34)
+#define VR4131_PCICLKSELREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c38)
+#define VR4131_PCITRDYREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c3c)
+#define VR4131_PCICLKRUNREG	(volatile unsigned int *)(CKSEG1 + 0x0f000c60)
+#define VR4131_PCIHOSTCONFIG	(volatile unsigned int *)(CKSEG1 + 0x0f000d00)
+#define VR4131_VENDORIDREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d00)
+#define VR4131_DEVICEIDREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d00)
+#define VR4131_COMMANDREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d04)
+#define VR4131_STATUSREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d04)
+#define VR4131_REVREG		(volatile unsigned int *)(CKSEG1 + 0x0f000d08)
+#define VR4131_CLASSREG		(volatile unsigned int *)(CKSEG1 + 0x0f000d08)
+#define VR4131_CACHELSREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
+#define VR4131_LATTIMERRG	(volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
+#define VR4131_MAILBAREG	(volatile unsigned int *)(CKSEG1 + 0x0f000d10)
+#define VR4131_PCIMBA1REG	(volatile unsigned int *)(CKSEG1 + 0x0f000d14)
+#define VR4131_PCIMBA2REG	(volatile unsigned int *)(CKSEG1 + 0x0f000d18)
 
 /*#define VR41XX_PCIIRQ_OFFSET    (VR41XX_IRQ_MAX + 1)	*/
 /*#define VR41XX_PCIIRQ_MAX       (VR41XX_IRQ_MAX + 12)	*/
diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile
index 92dcc16..5091781 100644
--- a/cpu/mips/Makefile
+++ b/cpu/mips/Makefile
@@ -25,13 +25,16 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).a
 
-START	= start.o
-COBJS	= asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \
-	  cpu.o interrupts.o incaip_clock.o
-SOBJS	= incaip_wdt.o cache.o
+SOBJS-y	= cache.o
+COBJS-y	= cpu.o interrupts.o
 
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+SOBJS-$(CONFIG_INCA_IP)	+= incaip_wdt.o
+COBJS-$(CONFIG_INCA_IP)	+= asc_serial.o incaip_clock.o
+COBJS-$(CONFIG_PURPLE)	+= asc_serial.o
+COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 START	:= $(addprefix $(obj),$(START))
 
 all:	$(obj).depend $(START) $(LIB)
diff --git a/cpu/mips/asc_serial.c b/cpu/mips/asc_serial.c
index 3498b61..be686c2 100644
--- a/cpu/mips/asc_serial.c
+++ b/cpu/mips/asc_serial.c
@@ -4,8 +4,6 @@
 
 #include <config.h>
 
-#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP)
-
 #ifdef CONFIG_PURPLE
 #define	serial_init	asc_serial_init
 #define	serial_putc	asc_serial_putc
@@ -368,4 +366,3 @@ int serial_tstc (void)
 
     return res;
 }
-#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */
diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c
index d70c5fe..d0cf8e0 100644
--- a/cpu/mips/au1x00_eth.c
+++ b/cpu/mips/au1x00_eth.c
@@ -23,8 +23,6 @@
  */
 #include <config.h>
 
-#ifdef CONFIG_AU1X00
-
 #if defined(CFG_DISCOVER_PHY)
 #error "PHY not supported yet"
 /* We just assume that we are running 100FD for now */
@@ -33,20 +31,20 @@
 
 /* I assume ethernet behaves like au1000 */
 
-#ifdef CONFIG_AU1000
+#ifdef CONFIG_SOC_AU1000
 /* Base address differ between cpu:s */
 #define ETH0_BASE AU1000_ETH0_BASE
 #define MAC0_ENABLE AU1000_MAC0_ENABLE
 #else
-#ifdef CONFIG_AU1100
+#ifdef CONFIG_SOC_AU1100
 #define ETH0_BASE AU1100_ETH0_BASE
 #define MAC0_ENABLE AU1100_MAC0_ENABLE
 #else
-#ifdef CONFIG_AU1500
+#ifdef CONFIG_SOC_AU1500
 #define ETH0_BASE AU1500_ETH0_BASE
 #define MAC0_ENABLE AU1500_MAC0_ENABLE
 #else
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
 #define ETH0_BASE AU1550_ETH0_BASE
 #define MAC0_ENABLE AU1550_MAC0_ENABLE
 #else
@@ -307,5 +305,3 @@ int au1x00_enet_initialize(bd_t *bis){
 
 	return 1;
 }
-
-#endif /* CONFIG_AU1X00 */
diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c
index 42c668e..6309794 100644
--- a/cpu/mips/au1x00_serial.c
+++ b/cpu/mips/au1x00_serial.c
@@ -26,9 +26,6 @@
  */
 
 #include <config.h>
-
-#ifdef CONFIG_AU1X00
-
 #include <common.h>
 #include <asm/au1x00.h>
 
@@ -132,4 +129,3 @@ int serial_tstc (void)
 	}
 	return 0;
 }
-#endif /* CONFIG_SERIAL_AU1X00 */
diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c
index dbf72dc..1ca8aaf 100644
--- a/cpu/mips/au1x00_usb_ohci.c
+++ b/cpu/mips/au1x00_usb_ohci.c
@@ -35,7 +35,7 @@
 
 #include <config.h>
 
-#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI)
+#ifdef CONFIG_USB_OHCI
 
 /* #include <pci.h> no PCI on the AU1x00 */
 
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 1b0efc3..ee5d411 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -23,7 +23,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/asm.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
@@ -41,7 +40,7 @@
  */
 #define MIPS_MAX_CACHE_SIZE	0x10000
 
-#define INDEX_BASE	KSEG0
+#define INDEX_BASE	CKSEG0
 
 	.macro	cache_op op addr
 	.set	push
@@ -219,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra)
 	/*
 	 * Now clear that much memory starting from zero.
 	 */
-	PTR_LI		a0, KSEG1
+	PTR_LI		a0, CKSEG1
 	PTR_ADDU	a1, a0, v0
 2:	PTR_ADDIU	a0, 64
 	f_fill64	a0, -64, zero
@@ -319,7 +318,7 @@ LEAF(dcache_enable)
 	.globl	mips_cache_lock
 	.ent	mips_cache_lock
 mips_cache_lock:
-	li	a1, K0BASE - CACHE_LOCK_SIZE
+	li	a1, CKSEG0 - CACHE_LOCK_SIZE
 	addu	a0, a1
 	li	a2, CACHE_LOCK_SIZE
 	li	a3, CFG_CACHELINE_SIZE
diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S
index 329386b..3ade3cd 100644
--- a/cpu/mips/incaip_wdt.S
+++ b/cpu/mips/incaip_wdt.S
@@ -24,7 +24,6 @@
 
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 
 
diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index d881879..09e4aab 100644
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -23,7 +23,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
 
diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c
index e4aaed6..a079b60 100644
--- a/drivers/net/inca-ip_sw.c
+++ b/drivers/net/inca-ip_sw.c
@@ -234,7 +234,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
 	/* Initialize the descriptor rings.
 	 */
 	for (i = 0; i < NUM_RX_DESC; i++) {
-		inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
+		inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
 		memset(rx_desc, 0, sizeof(rx_ring[i]));
 
 		/* Set maximum size of receive buffer.
@@ -252,14 +252,14 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
 			/* Let the last descriptor point to the first
 			 * one.
 			 */
-			rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
+			rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
 		} else {
 			/* Set the address of the next descriptor.
 			 */
-			rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
+			rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
 		}
 
-		rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]);
+		rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
 	}
 
 #if 0
@@ -268,7 +268,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
 #endif
 
 	for (i = 0; i < NUM_TX_DESC; i++) {
-		inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
+		inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
 
 		memset(tx_desc, 0, sizeof(tx_ring[i]));
 
@@ -282,11 +282,11 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
 				/* Let the last descriptor point to the
 				 * first one.
 				 */
-			tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
+			tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
 		} else {
 				/* Set the address of the next descriptor.
 				 */
-			tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
+			tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
 		}
 	}
 
@@ -346,7 +346,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
 	int		       res	= -1;
 	u32		       command;
 	u32		       regValue;
-	inca_tx_descriptor_t * tx_desc	= KSEG1ADDR(&tx_ring[tx_new]);
+	inca_tx_descriptor_t * tx_desc	= (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
 
 #if 0
 	printf("Entered inca_switch_send()\n");
@@ -365,7 +365,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
 	}
 
 	if (tx_old_hold >= 0) {
-		KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
+		((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
 	}
 	tx_old_hold = tx_hold;
 
@@ -376,7 +376,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
 	tx_desc->TxDataPtr = (u32)packet;
 	tx_desc->params.field.NBA = length;
 
-	KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
+	((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
 
 	tx_hold = tx_new;
 	tx_new	= (tx_new + 1) % NUM_TX_DESC;
@@ -397,7 +397,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
 	DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
 
 #if 1
-	for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
+	for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
 		if (i >= TOUT_LOOP) {
 			printf("%s: tx buffer not ready\n", dev->name);
 			goto Done;
@@ -423,7 +423,7 @@ static int inca_switch_recv(struct eth_device *dev)
 #endif
 
 	for (;;) {
-		rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
+		rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
 
 		if (rx_desc->status.field.C == 0) {
 			break;
@@ -456,7 +456,7 @@ static int inca_switch_recv(struct eth_device *dev)
 #if 0
 			printf("Received %d bytes\n", length);
 #endif
-			NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4);
+			NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
 		} else {
 #if 1
 			printf("Zero length!!!\n");
@@ -464,7 +464,7 @@ static int inca_switch_recv(struct eth_device *dev)
 		}
 
 
-		KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0;
+		((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
 
 		rx_hold = rx_new;
 
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 0e6abd7..3a1e6d6 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -3,16 +3,94 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1996 by Ralf Baechle
- * Copyright (C) 2000 by Maciej W. Rozycki
- *
- * Defitions for the address spaces of the MIPS CPUs.
+ * Copyright (C) 1996, 99 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ADDRSPACE_H
+#define _ASM_ADDRSPACE_H
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ATYPE_
+#define _ATYPE32_
+#define _ATYPE64_
+#define _CONST64_(x)	x
+#else
+#define _ATYPE_		__PTRDIFF_TYPE__
+#define _ATYPE32_	int
+#define _ATYPE64_	__s64
+#ifdef CONFIG_64BIT
+#define _CONST64_(x)	x ## L
+#else
+#define _CONST64_(x)	x ## LL
+#endif
+#endif
+
+/*
+ *  32-bit MIPS address spaces
+ */
+#ifdef __ASSEMBLY__
+#define _ACAST32_
+#define _ACAST64_
+#else
+#define _ACAST32_		(_ATYPE_)(_ATYPE32_)	/* widen if necessary */
+#define _ACAST64_		(_ATYPE64_)		/* do _not_ narrow */
+#endif
+
+/*
+ * Returns the kernel segment base of a given address
+ */
+#define KSEGX(a)		((_ACAST32_ (a)) & 0xe0000000)
+
+/*
+ * Returns the physical address of a CKSEGx / XKPHYS address
+ */
+#define CPHYSADDR(a)		((_ACAST32_(a)) & 0x1fffffff)
+#define XPHYSADDR(a)		((_ACAST64_(a)) &			\
+				 _CONST64_(0x000000ffffffffff))
+
+#ifdef CONFIG_64BIT
+
+/*
+ * Memory segments (64bit kernel mode addresses)
+ * The compatibility segments use the full 64-bit sign extended value.  Note
+ * the R8000 doesn't have them so don't reference these in generic MIPS code.
+ */
+#define XKUSEG			_CONST64_(0x0000000000000000)
+#define XKSSEG			_CONST64_(0x4000000000000000)
+#define XKPHYS			_CONST64_(0x8000000000000000)
+#define XKSEG			_CONST64_(0xc000000000000000)
+#define CKSEG0			_CONST64_(0xffffffff80000000)
+#define CKSEG1			_CONST64_(0xffffffffa0000000)
+#define CKSSEG			_CONST64_(0xffffffffc0000000)
+#define CKSEG3			_CONST64_(0xffffffffe0000000)
+
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
+#define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
+
+#else
+
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
+#define CKSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
+
+/*
+ * Map an address to a certain kernel segment
  */
-#ifndef __ASM_MIPS_ADDRSPACE_H
-#define __ASM_MIPS_ADDRSPACE_H
+#define KSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
+#define KSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
+#define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
+#define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
 
 /*
  * Memory segments (32bit kernel mode addresses)
+ * These are the traditional names used in the 32-bit universe.
  */
 #define KUSEG			0x00000000
 #define KSEG0			0x80000000
@@ -20,63 +98,68 @@
 #define KSEG2			0xc0000000
 #define KSEG3			0xe0000000
 
-#define K0BASE	KSEG0
+#define CKUSEG			0x00000000
+#define CKSEG0			0x80000000
+#define CKSEG1			0xa0000000
+#define CKSEG2			0xc0000000
+#define CKSEG3			0xe0000000
+
+#endif
 
 /*
- * Returns the kernel segment base of a given address
+ * Cache modes for XKPHYS address conversion macros
  */
-#ifndef __ASSEMBLY__
-#define KSEGX(a)		(((unsigned long)(a)) & 0xe0000000)
-#else
-#define KSEGX(a)		((a) & 0xe0000000)
-#endif
+#define K_CALG_COH_EXCL1_NOL2	0
+#define K_CALG_COH_SHRL1_NOL2	1
+#define K_CALG_UNCACHED		2
+#define K_CALG_NONCOHERENT	3
+#define K_CALG_COH_EXCL		4
+#define K_CALG_COH_SHAREABLE	5
+#define K_CALG_NOTUSED		6
+#define K_CALG_UNCACHED_ACCEL	7
 
 /*
- * Returns the physical address of a KSEG0/KSEG1 address
+ * 64-bit address conversions
  */
-#ifndef __ASSEMBLY__
-#define PHYSADDR(a)		(((unsigned long)(a)) & 0x1fffffff)
-#else
-#define PHYSADDR(a)		((a) & 0x1fffffff)
-#endif
+#define PHYS_TO_XKSEG_UNCACHED(p)	PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
+#define PHYS_TO_XKSEG_CACHED(p)		PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
+#define XKPHYS_TO_PHYS(p)		((p) & TO_PHYS_MASK)
+#define PHYS_TO_XKPHYS(cm, a)		(_CONST64_(0x8000000000000000) | \
+					 (_CONST64_(cm) << 59) | (a))
 
 /*
  * Returns the uncached address of a sdram address
  */
 #ifndef __ASSEMBLY__
-#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
+#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
 /* We use a 36 bit physical address map here and
    cannot access physical memory directly from core */
 #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
-#else	/* !CONFIG_AU1X00 */
+#else	/* !CONFIG_SOC_AU1X00 */
 #define UNCACHED_SDRAM(a) KSEG1ADDR(a)
-#endif	/* CONFIG_AU1X00 */
+#endif	/* CONFIG_SOC_AU1X00 */
 #endif	/* __ASSEMBLY__ */
+
 /*
- * Map an address to a certain kernel segment
+ * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
+ * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
+ * R8000 implements most with its 48-bit physical address space.
  */
-#ifndef __ASSEMBLY__
-#define KSEG0ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0))
-#define KSEG1ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1))
-#define KSEG2ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2))
-#define KSEG3ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3))
-#else
-#define KSEG0ADDR(a)		(((a) & 0x1fffffff) | KSEG0)
-#define KSEG1ADDR(a)		(((a) & 0x1fffffff) | KSEG1)
-#define KSEG2ADDR(a)		(((a) & 0x1fffffff) | KSEG2)
-#define KSEG3ADDR(a)		(((a) & 0x1fffffff) | KSEG3)
-#endif
+#define TO_PHYS_MASK	_CONST64_(0x07ffffffffffffff)	/* 2^^59 - 1 */
+
+#ifndef CONFIG_CPU_R8000
 
 /*
- * Memory segments (64bit kernel mode addresses)
+ * The R8000 doesn't have the 32-bit compat spaces so we don't define them
+ * in order to catch bugs in the source code.
  */
-#define XKUSEG			0x0000000000000000
-#define XKSSEG			0x4000000000000000
-#define XKPHYS			0x8000000000000000
-#define XKSEG			0xc000000000000000
-#define CKSEG0			0xffffffff80000000
-#define CKSEG1			0xffffffffa0000000
-#define CKSSEG			0xffffffffc0000000
-#define CKSEG3			0xffffffffe0000000
-
-#endif /* __ASM_MIPS_ADDRSPACE_H */
+
+#define COMPAT_K1BASE32		_CONST64_(0xffffffffa0000000)
+#define PHYS_TO_COMPATK1(x)	((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
+
+#endif
+
+#define KDM_TO_PHYS(x)		(_ACAST64_ (x) & TO_PHYS_MASK)
+#define PHYS_TO_K0(x)		(_ACAST64_ (x) | CAC_BASE)
+
+#endif /* _ASM_ADDRSPACE_H */
diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
index 6a33197..2a948e8 100644
--- a/include/asm-mips/au1x00.h
+++ b/include/asm-mips/au1x00.h
@@ -137,7 +137,7 @@ static __inline__ int au_ffs(int x)
 #define CP0_DEBUG		$23
 
 /* SDRAM Controller */
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
 
 #define MEM_SDMODE0                0xB4000800
 #define MEM_SDMODE1                0xB4000808
@@ -156,7 +156,7 @@ static __inline__ int au_ffs(int x)
 #define MEM_SDWRMD1                0xB4000888
 #define MEM_SDWRMD2                0xB4000890
 
-#else /* CONFIG_AU1550 */
+#else /* CONFIG_SOC_AU1550 */
 
 #define MEM_SDMODE0                0xB4000000
 #define MEM_SDMODE1                0xB4000004
@@ -174,7 +174,7 @@ static __inline__ int au_ffs(int x)
 #define MEM_SDWRMD1                0xB4000028
 #define MEM_SDWRMD2                0xB400002C
 
-#endif /* CONFIG_AU1550 */
+#endif /* CONFIG_SOC_AU1550 */
 
 #define MEM_SDSLEEP                0xB4000030
 #define MEM_SDSMCKE                0xB4000034
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 7137072..3a0f33f 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -120,7 +120,7 @@ static inline void set_io_port_base(unsigned long base)
  */
 extern inline unsigned long virt_to_phys(volatile void * address)
 {
-	return PHYSADDR(address);
+	return CPHYSADDR(address);
 }
 
 extern inline void * phys_to_virt(unsigned long address)
@@ -133,7 +133,7 @@ extern inline void * phys_to_virt(unsigned long address)
  */
 extern inline unsigned long virt_to_bus(volatile void * address)
 {
-	return PHYSADDR(address);
+	return CPHYSADDR(address);
 }
 
 extern inline void * bus_to_virt(unsigned long address)
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index b2f606f..0e10396 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -30,21 +30,21 @@
 
 #define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_DBAU1X00		1
-#define CONFIG_AU1X00		1  /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
 #ifdef CONFIG_DBAU1000
 /* Also known as Merlot */
-#define CONFIG_AU1000		1
+#define CONFIG_SOC_AU1000	1
 #else
 #ifdef CONFIG_DBAU1100
-#define CONFIG_AU1100		1
+#define CONFIG_SOC_AU1100	1
 #else
 #ifdef CONFIG_DBAU1500
-#define CONFIG_AU1500		1
+#define CONFIG_SOC_AU1500	1
 #else
 #ifdef CONFIG_DBAU1550
 /* Cabernet */
-#define CONFIG_AU1550           1
+#define CONFIG_SOC_AU1550	1
 #else
 #error "No valid board set"
 #endif
@@ -148,7 +148,9 @@
 #error "Invalid CPU frequency - must be multiple of 12!"
 #endif
 
-#define CFG_HZ                  (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+#define CFG_MIPS_TIMER_FREQ	(CFG_MHZ * 1000000)
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
 
diff --git a/include/configs/gth2.h b/include/configs/gth2.h
index c2a50c1..c2d6ca7 100644
--- a/include/configs/gth2.h
+++ b/include/configs/gth2.h
@@ -30,9 +30,9 @@
 
 #define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_GTH2		1
-#define CONFIG_AU1X00		1  /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
-#define CONFIG_AU1000		1
+#define CONFIG_SOC_AU1000	1
 
 #define CONFIG_MISC_INIT_R	1
 
@@ -118,7 +118,9 @@
 
 #define CFG_MHZ			500
 
-#define CFG_HZ			(CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+#define CFG_MIPS_TIMER_FREQ	(CFG_MHZ * 1000000)
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
 
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index 5ca00b3..2e4ee66 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -118,7 +118,9 @@
 
 #define CFG_BOOTPARAMS_LEN	128*1024
 
-#define CFG_HZ			(incaip_get_cpuclk() / 2)
+#define CFG_MIPS_TIMER_FREQ	(incaip_get_cpuclk() / 2)
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000
 
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 810e0f0..2caa641 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -30,16 +30,16 @@
 
 #define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_PB1X00		1
-#define CONFIG_AU1X00		1  /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
 #ifdef CONFIG_PB1000
-#define CONFIG_AU1000		1
+#define CONFIG_SOC_AU1000	1
 #else
 #ifdef CONFIG_PB1100
-#define CONFIG_AU1100		1
+#define CONFIG_SOC_AU1100	1
 #else
 #ifdef CONFIG_PB1500
-#define CONFIG_AU1500		1
+#define CONFIG_SOC_AU1500	1
 #else
 #error "No valid board set"
 #endif
@@ -81,7 +81,9 @@
 
 #define CFG_BOOTPARAMS_LEN	128*1024
 
-#define CFG_HZ			396000000      /* FIXME causes overflow in net.c */
+#define CFG_MIPS_TIMER_FREQ	396000000
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
 
diff --git a/include/configs/purple.h b/include/configs/purple.h
index 1be4e05..ef92637 100644
--- a/include/configs/purple.h
+++ b/include/configs/purple.h
@@ -114,7 +114,8 @@
 #define	CFG_PROMPT		"PURPLE # "	/* Monitor Command Prompt    */
 #define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
 #define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_HZ			(CPU_CLOCK_RATE/2)
+#define CFG_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE/2)
+#define CFG_HZ			1000
 #define	CFG_MAXARGS		16		/* max number of command args*/
 
 #define	CFG_LOAD_ADDR		0x80500000	/* default load address	*/
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index d6bcc8e..3dfd218 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -120,7 +120,9 @@
 
 #define CFG_MHZ			132
 
-#define CFG_HZ			(CFG_MHZ * 1000000)
+#define CFG_MIPS_TIMER_FREQ	(CFG_MHZ * 1000000)
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000	/* Cached addr */
 
diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h
index dadf5d3..fc2357d 100644
--- a/include/configs/tb0229.h
+++ b/include/configs/tb0229.h
@@ -122,7 +122,9 @@
 
 #define CFG_BOOTPARAMS_LEN	128*1024
 
-#define CFG_HZ			(CPU_TCLOCK_RATE/4)
+#define CFG_MIPS_TIMER_FREQ	(CPU_TCLOCK_RATE/4)
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000
 
diff --git a/lib_mips/time.c b/lib_mips/time.c
index cd8dc72..1e92789 100644
--- a/lib_mips/time.c
+++ b/lib_mips/time.c
@@ -22,26 +22,12 @@
  */
 
 #include <common.h>
+#include <asm/mipsregs.h>
 
+static unsigned long timestamp;
 
-static inline void mips_compare_set(u32 v)
-{
-	asm volatile ("mtc0 %0, $11" : : "r" (v));
-}
-
-static inline void mips_count_set(u32 v)
-{
-	asm volatile ("mtc0 %0, $9" : : "r" (v));
-}
-
-
-static inline u32 mips_count_get(void)
-{
-	u32 count;
-
-	asm volatile ("mfc0 %0, $9" : "=r" (count) :);
-	return count;
-}
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY	(CFG_MIPS_TIMER_FREQ + CFG_HZ / 2) / CFG_HZ
 
 /*
  * timer without interrupts
@@ -49,34 +35,47 @@ static inline u32 mips_count_get(void)
 
 int timer_init(void)
 {
-	mips_compare_set(0);
-	mips_count_set(0);
+	/* Set up the timer for the first expiration. */
+	timestamp = 0;
+	write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
 
 	return 0;
 }
 
 void reset_timer(void)
 {
-	mips_count_set(0);
+	timestamp = 0;
+	write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
 }
 
 ulong get_timer(ulong base)
 {
-	return mips_count_get() - base;
+	unsigned int count;
+	unsigned int expirelo = read_c0_compare();
+
+	/* Check to see if we have missed any timestamps. */
+	count = read_c0_count();
+	while ((count - expirelo) < 0x7fffffff) {
+		expirelo += CYCLES_PER_JIFFY;
+		timestamp++;
+	}
+	write_c0_compare(expirelo);
+
+	return (timestamp - base);
 }
 
 void set_timer(ulong t)
 {
-	mips_count_set(t);
+	timestamp = t;
+	write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
 }
 
-void udelay (unsigned long usec)
+void udelay(unsigned long usec)
 {
-	ulong tmo;
-	ulong start = get_timer(0);
+	unsigned int tmo;
 
-	tmo = usec * (CFG_HZ / 1000000);
-	while ((ulong)((mips_count_get() - start)) < tmo)
+	tmo = read_c0_count() + (usec * (CFG_MIPS_TIMER_FREQ / 1000000));
+	while ((tmo - read_c0_count()) < 0x7fffffff)
 		/*NOP*/;
 }
 
@@ -86,7 +85,7 @@ void udelay (unsigned long usec)
  */
 unsigned long long get_ticks(void)
 {
-	return mips_count_get();
+	return get_timer(0);
 }
 
 /*
diff --git a/mips_config.mk b/mips_config.mk
index 67fb67d..05eb05d 100644
--- a/mips_config.mk
+++ b/mips_config.mk
@@ -40,10 +40,9 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
 # LDFLAGS_vmlinux		+= -G 0 -static -n -nostdlib
 # MODFLAGS			+= -mlong-calls
 #
-
-#
-# Meanwhile, U-Boot rely on PIC. We add proper switches explicitly.
+# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
+# to RAM. $28 is always used as gp.
 #
-PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic -pipe
+PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic
 PLATFORM_CPPFLAGS		+= -msoft-float
 PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib

^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [U-Boot-Users] [GIT PULL] MIPS updates
@ 2008-07-08 14:04 Shinya Kuribayashi
  2008-07-09 21:24 ` Wolfgang Denk
  0 siblings, 1 reply; 18+ messages in thread
From: Shinya Kuribayashi @ 2008-07-08 14:04 UTC (permalink / raw)
  To: u-boot

Please pull MIPS update to pick up the following patch.

The following changes since commit c956717ab25c962ef49d49064dfc73f4edcba1fb:
  Wolfgang Denk (1):
        Merge branch 'master' of /home/wd/git/u-boot/custodians

are available in the git repository at:

  git://git.denx.de/u-boot-mips.git master

Jason McMullan (1):
      mips: When booting Linux images, add 'ethaddr' and 'eth1addr' to the environment

 lib_mips/bootm.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/lib_mips/bootm.c b/lib_mips/bootm.c
index f813fc5..8fe3782 100644
--- a/lib_mips/bootm.c
+++ b/lib_mips/bootm.c
@@ -54,6 +54,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
 	char	*commandline = getenv ("bootargs");
 	char	env_buf[12];
 	int	ret;
+	const char *cp;
 
 	/* find kernel entry point */
 	if (images->legacy_hdr_valid) {
@@ -113,6 +114,16 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
 	sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize));
 	linux_env_set ("flash_size", env_buf);
 
+	cp = getenv("ethaddr");
+	if (cp != NULL) {
+		linux_env_set("ethaddr", cp);
+	}
+
+	cp = getenv("eth1addr");
+	if (cp != NULL) {
+		linux_env_set("eth1addr", cp);
+	}
+
 	if (!images->autostart)
 		return ;
 

^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [U-Boot-Users] [GIT PULL] MIPS updates
@ 2008-07-29 16:00 Shinya Kuribayashi
  2008-07-29 23:24 ` Wolfgang Denk
  0 siblings, 1 reply; 18+ messages in thread
From: Shinya Kuribayashi @ 2008-07-29 16:00 UTC (permalink / raw)
  To: u-boot

Hi Wolfgang,

please pull MIPS update.  I'd like to make this into v1.3.4-final.

Thanks,

  Shinya

---

The following changes since commit 1953d128fd07f07d1c3810a28c0863ea64dae1b6:
  Michal Simek (1):
        microblaze: Fix printf() format issues

are available in the git repository at:

  git://git.denx.de/u-boot-mips.git master

Wolfgang Ocker (1):
      mips: Fix baudrate divisor computation on alchemy cpus

 cpu/mips/au1x00_serial.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

commit dbd32387920e5ad6f9dd58a7b5012bbabe2a6a21
Author: Wolfgang Ocker <weo@reccoware.de>
Date:   Mon Jul 28 16:56:51 2008 +0200

    mips: Fix baudrate divisor computation on alchemy cpus
    
    Use CFG_MIPS_TIMER_FREQ when computing the baudrate divisor
    on alchemy cpus.
    
    Signed-off-by: Wolfgang Ocker <weo@reccoware.de>
    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>

diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c
index 6309794..e8baab5 100644
--- a/cpu/mips/au1x00_serial.c
+++ b/cpu/mips/au1x00_serial.c
@@ -76,7 +76,7 @@ void serial_setbrg (void)
 	sd = (*sys_powerctrl & 0x03) + 2;
 
 	/* calulate 2x baudrate and round */
-	divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE)));
+	divisorx2 = ((CFG_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
 
 	if (divisorx2 & 0x01)
 		divisorx2 = divisorx2 + 1;

^ permalink raw reply related	[flat|nested] 18+ messages in thread
end of thread, other threads:[~2008-07-29 23:24 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-10-21 14:31 [U-Boot-Users] [GIT PULL] MIPS updates Shinya Kuribayashi
2007-11-01 21:54 ` Wolfgang Denk
  -- strict thread matches above, loose matches on Subject: below --
2007-11-17 12:15 Shinya Kuribayashi
2007-11-18  0:28 ` Wolfgang Denk
2008-01-16 23:42 Shinya Kuribayashi
2008-01-23 13:38 ` Wolfgang Denk
2008-03-25 13:04 Shinya Kuribayashi
2008-05-02  3:33 Shinya Kuribayashi
2008-05-03 22:10 ` Wolfgang Denk
2008-05-06  4:34 Shinya Kuribayashi
2008-05-09 20:20 ` Wolfgang Denk
2008-05-22 15:29 Shinya Kuribayashi
2008-06-07  1:19 Shinya Kuribayashi
2008-06-11 20:51 ` Wolfgang Denk
2008-07-08 14:04 Shinya Kuribayashi
2008-07-09 21:24 ` Wolfgang Denk
2008-07-29 16:00 Shinya Kuribayashi
2008-07-29 23:24 ` Wolfgang Denk

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