[U-Boot-Users] [PATCH 0/4] PPC4xx: Add board-independent support for DDR2 SPD DIMMs on 440EPx/GRx

[U-Boot-Users] [PATCH 0/4] PPC4xx: Add board-independent support for DDR2 SPD DIMMs on 440EPx/GRx

[Larry Johnson]

Summary:

 board/amcc/sequoia/sdram.h   |    4 +-
 board/lwmon5/sdram.h         |    4 +-
 cpu/ppc4xx/Makefile          |   31 +-
 cpu/ppc4xx/denali_data_eye.c |  396 +++++++++++++
 cpu/ppc4xx/denali_spd_ddr2.c | 1276 ++++++++++++++++++++++++++++++++++++++++++
 include/ppc440.h             |  514 +++++++++++++++--
 6 files changed, 2167 insertions(+), 58 deletions(-)

This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM
controller.  It should also work on the 440GRx.  It is based on the DDR2
SPD code for the 440EP/440EPx, but makes no provision for DDR1 support.
It also takes EPx/GRx SDRAM definitions and support code that are
specific to the Sequoia/Rainier and lwmon5 boards, and copies them to
general 4xx directories.  (Neither Stefan nor I are happy with the names
of the two new files, so suggestions are welcome!)

This code has been tested on prototype Korat boards with three Kingston
DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC
(two ranks), at PLB frequencies of 133 MHz and 166 MHz.  The Korat board
has a single DIMM socket, but support has been provided (though not
tested) for boards with two DIMM sockets.

The first patch adds the Denali SDRAM controller definitions to
"ppc440.h".  It also fixes two typos in the definitions, so the board-
specific "sdram.h" files containing these definitions are also fixed to
avoid compiler warnings.

The second patch creates a non-board-specific file for performing the
SDRAM data-eye search.  The only significant change from the board-
specific code is that error checking on reads uses ECC error information
in addition to checking the value of the data read back.  This
eliminates the theoretical possibility that a bad read might be masked
by the ECC.

The third patch creates a file containing the code to configure the
SDRAM controller based on the contents of the DIMMs SPDs.  The fourth
patch modifies "Makefile" to build the two new files when appropriate.

All comments and suggestions will be appreciated.

-- Best regards, Larry Johnson <lrj@acm.org>

[U-Boot-Users] [PATCH 0/4] PPC4xx: Add board-independent support for DDR2 SPD DIMMs on 440EPx/GRx

[Stefan Roese]

Larry,

On Thursday 25 October 2007, Larry Johnson wrote:
> Summary:
>
>  board/amcc/sequoia/sdram.h   |    4 +-
>  board/lwmon5/sdram.h         |    4 +-
>  cpu/ppc4xx/Makefile          |   31 +-
>  cpu/ppc4xx/denali_data_eye.c |  396 +++++++++++++
>  cpu/ppc4xx/denali_spd_ddr2.c | 1276
> ++++++++++++++++++++++++++++++++++++++++++ include/ppc440.h             | 
> 514 +++++++++++++++--
>  6 files changed, 2167 insertions(+), 58 deletions(-)
>
> This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM
> controller.  It should also work on the 440GRx.  It is based on the DDR2
> SPD code for the 440EP/440EPx, but makes no provision for DDR1 support.
> It also takes EPx/GRx SDRAM definitions and support code that are
> specific to the Sequoia/Rainier and lwmon5 boards, and copies them to
> general 4xx directories.  (Neither Stefan nor I are happy with the names
> of the two new files, so suggestions are welcome!)

I'm (finally) trying to integrate your patches into the u-boot-ppc4xx 
custodian repository for upstream merge. Unfortunately my repo changed quite 
a bit lately and your patches don't apply anymore. So could you please rebase 
this patchset against the "for-1.3.2" branch of the 4xx repo:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-ppc4xx.git;a=shortlog;h=for-1.3.2

I promise to commit soon so that you don't have to rework again.

Unfortunately this is valid also for these patchsets too:

[U-Boot-Users] [PATCH 1/2 (resubmit)] PPC4xx: Cosmetic changes

[U-Boot-Users] [PATCH 1/4 resubmit] Add driver for National Semiconductor LM73 
temperature sensor (with your Korat board support)

Thanks.

Best regards,
Stefan

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