From mboxrd@z Thu Jan  1 00:00:00 1970
From: gvb.uboot <gvb.uboot@gmail.com>
Date: Sat, 24 Nov 2007 07:53:54 -0500
Subject: [U-Boot-Users] question of codes in \cpu\74xx_7xx\cache.S
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References: <BAY131-DS292902233E345165ED844917B0@phx.gbl>
Message-ID: <47481EE2.7030202@gmail.com>
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To: u-boot@lists.denx.de

xiangguo_li at hotmail.com wrote:
> intercepted from \cpu\74xx_7xx\cache.S
>  
> /*
> * Enable L1 Instruction cache
> */
> _GLOBAL(icache_enable)
> mfspr r3, HID0
> li r5, HID0_ICFI|HID0_ILOCK
> andc r3, r3, r5
> ori r3, r3, HID0_ICE
> ori r5, r3, HID0_ICFI
> mtspr HID0, r5                    // this instruction is redundant,
> mtspr HID0, r3                    // or this one?
> isync
> blr
>  
>  
> -lxg

Most likely neither are redundant.  To say for sure, you need to read 
the User's Manual for the 74xx family where it specifies how to change 
the HID0 register.

Changing the HID0 register (and other processor control registers) 
require certain "magic" sequences that the chip designers specify.  If 
the software doesn't do the specified sequence *exactly,* there is no 
guarantee that the processor will run properly (indeed, it likely will 
crash).

The above code was written by very smart engineers who read and re-read 
the User's Manual.  The sequence has been working for several years now. 
  Odds are really good that it is exactly what is needed.

HTH,
gvb