[U-Boot-Users] question of codes in \cpu\74xx_7xx\cache.S

[U-Boot-Users] question of codes in \cpu\74xx_7xx\cache.S

[xiangguo_li at hotmail.com]

intercepted from \cpu\74xx_7xx\cache.S

/*
* Enable L1 Instruction cache
*/
_GLOBAL(icache_enable)
mfspr r3, HID0
li r5, HID0_ICFI|HID0_ILOCK
andc r3, r3, r5
ori r3, r3, HID0_ICE
ori r5, r3, HID0_ICFI
mtspr HID0, r5                    // this instruction is redundant,
mtspr HID0, r3                    // or this one?
isync
blr


-lxg
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[U-Boot-Users] question of codes in \cpu\74xx_7xx\cache.S

[gvb.uboot]

xiangguo_li at hotmail.com wrote:
> intercepted from \cpu\74xx_7xx\cache.S
>  
> /*
> * Enable L1 Instruction cache
> */
> _GLOBAL(icache_enable)
> mfspr r3, HID0
> li r5, HID0_ICFI|HID0_ILOCK
> andc r3, r3, r5
> ori r3, r3, HID0_ICE
> ori r5, r3, HID0_ICFI
> mtspr HID0, r5                    // this instruction is redundant,
> mtspr HID0, r3                    // or this one?
> isync
> blr
>  
>  
> -lxg

Most likely neither are redundant.  To say for sure, you need to read 
the User's Manual for the 74xx family where it specifies how to change 
the HID0 register.

Changing the HID0 register (and other processor control registers) 
require certain "magic" sequences that the chip designers specify.  If 
the software doesn't do the specified sequence *exactly,* there is no 
guarantee that the processor will run properly (indeed, it likely will 
crash).

The above code was written by very smart engineers who read and re-read 
the User's Manual.  The sequence has been working for several years now. 
  Odds are really good that it is exactly what is needed.

HTH,
gvb

[U-Boot-Users] question of codes in \cpu\74xx_7xx\cache.S

[xiangguo_li at hotmail.com]

thank you. you are right.
I find the reason in the manual: 
DCE 2 Data cache enable
0 The data cache is neither accessed nor updated. All pages are accessed as if they were
marked cache-inhibited (WIM = x1x). Potential cache accesses from the bus (snoop and cache
operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits are
ignored and all accesses are propagated to the L2 cache, L3 cache, or bus as cache-inhibited.
For those transactions, CI is asserted regardless of address translation.DCE is zero at
power-up.
1 The data cache is enabled.Note that HID0[DCFI] must be set at the same time that this bit is set.
                                          ********************************************************************************
-------------------------
Most likely neither are redundant.  To say for sure, you need to read 
the User's Manual for the 74xx family where it specifies how to change 
the HID0 register
....................

HTH,
gvb
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