[U-Boot-Users] Accessing IRAM & DRAM through different segments in MIPS

[Viswanath Bandi <bandiv@txc.stpn.soft.net>]

Hi All,

I am trying to run U-boot on a MIPS 4KEc processor mapped onto FPGA. The 
code is working fine when KSEG0 is configured as un-cached segment (K0 
field in CP0 register 16 configured as 2). But when I make this as 
cached segment, the code crashes and I see that the values on the stack 
are not written correctly. Due to this the program causes some exception 
or the other.

In order to isolate the problem between icache and dcache, I want to try 
and access IRAM using KSEG1 addresses (0xA0000000 onwards) and DRAM 
using KSEG0 addresses (0x80000000) or vice versa. Is the possible? Can 
it be done through some configuration changes or #defines? This way I 
can find out whether instruction is the culprit for not writing the 
value in memory or the data cache.

I would very much appreciate any information in this regard.

Best Regards,
Viswanath Bandi