[U-Boot-Users] Accessing IRAM & DRAM through different segments in MIPS

[U-Boot-Users] Accessing IRAM & DRAM through different segments in MIPS

[Viswanath Bandi]

Hi All,

I am trying to run U-boot on a MIPS 4KEc processor mapped onto FPGA. The 
code is working fine when KSEG0 is configured as un-cached segment (K0 
field in CP0 register 16 configured as 2). But when I make this as 
cached segment, the code crashes and I see that the values on the stack 
are not written correctly. Due to this the program causes some exception 
or the other.

In order to isolate the problem between icache and dcache, I want to try 
and access IRAM using KSEG1 addresses (0xA0000000 onwards) and DRAM 
using KSEG0 addresses (0x80000000) or vice versa. Is the possible? Can 
it be done through some configuration changes or #defines? This way I 
can find out whether instruction is the culprit for not writing the 
value in memory or the data cache.

I would very much appreciate any information in this regard.

Best Regards,
Viswanath Bandi

[U-Boot-Users] Accessing IRAM & DRAM through different segments in MIPS

[Shinya Kuribayashi]

Viswanath Bandi wrote:
> I am trying to run U-boot on a MIPS 4KEc processor mapped onto FPGA. The 
> code is working fine when KSEG0 is configured as un-cached segment (K0 
> field in CP0 register 16 configured as 2). But when I make this as 
> cached segment, the code crashes and I see that the values on the stack 
> are not written correctly. Due to this the program causes some exception 
> or the other.

Ok.

> In order to isolate the problem between icache and dcache, I want to try 
> and access IRAM using KSEG1 addresses (0xA0000000 onwards) and DRAM 
> using KSEG0 addresses (0x80000000) or vice versa. Is the possible? Can 

IMHO it's possible but very hard to do, and

> it be done through some configuration changes or #defines? This way I 

we don't have such debugging alternatives, sorry.

> can find out whether instruction is the culprit for not writing the 
> value in memory or the data cache.

How do you configure 4KEc caches? I'm interested in 1) its size and 2)
the numbers of its ways. Hmm, some ideas come to mind. For the first
setp does attached patch work for you?

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 443240e..05735f4 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -29,10 +29,10 @@
 #include <asm/addrspace.h>
 #include <asm/cacheops.h>
 
-	/* 16KB is the maximum size of instruction and data caches on
-	 * MIPS 4K.
+	/* 64KB is the maximum size of instruction and data caches on
+	 * MIPS 4KE.
 	 */
-#define MIPS_MAX_CACHE_SIZE	0x4000
+#define MIPS_MAX_CACHE_SIZE	0x10000
 
 /*
  * cacheop macro to automate cache operations

[U-Boot-Users] Accessing IRAM & DRAM through different segments in MIPS

[Hoi-Ho Chan]

I had a similar problem with running U-boot on a 4KEc processor on
cached memory, u-boot got stuck after display the memory sizes. Then I
added a routine like this:

ulong start_addr = KSEG0;
ulong end_addr = start_addr + CFG_DCACHE_SIZE;

while (start_addr < end_addr) {
    __asm__ __voltaile__(".set noreorder; \
                                     .set mips3; \
                                     cache %1, (%0);
                                     .set mips0;
                                     .set reorder"::"r"(start_addr),
"i"(Index_Writeback_Inv_D));

    start_addr += CFG_CACHELINE_SIZE;
}

and then call it at lib_mips/board.c right before relocate_code(...)

seems to work for me.

Thanks
Donald

On Jan 5, 2008 4:55 AM, Viswanath Bandi <bandiv@txc.stpn.soft.net> wrote:
> Hi All,
>
> I am trying to run U-boot on a MIPS 4KEc processor mapped onto FPGA. The
> code is working fine when KSEG0 is configured as un-cached segment (K0
> field in CP0 register 16 configured as 2). But when I make this as
> cached segment, the code crashes and I see that the values on the stack
> are not written correctly. Due to this the program causes some exception
> or the other.
>
> In order to isolate the problem between icache and dcache, I want to try
> and access IRAM using KSEG1 addresses (0xA0000000 onwards) and DRAM
> using KSEG0 addresses (0x80000000) or vice versa. Is the possible? Can
> it be done through some configuration changes or #defines? This way I
> can find out whether instruction is the culprit for not writing the
> value in memory or the data cache.
>
> I would very much appreciate any information in this regard.
>
> Best Regards,
> Viswanath Bandi
>
>
>
> -------------------------------------------------------------------------
> This SF.net email is sponsored by: Microsoft
> Defy all challenges. Microsoft(R) Visual Studio 2005.
> http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/
> _______________________________________________
> U-Boot-Users mailing list
> U-Boot-Users at lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/u-boot-users
>

[U-Boot-Users] Accessing IRAM & DRAM through different segments in MIPS

[Viswanath Bandi]

Thanks Shinya & Donald for the suggestions.

Following is our cache configuration.

Cache Size (KB): 8KBytes
Associativity (Lines Per Set): 4-Ways
Way Size (KB): 2KBytes
Number  of Sets:128 Sets
Cache Line Size: 16-bytes per line

One more thing I found out is that the cache works when configured in 
write-through mode (with or without write allocate). The only mode which 
is giving problem is "write-back, write allocate".

Two more points:
1) By the time the program hangs, relocation is done and program starts 
executing from DDR. It hangs somewhere down the program.
2) Whenever it hangs, it's reading gp value from stack and getting wrong 
value. When I single step through the code which actually puts it on the 
stack (sw), then this program goes further. Doesn't hang at this point.

I will try this piece of code and see if it makes any difference.

Best Regards,
Viswanath Bandi

Hoi-Ho Chan wrote:
> I had a similar problem with running U-boot on a 4KEc processor on
> cached memory, u-boot got stuck after display the memory sizes. Then I
> added a routine like this:
>
> ulong start_addr = KSEG0;
> ulong end_addr = start_addr + CFG_DCACHE_SIZE;
>
> while (start_addr < end_addr) {
>     __asm__ __voltaile__(".set noreorder; \
>                                      .set mips3; \
>                                      cache %1, (%0);
>                                      .set mips0;
>                                      .set reorder"::"r"(start_addr),
> "i"(Index_Writeback_Inv_D));
>
>     start_addr += CFG_CACHELINE_SIZE;
> }
>
> and then call it at lib_mips/board.c right before relocate_code(...)
>
> seems to work for me.
>
> Thanks
> Donald
>
> On Jan 5, 2008 4:55 AM, Viswanath Bandi <bandiv@txc.stpn.soft.net> wrote:
>   
>> Hi All,
>>
>> I am trying to run U-boot on a MIPS 4KEc processor mapped onto FPGA. The
>> code is working fine when KSEG0 is configured as un-cached segment (K0
>> field in CP0 register 16 configured as 2). But when I make this as
>> cached segment, the code crashes and I see that the values on the stack
>> are not written correctly. Due to this the program causes some exception
>> or the other.
>>
>> In order to isolate the problem between icache and dcache, I want to try
>> and access IRAM using KSEG1 addresses (0xA0000000 onwards) and DRAM
>> using KSEG0 addresses (0x80000000) or vice versa. Is the possible? Can
>> it be done through some configuration changes or #defines? This way I
>> can find out whether instruction is the culprit for not writing the
>> value in memory or the data cache.
>>
>> I would very much appreciate any information in this regard.
>>
>> Best Regards,
>> Viswanath Bandi
>>
>>
>>
>> -------------------------------------------------------------------------
>> This SF.net email is sponsored by: Microsoft
>> Defy all challenges. Microsoft(R) Visual Studio 2005.
>> http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/
>> _______________________________________________
>> U-Boot-Users mailing list
>> U-Boot-Users at lists.sourceforge.net
>> https://lists.sourceforge.net/lists/listinfo/u-boot-users
>>
>>     
>
>   
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[U-Boot-Users] Accessing IRAM & DRAM through different segments in MIPS

[Shinya Kuribayashi]

Viswanath Bandi wrote:
> Thanks Shinya & Donald for the suggestions.
> 
> Following is our cache configuration.
> 
> Cache Size (KB): 8KBytes
> Associativity (Lines Per Set): 4-Ways
> Way Size (KB): 2KBytes
> Number  of Sets:128 Sets
> Cache Line Size: 16-bytes per line
> 
> One more thing I found out is that the cache works when configured in
> write-through mode (with or without write allocate). The only mode which
> is giving problem is "write-back, write allocate".

Ok. I'd like to make sure that

 * Which version of U-Boot do you use?

 * How do you configure CFGs below?
   - CFG_ICACHE_SIZE
   - CFG_DCACHE_SIZE
   - CFG_CACHELINE_SIZE

And if possible, please post the diff regarding `cpu/mips' like this,

   $ diff -uprN u-boot-X.Y.Z{.orig,-yours}/cpu/mips > my.patch

Thanks in advance,

  Shinya