From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Warren <biggerbadderben@gmail.com>
Date: Sun, 13 Jan 2008 23:04:22 -0500
Subject: [U-Boot-Users] [PATCH 1/2] Add support for a Freescale non-CPM
 SPIcontroller
In-Reply-To: <58A20A281BAF1047B4EAE68DE5C0BDC2C0E411@zch01exm21.fsl.freescale.net>
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	<478AD7E2.1000807@gmail.com>
	<58A20A281BAF1047B4EAE68DE5C0BDC2C0E411@zch01exm21.fsl.freescale.net>
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Liu Dave wrote:
>>>> +typedef struct spi834x
>>>> +{
>>>> +       u8 res0[0x20];  /* 0x0-0x01f reserved */
>>>> +       u32 mode;       /* mode register  */
>>>> +       u32 event;      /* event register */
>>>> +       u32 mask;       /* mask register  */
>>>> +       u32 com;        /* command register */
>>>> +       u32 tx;         /* transmit register */
>>>> +       u32 rx;         /* receive register */
>>>> +       u8 res1[0xC8];  /* fill up to 0x100 */
>>>> + } spi834x_t;
>>>>     
>>>>         
>>> please put this into fsl_spi.h to reuse for different 8xxx family.
>>>   
>>>       
>> Can you confirm that the registers in 85xx are the same?  If so, I'll 
>> move this.
>>     
>
> Ben, at lease the 8610 has the same SPI as 834x.
>
> The 8360 and 8568 with CPU mode have likely SPI as 834x.
>   
I just looked up the RM for 8360, and for some reason its register 
offsets are a *bit* different than the 8349. I'll move this struct to 
fsl_spi.h, but we'll have to do some #ifdef magic to work with multiple 
processors, I guess.

regards,
Ben