From mboxrd@z Thu Jan  1 00:00:00 1970
From: John Rigby <jrigby@freescale.com>
Date: Wed, 16 Jan 2008 08:55:26 -0700
Subject: [U-Boot-Users] [PATCH] [ads5121] Set ips dividor to 1/4 of csb
	clock.
In-Reply-To: <478E0283.1070102@semihalf.com>
References: <478E0283.1070102@semihalf.com>
Message-ID: <478E28EE.2060306@freescale.com>
List-Id: <u-boot.lists.denx.de>
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To: u-boot@lists.denx.de

Grzegorz,

Sorry I got an update from the hw people today and
the recommended freq for the ips is 66MHz so we
need to change the divider to 0x3.  I'm pretty sure this
is final.

John

Grzegorz Bernacki wrote:
> Previous setting cause ips clock to be out of spec. This bug was found by John
> Rigby from Freescale.
>
> Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
>
> diff --git a/include/mpc512x.h b/include/mpc512x.h
> index a06b5c6..d1c6fb2 100644
> --- a/include/mpc512x.h
> +++ b/include/mpc512x.h
> @@ -185,7 +185,7 @@
>  
>  /* SCFR1 System Clock Frequency Register 1
>   */
> -#define SCFR1_IPS_DIV			0x2
> +#define SCFR1_IPS_DIV			0x4
>  #define SCFR1_IPS_DIV_MASK		0x03800000
>  #define SCFR1_IPS_DIV_SHIFT		23
>  
>