* [U-Boot-Users] [PATCH 3/4] [ARM] Added Artila M-501 board files
[not found] <mailman.1060081.1201392092.7786.u-boot-users@lists.sourceforge.net>
` (2 preceding siblings ...)
2008-01-31 8:17 ` [U-Boot-Users] [PATCH 2/4] [ARM] Added Artila M-501 config file Timo Tuunainen
@ 2008-01-31 8:18 ` Timo Tuunainen
2008-01-31 8:19 ` [U-Boot-Users] [PATCH 4/4] [ARM] Artila M-501 support CREDITS file Timo Tuunainen
4 siblings, 0 replies; 6+ messages in thread
From: Timo Tuunainen @ 2008-01-31 8:18 UTC (permalink / raw)
To: u-boot
Signed-off-by: Timo Tuunainen <timo.tuunainen@sysart.fi>
---
board/m501sk/Makefile | 48 +++++++++++
board/m501sk/config.mk | 1 +
board/m501sk/eeprom.c | 88 +++++++++++++++++++++
board/m501sk/m501sk.c | 189 ++++++++++++++++++++++++++++++++++++++++++++
board/m501sk/m501sk.h | 168 +++++++++++++++++++++++++++++++++++++++
board/m501sk/memsetup.S | 200
+++++++++++++++++++++++++++++++++++++++++++++++
board/m501sk/u-boot.lds | 56 +++++++++++++
7 files changed, 750 insertions(+), 0 deletions(-)
create mode 100644 board/m501sk/Makefile
create mode 100644 board/m501sk/config.mk
create mode 100644 board/m501sk/eeprom.c
create mode 100644 board/m501sk/m501sk.c
create mode 100644 board/m501sk/m501sk.h
create mode 100644 board/m501sk/memsetup.S
create mode 100644 board/m501sk/u-boot.lds
diff --git a/board/m501sk/Makefile b/board/m501sk/Makefile
new file mode 100644
index 0000000..5756ea0
--- /dev/null
+++ b/board/m501sk/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := m501sk.o eeprom.o
+
+SOBJS := memsetup.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/m501sk/config.mk b/board/m501sk/config.mk
new file mode 100644
index 0000000..9ce161e
--- /dev/null
+++ b/board/m501sk/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000
diff --git a/board/m501sk/eeprom.c b/board/m501sk/eeprom.c
new file mode 100644
index 0000000..0c6fe0b
--- /dev/null
+++ b/board/m501sk/eeprom.c
@@ -0,0 +1,88 @@
+/*
+ Add by Alan , 07-29-2005
+ For ATMEL AT24C16 EEPROM
+*/
+
+#include <common.h>
+#include <i2c.h>
+#ifdef CFG_EEPROM_AT24C16
+#undef DEBUG
+
+void eeprom_init (void)
+{
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+#endif
+ /*if(eeprom_probe(0x50, 0)==0)
+ printf("EEPROM Found!\n");*/
+}
+
+int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer,
unsigned cnt)
+{
+ int page,count=0,i=0;
+
+ page = offset / 0x100;
+ i = offset % 0x100;
+
+ while(count < cnt){
+ if (i2c_read (dev_addr|page, i++, 1, buffer+count++, 1) != 0)
+ return 1;
+ if(i > 0xff) {
+ page++;
+ i = 0;
+ }
+ }
+
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ *
+ * for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
+ * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
+ *
+ * for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
+ * 0x00000nxx for EEPROM address selectors and page number at n.
+ */
+int eeprom_write (unsigned dev_addr,unsigned offset, uchar *buffer,
unsigned cnt)
+{
+ int page,i=0,count=0;
+
+ page = offset / 0x100;
+ i = offset % 0x100;
+
+ while(count < cnt){
+ if (i2c_write (dev_addr|page, i++, 1, buffer+count++, 1) != 0)
+ return 1;
+ if(i > 0xff) {
+ page++;
+ i =0;
+ }
+ }
+
+#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+
+ return 0;
+}
+
+#ifndef CONFIG_SPI
+int eeprom_probe (unsigned dev_addr, unsigned offset)
+{
+ unsigned char chip;
+
+ /* Probe the chip address */
+#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
+ chip = offset >> 8; /* block number */
+#else
+ chip = offset >> 16; /* block number */
+#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
+
+ chip |= dev_addr; /* insert device address */
+/* printf("i2c_chip:%x\n", chip); */
+ return (i2c_probe (chip));
+}
+#endif
+#endif
+
diff --git a/board/m501sk/m501sk.c b/board/m501sk/m501sk.c
new file mode 100644
index 0000000..a402536
--- /dev/null
+++ b/board/m501sk/m501sk.c
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2008
+ * Based on modifications by Alan Lu / Artila
+ * Author : Timo Tuunainen / Sysart
+ Kimmo Leppala / Sysart
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+#include "m501sk.h"
+#include "net.h"
+
+#ifdef CONFIG_M501SK
+
+void m501sk_gpio_init (void)
+{
+ AT91C_BASE_PIOD->PIO_PER=1<<(M501SK_DEBUG_LED1-96)|
+ 1<<(M501SK_DEBUG_LED2-96)|1<<(M501SK_DEBUG_LED3-96)|
+ 1<<(M501SK_DEBUG_LED4-96)| 1<<(M501SK_READY_LED-96);
+
+ AT91C_BASE_PIOD->PIO_OER =1<<(M501SK_DEBUG_LED1-96)|
+ 1<<(M501SK_DEBUG_LED2-96)|1<<(M501SK_DEBUG_LED3-96)|
+ 1<<(M501SK_DEBUG_LED4-96)|1<<(M501SK_READY_LED-96);
+ AT91C_BASE_PIOD->PIO_SODR = 1<<(M501SK_READY_LED-96);
+ AT91C_BASE_PIOD->PIO_CODR = 1<<(M501SK_DEBUG_LED3-96);
+ AT91C_BASE_PIOB->PIO_PER = 1<<(M501SK_BUZZER-32);
+ AT91C_BASE_PIOB->PIO_OER = 1<<(M501SK_BUZZER-32);
+ AT91C_BASE_PIOC->PIO_PDR = (1<<7) | (1<<8);
+
+ /* Power OFF all USART's LEDs */
+ AT91C_BASE_PIOA->PIO_PER = AT91C_PA5_TXD3|AT91C_PA6_RXD3|AT91C_PA17_TXD0|
+ AT91C_PA18_RXD0|AT91C_PA22_RXD2| AT91C_PA23_TXD2;
+ AT91C_BASE_PIOA->PIO_OER = AT91C_PA5_TXD3|AT91C_PA6_RXD3|AT91C_PA17_TXD0|
+ AT91C_PA18_RXD0|AT91C_PA22_RXD2| AT91C_PA23_TXD2;
+ AT91C_BASE_PIOA->PIO_SODR = AT91C_PA5_TXD3|AT91C_PA6_RXD3|AT91C_PA17_TXD0|
+ AT91C_PA18_RXD0|AT91C_PA22_RXD2| AT91C_PA23_TXD2;
+ AT91C_BASE_PIOB->PIO_PER = AT91C_PB20_RXD1|AT91C_PB21_TXD1;
+ AT91C_BASE_PIOB->PIO_OER = AT91C_PB20_RXD1|AT91C_PB21_TXD1;
+ AT91C_BASE_PIOB->PIO_SODR = AT91C_PB20_RXD1|AT91C_PB21_TXD1;
+}
+
+uchar m501sk_gpio_set (M501SK_PIO io)
+{
+ uchar status = 0xff;
+ switch(io){
+ case M501SK_DEBUG_LED1:
+ case M501SK_DEBUG_LED2:
+ case M501SK_DEBUG_LED3:
+ case M501SK_DEBUG_LED4:
+ case M501SK_READY_LED:
+ AT91C_BASE_PIOD->PIO_SODR = 1<<(io-96);
+ status = AT91C_BASE_PIOD->PIO_ODSR & (1<<(io-96));
+ break;
+ case M501SK_BUZZER:
+ AT91C_BASE_PIOB->PIO_SODR = 1<<(io-32);
+ status = AT91C_BASE_PIOB->PIO_ODSR & (1<<(io-32));
+ break;
+ }
+ return status;
+}
+
+uchar m501sk_gpio_clear (M501SK_PIO io)
+{
+ uchar status = 0xff;
+ switch(io){
+ case M501SK_DEBUG_LED1:
+ case M501SK_DEBUG_LED2:
+ case M501SK_DEBUG_LED3:
+ case M501SK_DEBUG_LED4:
+ case M501SK_READY_LED:
+ AT91C_BASE_PIOD->PIO_CODR = 1<<(io-96);
+ status = AT91C_BASE_PIOD->PIO_ODSR & (1<<(io-96));
+ break;
+ case M501SK_BUZZER:
+ AT91C_BASE_PIOB->PIO_CODR = 1<<(io-32);
+ status = AT91C_BASE_PIOB->PIO_ODSR & (1<<(io-32));
+ break;
+ }
+ return status;
+}
+
+void load_sernum_ethaddr ()
+{
+;
+}
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init (void)
+{
+ /* Enable Ctrlc */
+ console_init_f ();
+
+ /* Correct IRDA resistor problem */
+ /* Set PA23_TXD in Output */
+ ((AT91PS_PIO)AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+ gd->bd->bi_arch_number = MACH_TYPE_M501;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ m501sk_gpio_init();
+
+ interrupt_init(); /*Do interrupt init here, because
+ flash needs timers initialized*/
+ flash_init();
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ int i=0;
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+ for(i=0;i<500;i++){
+ m501sk_gpio_clear(M501SK_DEBUG_LED3);
+ m501sk_gpio_clear(M501SK_BUZZER);
+ udelay(250);
+ m501sk_gpio_set(M501SK_DEBUG_LED3);
+ m501sk_gpio_set(M501SK_BUZZER);
+
+ udelay(80);
+ }
+ m501sk_gpio_clear(M501SK_BUZZER);
+ m501sk_gpio_clear(M501SK_DEBUG_LED3);
+
+ return 0;
+}
+
+int board_late_init (void)
+{
+ /* Fix Ethernet Initialization Bug when starting Linux from U-Boot */
+#if defined(CONFIG_CMD_NET)
+ eth_init(gd->bd);
+ eth_halt();
+#endif
+
+ run_command("protect on 10000000 1041ffff", 0);
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if defined(CONFIG_CMD_NET)
+/*
+ * Name:
+ * at91rm9200_GetPhyInterface
+ * Description:
+ * Initialise the interface functions to the PHY
+ * Arguments:
+ * None
+ * Return value:
+ * None
+ */
+void at91rm9200_GetPhyInterface (AT91PS_PhyOps p_phyops)
+{
+ p_phyops->Init = dm9161_InitPhy;
+ p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+ p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+ p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+#endif
+#endif /* CONFIG_DRIVER_ETHER */
+
+#endif
diff --git a/board/m501sk/m501sk.h b/board/m501sk/m501sk.h
new file mode 100644
index 0000000..9f71426
--- /dev/null
+++ b/board/m501sk/m501sk.h
@@ -0,0 +1,168 @@
+/*
+ * linux/include/asm-arm/arch-at91/hardware.h
+ *
+ * Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __M501SK_H
+#define __M501SK_H
+
+#ifndef __ASSEMBLY__
+#include <asm-arm/arch-at91rm9200/AT91RM9200.h>
+#else
+#include <asm-arm/arch-at91rm9200/AT91RM9200_inc.h>
+#endif
+
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by
PA22 */
+#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) /* USART 2
Receive Data */
+#define AT91C_PA5_TXD3 ((unsigned int) 1 << 5) /* USART 3 Transmit Data */
+#define AT91C_PA6_RXD3 ((unsigned int) 1 << 6) /* USART 3 Receive Data */
+
+/* ========== Register definition for PIOD peripheral ========== */
+#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) /* (PIOD) Pin Data
Status Register */
+#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) /* (PIOD) Clear
Output Data Register */
+#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) /* (PIOD) Output
Write Enable Register */
+#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) /* (PIOD)
Multi-driver Enable Register */
+#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) /* (PIOD) Interrupt
Mask Register */
+#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) /* (PIOD) Interrupt
Enable Register */
+#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) /* (PIOD) Output Data
Status Register */
+#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) /* (PIOD) Set Output
Data Register */
+#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) /* (PIOD) PIO Enable
Register */
+#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) /* (PIOD) Output
Write Disable Register */
+#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) /* (PIOD) Pull-up
Enable Register */
+#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) /* (PIOD)
Multi-driver Disable Register */
+#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) /* (PIOD) Interrupt
Status Register */
+#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) /* (PIOD) Interrupt
Disable Register */
+#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) /* (PIOD) PIO Disable
Register */
+#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) /* (PIOD) Output
Disable Registerr */
+#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) /* (PIOD) Output
Write Status Register */
+#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) /* (PIOD) AB Select
Status Register */
+#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) /* (PIOD) Select A
Register */
+#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) /* (PIOD) Pad
Pull-up Status Register */
+#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) /* (PIOD) Pull-up
Disable Register */
+#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) /* (PIOD)
Multi-driver Status Register */
+#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) /* (PIOD) PIO Status
Register */
+#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) /* (PIOD) Output
Enable Register */
+#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) /* (PIOD) Output
Status Register */
+#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) /* (PIOD) Input
Filter Enable Register */
+#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) /* (PIOD) Select B
Register */
+#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) /* (PIOD) Input
Filter Disable Register */
+#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) /* (PIOD) Input
Filter Status Register */
+
+#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) /* Pin Controlled by PD0 */
+#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) /* Ethernet MAC
Transmit Data 0 */
+#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) /* Pin Controlled by PD1 */
+#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) /* Ethernet MAC
Transmit Data 1 */
+#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) /* Pin Controlled by
PD10 */
+#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) /* PMC
Programmable Clock Output 3 */
+#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) /* ETM ARM9
pipeline status 1 */
+#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) /* Pin Controlled by
PD11 */
+#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) /* */
+#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) /* ETM ARM9
pipeline status 2 */
+#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) /* Pin Controlled by
PD12 */
+#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) /* */
+#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) /* ETM Trace
Packet 0 */
+#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) /* Pin Controlled by
PD13 */
+#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) /* */
+#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) /* ETM Trace
Packet 1 */
+#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) /* Pin Controlled by
PD14 */
+#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) /* */
+#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) /* ETM Trace
Packet 2 */
+#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) /* Pin Controlled by
PD15 */
+#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) /* SSC Transmit
data */
+#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) /* ETM Trace
Packet 3 */
+#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) /* Pin Controlled by
PD16 */
+#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) /* SSC Transmit
Data 1 */
+#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) /* ETM Trace
Packet 4 */
+#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) /* Pin Controlled by
PD17 */
+#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) /* SSC Transmit
Data 2 */
+#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) /* ETM Trace
Packet 5 */
+#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) /* Pin Controlled by
PD18 */
+#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) /* SPI
Peripheral Chip Select 1 */
+#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) /* ETM Trace
Packet 6 */
+#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) /* Pin Controlled by
PD19 */
+#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) /* SPI
Peripheral Chip Select 2 */
+#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) /* ETM Trace
Packet 7 */
+#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) /* Pin Controlled by PD2 */
+#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) /* Ethernet MAC
Transmit Data 2 */
+#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) /* Pin Controlled by
PD20 */
+#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) /* SPI
Peripheral Chip Select 3 */
+#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) /* ETM Trace
Packet 8 */
+#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) /* Pin Controlled by
PD21 */
+#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) /* Usart 0
Ready To Send */
+#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) /* ETM Trace
Packet 9 */
+#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) /* Pin Controlled by
PD22 */
+#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) /* Usart 0
Ready To Send */
+#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) /* ETM Trace
Packet 10 */
+#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) /* Pin Controlled by
PD23 */
+#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) /* USART 2
Ready To Send */
+#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) /* ETM Trace
Packet 11 */
+#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) /* Pin Controlled by
PD24 */
+#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) /* USART 3
Ready To Send */
+#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) /* ETM Trace
Packet 12 */
+#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) /* Pin Controlled by
PD25 */
+#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) /* USART 1 Data
Terminal ready */
+#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) /* ETM Trace
Packet 13 */
+#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) /* Pin Controlled by
PD26 */
+#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) /* ETM Trace
Packet 14 */
+#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) /* Pin Controlled by
PD27 */
+#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) /* ETM Trace
Packet 15 */
+#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) /* Pin Controlled by PD3 */
+#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) /* Ethernet MAC
Transmit Data 3 */
+#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) /* Pin Controlled by PD4 */
+#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) /* Ethernet MAC
Transmit Enable */
+#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) /* Pin Controlled by PD5 */
+#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) /* Ethernet MAC
Transmikt Coding Error */
+#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) /* Pin Controlled by PD6 */
+#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) /* DBGU Debug
Transmit Data */
+#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) /* Pin Controlled by PD7 */
+#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) /* PMC
Programmable Clock Output 0 */
+#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) /* ETM
Synchronization signal */
+#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) /* Pin Controlled by PD8 */
+#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) /* PMC
Programmable Clock Output 1 */
+#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) /* ETM Trace
Clock signal */
+#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) /* Pin Controlled by PD9 */
+#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) /* PMC
Programmable Clock 2 */
+#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) /* ETM ARM9
pipeline status 0 */
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
+#define AT91C_PIO_PC5 ((unsigned int) 1 << 5)
+#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PB8 ((unsigned int) 1 << 8)
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9)
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10)
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11)
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17)
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28)
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29)
+
+typedef enum {
+ M501SK_BUZZER=38,
+ M501SK_DEBUG_LED1=96,
+ M501SK_DEBUG_LED2,
+ M501SK_DEBUG_LED3,
+ M501SK_DEBUG_LED4,
+ M501SK_READY_LED=102,
+
+} M501SK_PIO;
+
+void m501sk_gpio_init(void);
+uchar m501sk_gpio_set(M501SK_PIO io);
+uchar m501sk_gpio_clear(M501SK_PIO io);
+
+#endif
diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S
new file mode 100644
index 0000000..725b62e
--- /dev/null
+++ b/board/m501sk/memsetup.S
@@ -0,0 +1,200 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw at its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker at its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifdef CONFIG_BOOTBINFUNC
+/*
+ * some parameters for the board
+ *
+ * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
+ * turn is based on the boot.bin code from ATMEL
+ *
+ */
+
+/* flash */
+#define MC_PUIA 0xFFFFFF10
+#define MC_PUIA_VAL 0x00000000
+#define MC_PUP 0xFFFFFF50
+#define MC_PUP_VAL 0x00000000
+#define MC_PUER 0xFFFFFF54
+#define MC_PUER_VAL 0x00000000
+#define MC_ASR 0xFFFFFF04
+#define MC_ASR_VAL 0x00000000
+#define MC_AASR 0xFFFFFF08
+#define MC_AASR_VAL 0x00000000
+#define EBI_CFGR 0xFFFFFF64
+#define EBI_CFGR_VAL 0x00000000
+#define SMC2_CSR 0xFFFFFF70
+#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR 0xFFFFFC28
+#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
+#define PLLBR 0xFFFFFC2C
+#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR 0xFFFFFC30
+#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz
from PLLA */
+
+/* sdram */
+#define PIOC_ASR 0xFFFFF870
+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral
(D16/D31) */
+#define PIOC_BSR 0xFFFFF874
+#define PIOC_BSR_VAL 0x00000000
+#define PIOC_PDR 0xFFFFF804
+#define PIOC_PDR_VAL 0xFFFF0000
+#define EBI_CSA 0xFFFFFF60
+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define SDRC_CR 0xFFFFFF98
+#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
+#define SDRAM 0x20000000 /* address of the SDRAM */
+#define SDRAM1 0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define SDRC_MR 0xFFFFFF90
+#define SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1 0x00000004 /* refresh */
+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define SDRC_TR 0xFFFFFF94
+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevelinit
+lowlevelinit:
+ /* memory control configuration */
+ /* this isn't very elegant, but what the heck */
+ ldr r0, =SMRDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ add r2, r0, #80
+0:
+ /* the address */
+ ldr r1, [r0], #4
+ /* the value */
+ ldr r3, [r0], #4
+ str r3, [r1]
+ cmp r2, r0
+ bne 0b
+ /* delay - this is all done by guess */
+ ldr r0, =0x00010000
+1:
+ subs r0, r0, #1
+ bhi 1b
+ ldr r0, =SMRDATA1
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ add r2, r0, #176
+2:
+ /* the address */
+ ldr r1, [r0], #4
+ /* the value */
+ ldr r3, [r0], #4
+ str r3, [r1]
+ cmp r2, r0
+ bne 2b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+
+SMRDATA:
+ .word MC_PUIA
+ .word MC_PUIA_VAL
+ .word MC_PUP
+ .word MC_PUP_VAL
+ .word MC_PUER
+ .word MC_PUER_VAL
+ .word MC_ASR
+ .word MC_ASR_VAL
+ .word MC_AASR
+ .word MC_AASR_VAL
+ .word EBI_CFGR
+ .word EBI_CFGR_VAL
+ .word SMC2_CSR
+ .word SMC2_CSR_VAL
+ .word PLLAR
+ .word PLLAR_VAL
+ .word PLLBR
+ .word PLLBR_VAL
+ .word MCKR
+ .word MCKR_VAL
+ /* SMRDATA is 80 bytes long */
+ /* here there's a delay of 100 */
+SMRDATA1:
+ .word PIOC_ASR
+ .word PIOC_ASR_VAL
+ .word PIOC_BSR
+ .word PIOC_BSR_VAL
+ .word PIOC_PDR
+ .word PIOC_PDR_VAL
+ .word EBI_CSA
+ .word EBI_CSA_VAL
+ .word SDRC_CR
+ .word SDRC_CR_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL1
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL2
+ .word SDRAM1
+ .word SDRAM_VAL
+ .word SDRC_TR
+ .word SDRC_TR_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL3
+ .word SDRAM
+ .word SDRAM_VAL
+ /* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_BOOTBINFUNC */
diff --git a/board/m501sk/u-boot.lds b/board/m501sk/u-boot.lds
new file mode 100644
index 0000000..76df6b2
--- /dev/null
+++ b/board/m501sk/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--
1.5.2.5
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