From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anatolij Gustschin Date: Mon, 25 Feb 2008 20:04:20 +0100 Subject: [U-Boot-Users] [PATCH] POST: Disable cache while SPR POST Message-ID: <47C31134.5080406@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Currently (since commit b2e2142c) u-boot crashes on sequoia board while SPR test if CONFIG_4xx_DCACHE is enabled. This patch disables the cache while SPR test. Signed-off-by: Anatolij Gustschin --- post/cpu/ppc4xx/spr.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c index c12e378..37c9559 100644 --- a/post/cpu/ppc4xx/spr.c +++ b/post/cpu/ppc4xx/spr.c @@ -43,6 +43,12 @@ #include +#ifdef CONFIG_4xx_DCACHE +#include + +DECLARE_GLOBAL_DATA_PTR; +#endif + static struct { int number; char * name; @@ -164,6 +170,10 @@ int spr_post_test (int flags) }; unsigned long (*get_spr) (void) = (void *) code; +#ifdef CONFIG_4xx_DCACHE + /* disable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); +#endif for (i = 0; i < spr_test_list_size; i++) { int num = spr_test_list[i].number; @@ -180,6 +190,10 @@ int spr_post_test (int flags) ret = -1; } } +#ifdef CONFIG_4xx_DCACHE + /* enable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); +#endif return ret; } -- 1.5.3.3