[U-Boot-Users] Altera Stratix II

[David Hawkins <dwh@ovro.caltech.edu>]

Hi Liberty,

> I believe I will prefare crippling the CFI over Crippling the flash
> eeprom as I believe it will be easier on our production team... But I
> will have to play with it some more...

If I understand your earlier posts, you are using a CFI
flash, and then 'hiding' half or more of that Flash
from the end user. You mention 'lifting pins', but I'm
not sure if you were actually doing that, or effectively
doing that using your FPGA on the Flash address lines.

A few questions

1. Does it really matter if the user can read the data?

    If not, just use the write-protect feature of the Flash
    to protect it from users. Eg. have the local bus FPGA
    decode the flash chip select, and address, and keep
    write-protect asserted for the regions you want to
    protect.

2. Is there any way to have your FPGA do this hiding for you?

    For example, if the FPGA decoded the Flash chip select,
    it could allow the Flash to respond to low-addresses,
    and could itself drive zeros on the bus for accesses
    to the hidden region.

3. Even if you lift the pins on the Flash, what is to stop
    the user doing a full chip erase, and deleting your
    unseen settings?


Cheers,
Dave