[U-Boot-Users] Regarding Dcache Flush in MPC85xx

[Rafal Jaworowski <raj@semihalf.com>]

Scott Wood wrote:
> On Fri, Feb 29, 2008 at 06:10:10PM +0100, Rafal Jaworowski wrote:
>> Not really, unfortunatelly: the 85xx still lacks flushing the d-cache
>> before disabling it. I was going to fix this by refactoring existing
>> d-cache disabling/flushing routines into a common code that would sit in
>> the lib_ppc/ppccache.S (as mostly exisiting implementations are just
>> copy/paste of the same thing) and have 85xx use it too, but didn't have
>> time yet to clean it up. If anyone is willing to do it sooner, I won't
>> complain :)
> 
> The implementations for other CPUs such as 86xx are a bit questionable
> (arbitrarily using the cache line times 65536 as the size to flush, and
> inefficiently iterating 4 bytes at a time rather than a cache line).
> 
> Here's an 85xx implementation from an as-yet-unmerged Linux tree (replace
> KERNELBASE with something appropriate for U-boot) that dynamically figures
> out the cache and cache block sizes.  Note that it assumes at most 8 ways.
> 

Hi Scott,

Thanks for this code. It's true that bulk of current U-Boot implementations of
the PPC flushing routines are not relevant to real parameters of the cache
they operate against. I thought about making this auto-discovery too, so your
code is a great hint. I don't know however when I'd be able to work on merging
it with U-Boot and testing..

Rafal