[U-Boot-Users] FPGA mess

[Andre Schwarz <andre.schwarz@matrix-vision.de>]

Stefan,

you're listed as maintainer for the alpr board.
It's the only board that uses the ACEX1K.c file for FPGA loading...

I'm quite sure there are many boards with Altera FPGAs outside and can't 
believe they have all mounted
platform flashes and therefore don't use u-boot for loading the FPGA.
Nevertheless those board don't show up in the tree. Maybe they all keep 
their own patches like me ...

There are some points that doesn't seem to work out very well in general.
This is where some questions come up (top->down) :

common/cmd_fpga:
In function do_fpga there's a used environment variable "fpgadata" that 
obviously stores the location of the bitstream.
What sense does this make if the "data_size" parameter (=arg4) is _not_ 
optional ?
Instead the command "fpga load 0 0x..." leads to a load function with 
zero length.
The user always has to supply all 4 args (load, nr, data, size).
Of course the loading function could use the pre-defined bitstream size 
from the header or the device struct...

common/altera.c
What's that ACEX1K ? Isn't it a Cyclone chip and should use that interface ?
Why does this need special treatment throughout the interface ?

include/ACEX1K.h
Obviously there are some confusions about the various file formats and 
sizes that can be output
from Altera's SoPC Builder. Compression is also possible with 
de-compression on the fly during load ...
Of course the defined file sizes should match a raw bit file that 
represents the true size of the device.

Why is ACEX1K and Cyclone not merged ?


Does _any_ real board use the Altera path ? scanning the config files 
... no.

CYC2_ps_load in common/cyclon2.c the nCONFIG pin is never de-asserted 
during preparation. This code can't work.


Is there any interest in getting this fixed ?

What about Liberty's Stratix code ? It's living and working !


regards,
Andre Schwarz

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