[U-Boot-Users] FPGA mess

André Schwarz
2008-03-06T20:41:11Z

Heiko,

this all sounds very well indeed. Looks like we'll get common code.

Heiko Schocher wrote:
> Hello Andre,
>
> Andre Schwarz wrote:
>
>> Heiko Schocher schrieb:
>>
>>> Hello Stefan,
>>>
>>> Stefan Roese wrote:
>>>
>>>
>>>> On Thursday 06 March 2008, Andre Schwarz wrote:
>>>>
>>>>
>>>>> Stefan Roese schrieb:
>>>>>
>>>>>
>>>>>> On Wednesday 05 March 2008, Andre Schwarz wrote:
>>>>>>
> [...]
>
>>>>>>> Is there any interest in getting this fixed ?
>>>>>>>
>>>>>>>
>>>>>> Sure.
>>>>>>
>>>>>>
>>>>> But implementing the Altera path in a clean way means discarding the
>>>>> ACEX1K and breaking the alpr borad.
>>>>> I'm quite sure that Wolfgang will reject those changes.
>>>>>
>>>>>
>>>> Yes, I will reject this too. :)
>>>>
>>>>
>>> Why you break the alpr board. It uses the common/cyclon2.c?
>>> (OK, we should make a include/cyclon2.h and then we can drop the
>>> ACEX1K, right?)
>>>
>>>
>>>
>> I admit that I have not followed the ACEX1K down through the interface.
>> But since there is an ACEX1K "#define"
>> in common/altera.c and the serial download of the Cyclone is broken
>> (missing deassertion of nConfig) it looked like
>> alpr used the ACEX1K.
>>
>
> Ah, I understand (but the serial download on a cyclon 2 work(ed) fine ...)
> I think I will have a look in the datasheet for the cyclon 2 ...
>
> Hmm.. maybe I overlook something, but I see in:
>
> www.altera.com/literature/hb/cfg/cfg_cf51001.pdf
>
> on page 3 in the "Device Configuration Overview for Passive Schemes"
> Figure 1-1
>
> No need to deassert the nConfig Line after the Configuration ...
>
> And a "A reconfiguration is initiated by toggling the nCONFIG pin from high to
> low and then back to high."
>
> So it sounds to me its better to hold this line high ... but I am
> not a expert ;-)
>
>
yes - exactly. The pin is low active and by pulling it low (falling
edge) you can inititate device programming.
Holding this pin low doesn't work on any cyclone-II/III chip I have. You
have to deassert (=back to high) this before the first data bit comes in.
>> As I see now this is not true. We should fix the programming of nConfig
>> and verify on alpr.
>> Then we can remove ACEX1K and prepare for Cyclone-II and -III with a
>> unified loader, corrected chip
>> sizes and variable bitstream formats including endianess.
>>
>
> Sounds good.
>
>
>>>>> How can we solve this ?
>>>>>
>>>>>
>>>> By trying to solve it in a compatible way. I added Heiko Schocher to
>>>> CC too, since he was responsible for the FPGA booting implementation
>>>> of the alpr board.
>>>>
>>>>
>>> I have to admit that this was my First and only FPGA Implementation.
>>> Stefan, do you know, if we have somewhere an alpr board, so we can do
>>> tests with it, if we change code?
>>>
>>> bye
>>> Heiko
>>>
>>>
>> If would be great if you could test the changes on alpr before applying
>> patches.
>>
>
> I fast look in the VLAB and I found no alpr board :-(
>
>
>> It looks like no other Altera boards are in the tree ... I have
>> different ones and can do excessive testing.
>>
>
> That would be great
>
> bye,
> Heiko
>
I'm doing a lot of updates regarding u-boot + linux kernel right now
since we're upgrading the kernel to 2.6.24 with the new "libfdt".
Of course there will be a lot of code cleaning and hopefully Wolfgang
will accept our boards :-)

I'll supply a patch to the FPGA tree as soon as everything is running fine.
It would be great if you could test the patch against the alpr and give
me some feedback.

cheers,

Andr?

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