From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shinya Kuribayashi Date: Sat, 22 Mar 2008 13:21:12 +0900 Subject: [U-Boot-Users] [MIPS] Cleanup CP0 Status initialization Message-ID: <47E48938.6010602@ruby.dti.ne.jp> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add setup_c0_status from Linux. For the moment we disable interrupts, set CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for reset-time configuration and will work well across most processors. Signed-off-by: Shinya Kuribayashi --- cpu/mips/start.S | 34 +++++++++++++++++++++++++--------- 1 files changed, 25 insertions(+), 9 deletions(-) diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 0ecdd83..baac2ce 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -27,6 +27,30 @@ #include #include + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm + #define RVECENT(f,n) \ b f; nop #define XVECENT(f,bev) \ @@ -214,15 +238,7 @@ reset: /* WP(Watch Pending), SW0/1 should be cleared. */ mtc0 zero, CP0_CAUSE - /* STATUS register */ -#ifdef CONFIG_TB0229 - li k0, ST0_CU0 -#else - mfc0 k0, CP0_STATUS -#endif - li k1, ~ST0_IE - and k0, k1 - mtc0 k0, CP0_STATUS + setup_c0_status_reset /* Init Timer */ mtc0 zero, CP0_COUNT