[U-Boot-Users] [PATCH] ppc4xx: Don't use last 256 bytes of SDRAM, workaround for 440EPx CHIP 11 errata

[Larry Johnson <lrj@acm.org>]

Stefan Roese wrote:
> [...]
> 
> BTW: Can you test your board with ECC modules? We need to change the ECC code 
> in the Denali SPD routines to not touch the last 256 bytes here too. Best 
> would be if you could provide a patch for this. :)
> 
> Thanks.
> 
> Best regards,
> Stefan

Yes, we normally use ECC modules in our testing.  I've been looking at a
patch for "initdram()" Denali SPD, but I've been waiting to see how your
"CFG_MEM_TOP_HIDE" patch would turn out.

As things stand now, can I assume that boards using the Denali SPD will
also define "CFG_MEM_TOP_HIDE", and therefore initdram() should continue
to return the full size of the memory?

The only place that the last 256 bytes of memory are touched is when
"dflush()" is called to zero the SDRAM.  This does not cause a Machine
Check interrupt.  I am guessing that all the writes from "dflush()" are
aligned, and therefore there are no burst that access beyond the end of
of the SDRAM memory space.  If so, then my inclination is not to change
this part of the code.  Does this make sense?

Best regards,
Larry