From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Schwarz Date: Tue, 01 Apr 2008 16:08:50 +0200 Subject: [U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver In-Reply-To: <2acbd3e40804010642gbf413e1o12aa16657ce5129a@mail.gmail.com> References: <1206714585-13569-1-git-send-email-tor@excito.com> <47F23996.7070105@matrix-vision.de> <2acbd3e40804010642gbf413e1o12aa16657ce5129a@mail.gmail.com> Message-ID: <47F241F2.1000407@matrix-vision.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Andy Fleming schrieb: > On Tue, Apr 1, 2008 at 8:33 AM, Andre Schwarz > wrote: > >> Tor, >> >> after investigating the tsec code I'm wondering how your PHY works in >> RGMII mode ... >> >> I think that there are some things missing, e.g. taking RGMII into >> account during tsec_init. >> >> /* Init ECNTRL */ >> regs->ecntrl = ECNTRL_INIT_SETTINGS; >> > > If you look carefully, you'll notice that ecntrl's RPM bit is > read-only. Those bits are configured by POR pin strappings. > > sorry, my documentation (MPC8349EARM rev.1) declares this register read-write. Of course it will be configured by the HRCW but can be overwritten afterwards. If this is not true it's a documentation bug. > You may be more familiar with the UEC, which doesn't automatically > detect the link type, but is otherwise fairly similar to the tsec. > > What do you mean ? I'm trying to get two VSC8601 RGMII PHYs running on a MPC8343B ... > Andy > regards, Andre MATRIX VISION GmbH, Talstra?e 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Gesch?ftsf?hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.denx.de/pipermail/u-boot/attachments/20080401/7bad5047/attachment.htm