From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shinya Kuribayashi Date: Tue, 08 Apr 2008 16:20:35 +0900 Subject: [U-Boot-Users] [MIPS] cpu/mips/cpu.c: Fix flush_cache bug Message-ID: <47FB1CC3.2090904@necel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Cache operations have to take line address (addr), not start_addr. I noticed this bug when debugging ping failure. Signed-off-by: Shinya Kuribayashi --- cpu/mips/cpu.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index 8b43d8e..e267bba 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -56,8 +56,8 @@ void flush_cache(ulong start_addr, ulong size) unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); while (1) { - cache_op(Hit_Writeback_Inv_D, start_addr); - cache_op(Hit_Invalidate_I, start_addr); + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); if (addr == aend) break; addr += lsize;