* [PATCH v3 0/4] mips: Add initial Octeon MIPS64 base support
@ 2020-06-19 13:44 Stefan Roese
2020-06-19 13:44 ` [PATCH v3 1/4] sysreset: Add Octeon sysreset driver Stefan Roese
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Stefan Roese @ 2020-06-19 13:44 UTC (permalink / raw)
To: u-boot
This patch adds very basic support for the Octeon III SoCs. Only CFI
parallel UART, reset and NOR flash are supported for now.
Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches later.
To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III
CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such
boards.
v3:
This version is based on the MIPS start.S rework and Linux header sync
from Daniel using this branch: u-boot-mips/header_sync_v2
I removed the very early copy to to L2 cache for now to make the
integration into mainline easier. With all the patches already applied
and the Linux header sync, the resulting patchset is much smaller.
Thanks,
Stefan
Changes in v3:
- Don't "relocate" to L2 cache for now
- Remove inclusion of "common.h"
- Remove inclusion of "common.h"
- Slightly change some copyright messages (adjust year)
Changes in v2:
- Remove custom start.S and use common start.S. Minimal custom lowlevel
init code is currently added in the custom lowlevel_init.S. This needs
to be extended with necessary code, like errata handling etc. But for
a very first basic port, this seems to be all thats needed to boot on
the EBB7304 to the prompt.
- Removed select CREATE_ARCH_SYMLINK
- Removed Octeon II support, as its currently no added in this patchset
- Added cache.c to add the platform specific cache functions as no-ops
for Octeon as the platform is cache coherent
- Removed CONFIG_MIPS_CACHE_COHERENT
- Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
to enable better sync with the Linux files in the future
- Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
- Removed CONFIG_SYS_MIPS_TIMER_FREQ
Aaron Williams (1):
mips: octeon: Initial minimal support for the Marvell Octeon SoC
Stefan Roese (3):
sysreset: Add Octeon sysreset driver
mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file
mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
MAINTAINERS | 7 ++
arch/mips/Kconfig | 41 ++++++++
arch/mips/Makefile | 3 +
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mrvl,cn73xx.dtsi | 64 +++++++++++++
arch/mips/dts/mrvl,octeon-ebb7304.dts | 96 +++++++++++++++++++
arch/mips/mach-octeon/Kconfig | 60 ++++++++++++
arch/mips/mach-octeon/Makefile | 10 ++
arch/mips/mach-octeon/cache.c | 20 ++++
arch/mips/mach-octeon/clock.c | 27 ++++++
arch/mips/mach-octeon/cpu.c | 57 +++++++++++
arch/mips/mach-octeon/dram.c | 28 ++++++
arch/mips/mach-octeon/include/ioremap.h | 30 ++++++
arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 ++++++++
arch/mips/mach-octeon/include/mach/clock.h | 22 +++++
arch/mips/mach-octeon/lowlevel_init.S | 19 ++++
board/Marvell/octeon_ebb7304/Kconfig | 19 ++++
board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++
board/Marvell/octeon_ebb7304/Makefile | 8 ++
board/Marvell/octeon_ebb7304/board.c | 9 ++
configs/octeon_ebb7304_defconfig | 37 +++++++
drivers/sysreset/Kconfig | 7 ++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_octeon.c | 52 ++++++++++
include/configs/octeon_common.h | 25 +++++
include/configs/octeon_ebb7304.h | 20 ++++
scripts/config_whitelist.txt | 1 -
27 files changed, 712 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/dts/mrvl,cn73xx.dtsi
create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts
create mode 100644 arch/mips/mach-octeon/Kconfig
create mode 100644 arch/mips/mach-octeon/Makefile
create mode 100644 arch/mips/mach-octeon/cache.c
create mode 100644 arch/mips/mach-octeon/clock.c
create mode 100644 arch/mips/mach-octeon/cpu.c
create mode 100644 arch/mips/mach-octeon/dram.c
create mode 100644 arch/mips/mach-octeon/include/ioremap.h
create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h
create mode 100644 arch/mips/mach-octeon/include/mach/clock.h
create mode 100644 arch/mips/mach-octeon/lowlevel_init.S
create mode 100644 board/Marvell/octeon_ebb7304/Kconfig
create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS
create mode 100644 board/Marvell/octeon_ebb7304/Makefile
create mode 100644 board/Marvell/octeon_ebb7304/board.c
create mode 100644 configs/octeon_ebb7304_defconfig
create mode 100644 drivers/sysreset/sysreset_octeon.c
create mode 100644 include/configs/octeon_common.h
create mode 100644 include/configs/octeon_ebb7304.h
--
2.27.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/4] sysreset: Add Octeon sysreset driver
2020-06-19 13:44 [PATCH v3 0/4] mips: Add initial Octeon MIPS64 base support Stefan Roese
@ 2020-06-19 13:44 ` Stefan Roese
2020-06-29 22:11 ` Daniel Schwierzeck
2020-06-19 13:44 ` [PATCH v3 2/4] mips: octeon: Initial minimal support for the Marvell Octeon SoC Stefan Roese
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Stefan Roese @ 2020-06-19 13:44 UTC (permalink / raw)
To: u-boot
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.
Signed-off-by: Stefan Roese <sr@denx.de>
---
(no changes since v1)
drivers/sysreset/Kconfig | 7 ++++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_octeon.c | 52 ++++++++++++++++++++++++++++++
3 files changed, 60 insertions(+)
create mode 100644 drivers/sysreset/sysreset_octeon.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 4be7433404..6ebc90e1d3 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -57,6 +57,13 @@ config SYSRESET_MICROBLAZE
help
This is soft reset on Microblaze which does jump to 0x0 address.
+config SYSRESET_OCTEON
+ bool "Enable support for Marvell Octeon SoC family"
+ depends on ARCH_OCTEON
+ help
+ This enables the system reset driver support for Marvell Octeon
+ SoCs.
+
config SYSRESET_PSCI
bool "Enable support for PSCI System Reset"
depends on ARM_PSCI_FW
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 3ed4bab9e3..df2293b848 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
+obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
diff --git a/drivers/sysreset/sysreset_octeon.c b/drivers/sysreset/sysreset_octeon.c
new file mode 100644
index 0000000000..a05dac3226
--- /dev/null
+++ b/drivers/sysreset/sysreset_octeon.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+
+#define RST_SOFT_RST 0x0080
+
+struct octeon_sysreset_data {
+ void __iomem *base;
+};
+
+static int octeon_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct octeon_sysreset_data *data = dev_get_priv(dev);
+
+ writeq(1, data->base + RST_SOFT_RST);
+
+ return -EINPROGRESS;
+}
+
+static int octeon_sysreset_probe(struct udevice *dev)
+{
+ struct octeon_sysreset_data *data = dev_get_priv(dev);
+
+ data->base = dev_remap_addr(dev);
+
+ return 0;
+}
+
+static struct sysreset_ops octeon_sysreset = {
+ .request = octeon_sysreset_request,
+};
+
+static const struct udevice_id octeon_sysreset_ids[] = {
+ { .compatible = "mrvl,cn7xxx-rst" },
+ { }
+};
+
+U_BOOT_DRIVER(sysreset_octeon) = {
+ .id = UCLASS_SYSRESET,
+ .name = "octeon_sysreset",
+ .priv_auto_alloc_size = sizeof(struct octeon_sysreset_data),
+ .ops = &octeon_sysreset,
+ .probe = octeon_sysreset_probe,
+ .of_match = octeon_sysreset_ids,
+};
--
2.27.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/4] mips: octeon: Initial minimal support for the Marvell Octeon SoC
2020-06-19 13:44 [PATCH v3 0/4] mips: Add initial Octeon MIPS64 base support Stefan Roese
2020-06-19 13:44 ` [PATCH v3 1/4] sysreset: Add Octeon sysreset driver Stefan Roese
@ 2020-06-19 13:44 ` Stefan Roese
2020-06-29 22:34 ` Daniel Schwierzeck
2020-06-19 13:44 ` [PATCH v3 3/4] mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file Stefan Roese
2020-06-19 13:44 ` [PATCH v3 4/4] mips: octeon: Add minimal Octeon 3 EBB7304 EVK support Stefan Roese
3 siblings, 1 reply; 8+ messages in thread
From: Stefan Roese @ 2020-06-19 13:44 UTC (permalink / raw)
To: u-boot
From: Aaron Williams <awilliams@marvell.com>
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.
Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use U-Boot on with this port, the L2 cache (4MiB on
Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
prompt on such boards.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
Changes in v3:
- Don't "relocate" to L2 cache for now
- Remove inclusion of "common.h"
Changes in v2:
- Remove custom start.S and use common start.S. Minimal custom lowlevel
init code is currently added in the custom lowlevel_init.S. This needs
to be extended with necessary code, like errata handling etc. But for
a very first basic port, this seems to be all thats needed to boot on
the EBB7304 to the prompt.
- Removed select CREATE_ARCH_SYMLINK
- Removed Octeon II support, as its currently no added in this patchset
- Added cache.c to add the platform specific cache functions as no-ops
for Octeon as the platform is cache coherent
- Removed CONFIG_MIPS_CACHE_COHERENT
- Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
to enable better sync with the Linux files in the future
- Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
MAINTAINERS | 6 ++
arch/mips/Kconfig | 41 +++++++++++++
arch/mips/Makefile | 3 +
arch/mips/mach-octeon/Kconfig | 46 +++++++++++++++
arch/mips/mach-octeon/Makefile | 10 ++++
arch/mips/mach-octeon/cache.c | 20 +++++++
arch/mips/mach-octeon/clock.c | 27 +++++++++
arch/mips/mach-octeon/cpu.c | 57 +++++++++++++++++++
arch/mips/mach-octeon/dram.c | 28 +++++++++
arch/mips/mach-octeon/include/ioremap.h | 30 ++++++++++
arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 ++++++++++++++
arch/mips/mach-octeon/include/mach/clock.h | 22 +++++++
arch/mips/mach-octeon/lowlevel_init.S | 19 +++++++
scripts/config_whitelist.txt | 1 -
14 files changed, 351 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/mach-octeon/Kconfig
create mode 100644 arch/mips/mach-octeon/Makefile
create mode 100644 arch/mips/mach-octeon/cache.c
create mode 100644 arch/mips/mach-octeon/clock.c
create mode 100644 arch/mips/mach-octeon/cpu.c
create mode 100644 arch/mips/mach-octeon/dram.c
create mode 100644 arch/mips/mach-octeon/include/ioremap.h
create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h
create mode 100644 arch/mips/mach-octeon/include/mach/clock.h
create mode 100644 arch/mips/mach-octeon/lowlevel_init.S
diff --git a/MAINTAINERS b/MAINTAINERS
index 1fd975c72f..0aa0357967 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -763,6 +763,12 @@ M: Ezequiel Garcia <ezequiel@collabora.com>
S: Maintained
F: arch/mips/mach-jz47xx/
+MIPS Octeon
+M: Aaron Williams <awilliams@marvell.com>
+S: Maintained
+F: arch/mips/mach-octeon/
+F: arch/mips/include/asm/arch-octeon/
+
MMC
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bccd06cb0c..dd56da6dae 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -106,6 +106,23 @@ config ARCH_JZ47XX
select OF_CONTROL
select DM
+config ARCH_OCTEON
+ bool "Support Marvell Octeon CN7xxx platforms"
+ select CPU_CAVIUM_OCTEON
+ select DISPLAY_CPUINFO
+ select DMA_ADDR_T_64BIT
+ select DM
+ select DM_SERIAL
+ select MIPS_L2_CACHE
+ select MIPS_TUNE_OCTEON3
+ select ROM_EXCEPTION_VECTORS
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS64_OCTEON
+ select PHYS_64BIT
+ select OF_CONTROL
+ select OF_LIVE
+ imply CMD_DM
+
config MACH_PIC32
bool "Support Microchip PIC32"
select DM
@@ -160,6 +177,7 @@ source "arch/mips/mach-bmips/Kconfig"
source "arch/mips/mach-jz47xx/Kconfig"
source "arch/mips/mach-pic32/Kconfig"
source "arch/mips/mach-mtmips/Kconfig"
+source "arch/mips/mach-octeon/Kconfig"
if MIPS
@@ -233,6 +251,14 @@ config CPU_MIPS64_R6
Choose this option to build a kernel for release 6 or later of the
MIPS64 architecture.
+config CPU_MIPS64_OCTEON
+ bool "Marvell Octeon series of CPUs"
+ depends on SUPPORTS_CPU_MIPS64_OCTEON
+ select 64BIT
+ help
+ Choose this option for Marvell Octeon CPUs. These CPUs are between
+ MIPS64 R5 and R6 with other extensions.
+
endchoice
menu "General setup"
@@ -408,6 +434,12 @@ config SUPPORTS_CPU_MIPS64_R2
config SUPPORTS_CPU_MIPS64_R6
bool
+config SUPPORTS_CPU_MIPS64_OCTEON
+ bool
+
+config CPU_CAVIUM_OCTEON
+ bool
+
config CPU_MIPS32
bool
default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
@@ -415,6 +447,7 @@ config CPU_MIPS32
config CPU_MIPS64
bool
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
+ default y if CPU_MIPS64_OCTEON
config MIPS_TUNE_4KC
bool
@@ -431,6 +464,9 @@ config MIPS_TUNE_34KC
config MIPS_TUNE_74KC
bool
+config MIPS_TUNE_OCTEON3
+ bool
+
config 32BIT
bool
@@ -463,6 +499,11 @@ config MIPS_SRAM_INIT
before it can be used. If enabled, a function mips_sram_init() will
be called just before setup_stack_gd.
+config DMA_ADDR_T_64BIT
+ bool
+ help
+ Select this to enable 64-bit DMA addressing
+
config SYS_DCACHE_SIZE
int
default 0
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index af3f227436..6502aebd29 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -17,6 +17,7 @@ machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
machine-$(CONFIG_MACH_PIC32) += pic32
machine-$(CONFIG_ARCH_MTMIPS) += mtmips
machine-$(CONFIG_ARCH_MSCC) += mscc
+machine-${CONFIG_ARCH_OCTEON} += octeon
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
libs-y += $(machdirs)
@@ -30,6 +31,7 @@ arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6
arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
+arch-${CONFIG_CPU_MIPS64_OCTEON} += -march=octeon2
# Allow extra optimization for specific CPUs/SoCs
tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
@@ -37,6 +39,7 @@ tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
+tune-${CONFIG_MIPS_TUNE_OCTEON3} += -mtune=octeon2
# Include default header files
cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig
new file mode 100644
index 0000000000..3c8ca8dd36
--- /dev/null
+++ b/arch/mips/mach-octeon/Kconfig
@@ -0,0 +1,46 @@
+menu "Octeon platforms"
+ depends on ARCH_OCTEON
+
+config SYS_SOC
+ string
+ default "octeon"
+
+config OCTEON_CN7XXX
+ bool "Octeon CN7XXX SoC"
+
+config OCTEON_CN70XX
+ bool "Octeon CN70XX SoC"
+ select OCTEON_CN7XXX
+
+config OCTEON_CN73XX
+ bool "Octeon CN73XX SoC"
+ select OCTEON_CN7XXX
+
+config OCTEON_CN78XX
+ bool "Octeon CN78XX SoC"
+ select OCTEON_CN7XXX
+
+choice
+ prompt "Octeon MIPS family select"
+
+config SOC_OCTEON3
+ bool "Octeon III family"
+ help
+ This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx
+ and CNF75XX.
+
+endchoice
+
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_DCACHE_LINE_SIZE
+ default 128
+
+config SYS_ICACHE_SIZE
+ default 79872
+
+config SYS_ICACHE_LINE_SIZE
+ default 128
+
+endmenu
diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile
new file mode 100644
index 0000000000..2e37ca572c
--- /dev/null
+++ b/arch/mips/mach-octeon/Makefile
@@ -0,0 +1,10 @@
+# (C) Copyright 2019 Marvell, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += lowlevel_init.o
+obj-y += cache.o
+obj-y += clock.o
+obj-y += cpu.o
+obj-y += dram.o
diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c
new file mode 100644
index 0000000000..bea846d757
--- /dev/null
+++ b/arch/mips/mach-octeon/cache.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <cpu_func.h>
+
+/*
+ * The Octeon platform is cache coherent and cache flushes and invalidates
+ * are not needed. Define some platform specific empty flush_foo()
+ * functions here to overwrite the _weak common function as a no-op.
+ * This effectively disables all cache operations.
+ */
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+}
diff --git a/arch/mips/mach-octeon/clock.c b/arch/mips/mach-octeon/clock.c
new file mode 100644
index 0000000000..fc3776dc8f
--- /dev/null
+++ b/arch/mips/mach-octeon/clock.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018, 2019 Marvell International Ltd.
+ */
+
+#include <asm/global_data.h>
+#include <mach/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong notrace get_tbclk(void)
+{
+ return gd->cpu_clk;
+}
+
+int octeon_get_timer_freq(void)
+{
+ return gd->cpu_clk;
+}
+
+/**
+ * Returns the I/O clock speed in Hz
+ */
+u64 octeon_get_io_clock(void)
+{
+ return gd->bus_clk;
+}
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
new file mode 100644
index 0000000000..7ef17a7d66
--- /dev/null
+++ b/arch/mips/mach-octeon/cpu.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <asm/global_data.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/io.h>
+#include <mach/clock.h>
+#include <mach/cavm-reg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int get_clocks(void)
+{
+ const u64 ref_clock = PLL_REF_CLK;
+ union cavm_rst_boot rst_boot;
+
+ rst_boot.u = ioread64(CAVM_RST_BOOT);
+ gd->cpu_clk = ref_clock * rst_boot.s.c_mul;
+ gd->bus_clk = ref_clock * rst_boot.s.pnr_mul;
+
+ debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
+
+ return 0;
+}
+
+/* Early mach init code run from flash */
+int mach_cpu_init(void)
+{
+ /* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
+ /* ToDo: Move this to an early running bus (bootbus) DM driver */
+ clrsetbits_be64(CAVM_MIO_BOOT_REG_CFG0, 0xffff, 0x1f40);
+
+ /* Get clocks and store them in GD */
+ get_clocks();
+
+ return 0;
+}
+
+/**
+ * Returns number of cores
+ *
+ * @return number of CPU cores for the specified node
+ */
+static int cavm_octeon_num_cores(void)
+{
+ return fls64(ioread64(CAVM_CIU_FUSE) & 0xffffffffffff);
+}
+
+int print_cpuinfo(void)
+{
+ printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
+
+ return 0;
+}
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
new file mode 100644
index 0000000000..ff7a59f2ab
--- /dev/null
+++ b/arch/mips/mach-octeon/dram.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Stefan Roese <sr@denx.de>
+ */
+
+#include <dm.h>
+#include <ram.h>
+#include <asm/global_data.h>
+#include <linux/compat.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ /*
+ * No DDR init yet -> run in L2 cache
+ */
+ gd->ram_size = (4 << 20);
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->bd->bi_dram[1].size = 0;
+
+ return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return gd->ram_top;
+}
diff --git a/arch/mips/mach-octeon/include/ioremap.h b/arch/mips/mach-octeon/include/ioremap.h
new file mode 100644
index 0000000000..59b75008a2
--- /dev/null
+++ b/arch/mips/mach-octeon/include/ioremap.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_OCTEON_IOREMAP_H
+#define __ASM_MACH_OCTEON_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+ phys_addr_t size)
+{
+ return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
+{
+ return (void __iomem *)(XKPHYS | offset);
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+ return 0;
+}
+
+#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_OCTEON_IOREMAP_H */
diff --git a/arch/mips/mach-octeon/include/mach/cavm-reg.h b/arch/mips/mach-octeon/include/mach/cavm-reg.h
new file mode 100644
index 0000000000..b961e54956
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cavm-reg.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CAVM_REG_H__
+
+/* Register offsets */
+#define CAVM_CIU_FUSE ((u64 *)0x80010100000001a0)
+#define CAVM_MIO_BOOT_REG_CFG0 ((u64 *)0x8001180000000000)
+#define CAVM_RST_BOOT ((u64 *)0x8001180006001600)
+
+/* Register structs */
+
+/**
+ * Register (RSL) rst_boot
+ *
+ * RST Boot Register
+ */
+union cavm_rst_boot {
+ u64 u;
+ struct cavm_rst_boot_s {
+ u64 chipkill : 1;
+ u64 jtcsrdis : 1;
+ u64 ejtagdis : 1;
+ u64 romen : 1;
+ u64 ckill_ppdis : 1;
+ u64 jt_tstmode : 1;
+ u64 vrm_err : 1;
+ u64 reserved_37_56 : 20;
+ u64 c_mul : 7;
+ u64 pnr_mul : 6;
+ u64 reserved_21_23 : 3;
+ u64 lboot_oci : 3;
+ u64 lboot_ext : 6;
+ u64 lboot : 10;
+ u64 rboot : 1;
+ u64 rboot_pin : 1;
+ } s;
+};
+
+#endif /* __CAVM_REG_H__ */
diff --git a/arch/mips/mach-octeon/include/mach/clock.h b/arch/mips/mach-octeon/include/mach/clock.h
new file mode 100644
index 0000000000..a3c1d8b2cd
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/clock.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018, 2019 Marvell International Ltd.
+ */
+
+#ifndef __CLOCK_H__
+
+/** System PLL reference clock */
+#define PLL_REF_CLK 50000000 /* 50 MHz */
+#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK)
+
+/**
+ * Returns the I/O clock speed in Hz
+ */
+u64 octeon_get_io_clock(void);
+
+/**
+ * Returns the core clock speed in Hz
+ */
+u64 octeon_get_core_clock(void);
+
+#endif /* __CLOCK_H__ */
diff --git a/arch/mips/mach-octeon/lowlevel_init.S b/arch/mips/mach-octeon/lowlevel_init.S
new file mode 100644
index 0000000000..d9aab38cde
--- /dev/null
+++ b/arch/mips/mach-octeon/lowlevel_init.S
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/cacheops.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+
+ .set noreorder
+
+LEAF(lowlevel_init)
+ jr ra
+ nop
+ END(lowlevel_init)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index f6bf6f2474..f0e13389d0 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -230,7 +230,6 @@ CONFIG_CPLD_BR_PRELIM
CONFIG_CPLD_OR_PRELIM
CONFIG_CPM2
CONFIG_CPU_ARMV8
-CONFIG_CPU_CAVIUM_OCTEON
CONFIG_CPU_FREQ_HZ
CONFIG_CPU_HAS_LLSC
CONFIG_CPU_HAS_PREFETCH
--
2.27.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 3/4] mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file
2020-06-19 13:44 [PATCH v3 0/4] mips: Add initial Octeon MIPS64 base support Stefan Roese
2020-06-19 13:44 ` [PATCH v3 1/4] sysreset: Add Octeon sysreset driver Stefan Roese
2020-06-19 13:44 ` [PATCH v3 2/4] mips: octeon: Initial minimal support for the Marvell Octeon SoC Stefan Roese
@ 2020-06-19 13:44 ` Stefan Roese
2020-06-19 13:44 ` [PATCH v3 4/4] mips: octeon: Add minimal Octeon 3 EBB7304 EVK support Stefan Roese
3 siblings, 0 replies; 8+ messages in thread
From: Stefan Roese @ 2020-06-19 13:44 UTC (permalink / raw)
To: u-boot
This patch adds the base dtsi file for the Octeon 3 cn73xx SoC.
Signed-off-by: Stefan Roese <sr@denx.de>
---
(no changes since v1)
MAINTAINERS | 1 +
arch/mips/dts/mrvl,cn73xx.dtsi | 64 ++++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+)
create mode 100644 arch/mips/dts/mrvl,cn73xx.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 0aa0357967..6acdbcf8ac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -768,6 +768,7 @@ M: Aaron Williams <awilliams@marvell.com>
S: Maintained
F: arch/mips/mach-octeon/
F: arch/mips/include/asm/arch-octeon/
+F: arch/mips/dts/mrvl,cn73xx.dtsi
MMC
M: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
new file mode 100644
index 0000000000..a7bd55f8ad
--- /dev/null
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell / Cavium Inc. CN73xx
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ soc0: soc at 0 {
+ interrupt-parent = <&ciu3>;
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges; /* Direct mapping */
+
+ ciu3: interrupt-controller at 1010000000000 {
+ compatible = "cavium,octeon-7890-ciu3";
+ interrupt-controller;
+ /*
+ * Interrupts are specified by two parts:
+ * 1) Source number (20 significant bits)
+ * 2) Trigger type: (4 == level, 1 == edge)
+ */
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x10100 0x00000000 0x0 0xb0000000>;
+ };
+
+ bootbus: bootbus at 1180000000000 {
+ compatible = "cavium,octeon-3860-bootbus","simple-bus";
+ reg = <0x11800 0x00000000 0x0 0x200>;
+ /* The chip select number and offset */
+ #address-cells = <2>;
+ /* The size of the chip select region */
+ #size-cells = <1>;
+ };
+
+ reset: reset at 1180006001600 {
+ compatible = "mrvl,cn7xxx-rst";
+ reg = <0x11800 0x06001600 0x0 0x200>;
+ };
+
+ uart0: serial at 1180000000800 {
+ compatible = "cavium,octeon-3860-uart","ns16550";
+ reg = <0x11800 0x00000800 0x0 0x400>;
+ clock-frequency = <0>;
+ current-speed = <115200>;
+ reg-shift = <3>;
+ interrupts = <0x08000 4>;
+ };
+
+ uart1: serial at 1180000000c00 {
+ compatible = "cavium,octeon-3860-uart","ns16550";
+ reg = <0x11800 0x00000c00 0x0 0x400>;
+ clock-frequency = <0>;
+ current-speed = <115200>;
+ reg-shift = <3>;
+ interrupts = <0x08040 4>;
+ };
+ };
+};
--
2.27.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 4/4] mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
2020-06-19 13:44 [PATCH v3 0/4] mips: Add initial Octeon MIPS64 base support Stefan Roese
` (2 preceding siblings ...)
2020-06-19 13:44 ` [PATCH v3 3/4] mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file Stefan Roese
@ 2020-06-19 13:44 ` Stefan Roese
3 siblings, 0 replies; 8+ messages in thread
From: Stefan Roese @ 2020-06-19 13:44 UTC (permalink / raw)
To: u-boot
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on this board.
Supported devices:
- UART
- reset
- CFI parallel NOR flash
Signed-off-by: Stefan Roese <sr@denx.de>
---
Changes in v3:
- Remove inclusion of "common.h"
- Slightly change some copyright messages (adjust year)
Changes in v2:
- Removed CONFIG_SYS_MIPS_TIMER_FREQ
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mrvl,octeon-ebb7304.dts | 96 ++++++++++++++++++++++++
arch/mips/mach-octeon/Kconfig | 14 ++++
board/Marvell/octeon_ebb7304/Kconfig | 19 +++++
board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++
board/Marvell/octeon_ebb7304/Makefile | 8 ++
board/Marvell/octeon_ebb7304/board.c | 9 +++
configs/octeon_ebb7304_defconfig | 37 +++++++++
include/configs/octeon_common.h | 25 ++++++
include/configs/octeon_ebb7304.h | 20 +++++
10 files changed, 236 insertions(+)
create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts
create mode 100644 board/Marvell/octeon_ebb7304/Kconfig
create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS
create mode 100644 board/Marvell/octeon_ebb7304/Makefile
create mode 100644 board/Marvell/octeon_ebb7304/board.c
create mode 100644 configs/octeon_ebb7304_defconfig
create mode 100644 include/configs/octeon_common.h
create mode 100644 include/configs/octeon_ebb7304.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index f711e9fb59..dc85901dca 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
+dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f at st1704.dtb
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts
new file mode 100644
index 0000000000..4e9c2de7d4
--- /dev/null
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell / Cavium Inc. EVB CN7300
+ */
+
+/dts-v1/;
+
+/include/ "mrvl,cn73xx.dtsi"
+
+/ {
+ model = "cavium,ebb7304";
+ compatible = "cavium,ebb7304";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&bootbus {
+ /*
+ * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)
+ * as the initial size is too small for the 8MiB flash device
+ */
+ ranges = <0 0 0 0x1f400000 0xc00000>,
+ <1 0 0x10000 0x10000000 0>,
+ <2 0 0x10000 0x20000000 0>,
+ <3 0 0x10000 0x30000000 0>,
+ <4 0 0 0x1d020000 0x10000>,
+ <5 0 0x10000 0x50000000 0>,
+ <6 0 0x10000 0x60000000 0>,
+ <7 0 0x10000 0x70000000 0>;
+
+ cavium,cs-config at 0 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <0>;
+ cavium,t-adr = <10>;
+ cavium,t-ce = <50>;
+ cavium,t-oe = <50>;
+ cavium,t-we = <35>;
+ cavium,t-rd-hld = <25>;
+ cavium,t-wr-hld = <35>;
+ cavium,t-pause = <0>;
+ cavium,t-wait = <50>;
+ cavium,t-page = <30>;
+ cavium,t-rd-dly = <0>;
+ cavium,page-mode = <1>;
+ cavium,pages = <8>;
+ cavium,bus-width = <8>;
+ };
+
+ cavium,cs-config at 4 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <4>;
+ cavium,t-adr = <10>;
+ cavium,t-ce = <10>;
+ cavium,t-oe = <160>;
+ cavium,t-we = <100>;
+ cavium,t-rd-hld = <10>;
+ cavium,t-wr-hld = <0>;
+ cavium,t-pause = <50>;
+ cavium,t-wait = <50>;
+ cavium,t-page = <10>;
+ cavium,t-rd-dly = <10>;
+ cavium,pages = <0>;
+ cavium,bus-width = <8>;
+ };
+
+ flash0: nor at 0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition at 0 {
+ label = "bootloader";
+ reg = <0 0x340000>;
+ read-only;
+ };
+ partition at 300000 {
+ label = "storage";
+ reg = <0x340000 0x4be000>;
+ };
+ partition at 7fe000 {
+ label = "environment";
+ reg = <0x7fe000 0x2000>;
+ read-only;
+ };
+ };
+};
+
+&uart0 {
+ clock-frequency = <1200000000>;
+};
diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig
index 3c8ca8dd36..e8596ed99a 100644
--- a/arch/mips/mach-octeon/Kconfig
+++ b/arch/mips/mach-octeon/Kconfig
@@ -31,6 +31,18 @@ config SOC_OCTEON3
endchoice
+choice
+ prompt "Octeon 3 board select"
+ default TARGET_OCTEON_EBB7304
+
+config TARGET_OCTEON_EBB7304
+ bool "Marvell Octeon EBB7304"
+ select OCTEON_CN73XX
+ help
+ Choose this for the Octeon EBB7304 board
+
+endchoice
+
config SYS_DCACHE_SIZE
default 32768
@@ -43,4 +55,6 @@ config SYS_ICACHE_SIZE
config SYS_ICACHE_LINE_SIZE
default 128
+source "board/Marvell/octeon_ebb7304/Kconfig"
+
endmenu
diff --git a/board/Marvell/octeon_ebb7304/Kconfig b/board/Marvell/octeon_ebb7304/Kconfig
new file mode 100644
index 0000000000..ab54e6dbbc
--- /dev/null
+++ b/board/Marvell/octeon_ebb7304/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_OCTEON_EBB7304
+
+config SYS_BOARD
+ string
+ default "octeon_ebb7304"
+
+config SYS_VENDOR
+ string
+ default "Marvell"
+
+config SYS_CONFIG_NAME
+ string
+ default "octeon_ebb7304"
+
+config DEFAULT_DEVICE_TREE
+ string
+ default "mrvl,octeon-ebb7304"
+
+endif
diff --git a/board/Marvell/octeon_ebb7304/MAINTAINERS b/board/Marvell/octeon_ebb7304/MAINTAINERS
new file mode 100644
index 0000000000..7256f83567
--- /dev/null
+++ b/board/Marvell/octeon_ebb7304/MAINTAINERS
@@ -0,0 +1,7 @@
+OCTEON_EBB7304 BOARD
+M: Aaron Williams <awilliams@marvell.com>
+S: Maintained
+F: board/Marvell/octeon_ebb7304/*
+F: configs/octeon_ebb7304_defconfig
+F: include/configs/octeon_ebb7304.h
+F: arch/mips/dts/mrvl,octeon-ebb7304.dts
diff --git a/board/Marvell/octeon_ebb7304/Makefile b/board/Marvell/octeon_ebb7304/Makefile
new file mode 100644
index 0000000000..a3ed0c8873
--- /dev/null
+++ b/board/Marvell/octeon_ebb7304/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2020 Stefan Roese <sr@denx.de>
+# Copyright (C) 2019-2020 Marvell International Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c
new file mode 100644
index 0000000000..56e50a9063
--- /dev/null
+++ b/board/Marvell/octeon_ebb7304/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+/*
+ * Nothing included right now. Code will be added in follow-up
+ * patches.
+ */
diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig
new file mode 100644
index 0000000000..0304b1ef8d
--- /dev/null
+++ b/configs/octeon_ebb7304_defconfig
@@ -0,0 +1,37 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0xffffffffbfc00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEBUG_UART_BASE=0x8001180000000800
+CONFIG_DEBUG_UART_CLOCK=1200000000
+CONFIG_ARCH_OCTEON=y
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_ADDR=0x1FBFE000
+CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_ETH=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DEBUG_UART_SHIFT=3
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_OCTEON=y
+CONFIG_HEXDUMP=y
diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h
new file mode 100644
index 0000000000..5d1e74cb76
--- /dev/null
+++ b/include/configs/octeon_common.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-2020
+ * Marvell <www.marvell.com>
+ */
+
+#ifndef __OCTEON_COMMON_H__
+#define __OCTEON_COMMON_H__
+
+/* No DDR init yet -> run in L2 cache with limited resources */
+#define CONFIG_SYS_MALLOC_LEN (256 << 10)
+#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20))
+
+/*
+ * Set a max image size for the image (incl. DTB), so that a growing
+ * image will not exceed this maximum size
+ */
+#define CONFIG_BOARD_SIZE_LIMIT 0x100000 /* 1MiB */
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x180000
+
+#endif /* __OCTEON_COMMON_H__ */
diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h
new file mode 100644
index 0000000000..04fe4dfe22
--- /dev/null
+++ b/include/configs/octeon_ebb7304.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-2020
+ * Marvell <www.marvell.com>
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include "octeon_common.h"
+
+/*
+ * CFI flash
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+
+#endif /* __CONFIG_H__ */
--
2.27.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 1/4] sysreset: Add Octeon sysreset driver
2020-06-19 13:44 ` [PATCH v3 1/4] sysreset: Add Octeon sysreset driver Stefan Roese
@ 2020-06-29 22:11 ` Daniel Schwierzeck
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Schwierzeck @ 2020-06-29 22:11 UTC (permalink / raw)
To: u-boot
> This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
> family.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> ---
>
> (no changes since v1)
>
> drivers/sysreset/Kconfig | 7 ++++
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_octeon.c | 52 ++++++++++++++++++++++++++++++
> 3 files changed, 60 insertions(+)
> create mode 100644 drivers/sysreset/sysreset_octeon.c
>
>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--
- Daniel
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 2/4] mips: octeon: Initial minimal support for the Marvell Octeon SoC
2020-06-19 13:44 ` [PATCH v3 2/4] mips: octeon: Initial minimal support for the Marvell Octeon SoC Stefan Roese
@ 2020-06-29 22:34 ` Daniel Schwierzeck
2020-06-30 9:29 ` Stefan Roese
0 siblings, 1 reply; 8+ messages in thread
From: Daniel Schwierzeck @ 2020-06-29 22:34 UTC (permalink / raw)
To: u-boot
Am Freitag, den 19.06.2020, 15:44 +0200 schrieb Stefan Roese:
> From: Aaron Williams <awilliams@marvell.com>
>
> This patch adds very basic support for the Octeon III SoCs. Only
> CFI parallel NOR flash and UART is supported for now.
>
> Please note that the basic Octeon port does not include the DDR3/4
> initialization yet. This will be added in some follow-up patches
> later. To still use U-Boot on with this port, the L2 cache (4MiB on
> Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
> prompt on such boards.
>
> Signed-off-by: Aaron Williams <awilliams@marvell.com>
> Signed-off-by: Stefan Roese <sr@denx.de>
>
> ---
>
> Changes in v3:
> - Don't "relocate" to L2 cache for now
> - Remove inclusion of "common.h"
>
> Changes in v2:
> - Remove custom start.S and use common start.S. Minimal custom lowlevel
> init code is currently added in the custom lowlevel_init.S. This needs
> to be extended with necessary code, like errata handling etc. But for
> a very first basic port, this seems to be all thats needed to boot on
> the EBB7304 to the prompt.
> - Removed select CREATE_ARCH_SYMLINK
> - Removed Octeon II support, as its currently no added in this patchset
> - Added cache.c to add the platform specific cache functions as no-ops
> for Octeon as the platform is cache coherent
> - Removed CONFIG_MIPS_CACHE_COHERENT
> - Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
> to enable better sync with the Linux files in the future
> - Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
>
> MAINTAINERS | 6 ++
> arch/mips/Kconfig | 41 +++++++++++++
> arch/mips/Makefile | 3 +
> arch/mips/mach-octeon/Kconfig | 46 +++++++++++++++
> arch/mips/mach-octeon/Makefile | 10 ++++
> arch/mips/mach-octeon/cache.c | 20 +++++++
> arch/mips/mach-octeon/clock.c | 27 +++++++++
> arch/mips/mach-octeon/cpu.c | 57 +++++++++++++++++++
> arch/mips/mach-octeon/dram.c | 28 +++++++++
> arch/mips/mach-octeon/include/ioremap.h | 30 ++++++++++
> arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 ++++++++++++++
> arch/mips/mach-octeon/include/mach/clock.h | 22 +++++++
> arch/mips/mach-octeon/lowlevel_init.S | 19 +++++++
> scripts/config_whitelist.txt | 1 -
> 14 files changed, 351 insertions(+), 1 deletion(-)
> create mode 100644 arch/mips/mach-octeon/Kconfig
> create mode 100644 arch/mips/mach-octeon/Makefile
> create mode 100644 arch/mips/mach-octeon/cache.c
> create mode 100644 arch/mips/mach-octeon/clock.c
> create mode 100644 arch/mips/mach-octeon/cpu.c
> create mode 100644 arch/mips/mach-octeon/dram.c
> create mode 100644 arch/mips/mach-octeon/include/ioremap.h
> create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h
> create mode 100644 arch/mips/mach-octeon/include/mach/clock.h
> create mode 100644 arch/mips/mach-octeon/lowlevel_init.S
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1fd975c72f..0aa0357967 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -763,6 +763,12 @@ M: Ezequiel Garcia <ezequiel@collabora.com>
> S: Maintained
> F: arch/mips/mach-jz47xx/
>
> +MIPS Octeon
> +M: Aaron Williams <awilliams@marvell.com>
> +S: Maintained
> +F: arch/mips/mach-octeon/
> +F: arch/mips/include/asm/arch-octeon/
> +
> MMC
> M: Peng Fan <peng.fan@nxp.com>
> S: Maintained
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index bccd06cb0c..dd56da6dae 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -106,6 +106,23 @@ config ARCH_JZ47XX
> select OF_CONTROL
> select DM
>
> +config ARCH_OCTEON
> + bool "Support Marvell Octeon CN7xxx platforms"
> + select CPU_CAVIUM_OCTEON
> + select DISPLAY_CPUINFO
> + select DMA_ADDR_T_64BIT
> + select DM
> + select DM_SERIAL
> + select MIPS_L2_CACHE
> + select MIPS_TUNE_OCTEON3
> + select ROM_EXCEPTION_VECTORS
> + select SUPPORTS_BIG_ENDIAN
> + select SUPPORTS_CPU_MIPS64_OCTEON
> + select PHYS_64BIT
> + select OF_CONTROL
> + select OF_LIVE
> + imply CMD_DM
> +
> config MACH_PIC32
> bool "Support Microchip PIC32"
> select DM
> @@ -160,6 +177,7 @@ source "arch/mips/mach-bmips/Kconfig"
> source "arch/mips/mach-jz47xx/Kconfig"
> source "arch/mips/mach-pic32/Kconfig"
> source "arch/mips/mach-mtmips/Kconfig"
> +source "arch/mips/mach-octeon/Kconfig"
>
> if MIPS
>
> @@ -233,6 +251,14 @@ config CPU_MIPS64_R6
> Choose this option to build a kernel for release 6 or later of the
> MIPS64 architecture.
>
> +config CPU_MIPS64_OCTEON
> + bool "Marvell Octeon series of CPUs"
> + depends on SUPPORTS_CPU_MIPS64_OCTEON
> + select 64BIT
> + help
> + Choose this option for Marvell Octeon CPUs. These CPUs are between
> + MIPS64 R5 and R6 with other extensions.
> +
> endchoice
>
> menu "General setup"
> @@ -408,6 +434,12 @@ config SUPPORTS_CPU_MIPS64_R2
> config SUPPORTS_CPU_MIPS64_R6
> bool
>
> +config SUPPORTS_CPU_MIPS64_OCTEON
> + bool
> +
> +config CPU_CAVIUM_OCTEON
> + bool
> +
> config CPU_MIPS32
> bool
> default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
> @@ -415,6 +447,7 @@ config CPU_MIPS32
> config CPU_MIPS64
> bool
> default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
> + default y if CPU_MIPS64_OCTEON
>
> config MIPS_TUNE_4KC
> bool
> @@ -431,6 +464,9 @@ config MIPS_TUNE_34KC
> config MIPS_TUNE_74KC
> bool
>
> +config MIPS_TUNE_OCTEON3
> + bool
> +
> config 32BIT
> bool
>
> @@ -463,6 +499,11 @@ config MIPS_SRAM_INIT
> before it can be used. If enabled, a function mips_sram_init() will
> be called just before setup_stack_gd.
>
> +config DMA_ADDR_T_64BIT
> + bool
> + help
> + Select this to enable 64-bit DMA addressing
> +
> config SYS_DCACHE_SIZE
> int
> default 0
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index af3f227436..6502aebd29 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -17,6 +17,7 @@ machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
> machine-$(CONFIG_MACH_PIC32) += pic32
> machine-$(CONFIG_ARCH_MTMIPS) += mtmips
> machine-$(CONFIG_ARCH_MSCC) += mscc
> +machine-${CONFIG_ARCH_OCTEON} += octeon
>
> machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
> libs-y += $(machdirs)
> @@ -30,6 +31,7 @@ arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6
> arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
> arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
> arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
> +arch-${CONFIG_CPU_MIPS64_OCTEON} += -march=octeon2
>
> # Allow extra optimization for specific CPUs/SoCs
> tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
> @@ -37,6 +39,7 @@ tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
> tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
> tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
> tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
> +tune-${CONFIG_MIPS_TUNE_OCTEON3} += -mtune=octeon2
>
> # Include default header files
> cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
> diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig
> new file mode 100644
> index 0000000000..3c8ca8dd36
> --- /dev/null
> +++ b/arch/mips/mach-octeon/Kconfig
> @@ -0,0 +1,46 @@
> +menu "Octeon platforms"
> + depends on ARCH_OCTEON
> +
> +config SYS_SOC
> + string
> + default "octeon"
> +
> +config OCTEON_CN7XXX
> + bool "Octeon CN7XXX SoC"
> +
> +config OCTEON_CN70XX
> + bool "Octeon CN70XX SoC"
> + select OCTEON_CN7XXX
> +
> +config OCTEON_CN73XX
> + bool "Octeon CN73XX SoC"
> + select OCTEON_CN7XXX
> +
> +config OCTEON_CN78XX
> + bool "Octeon CN78XX SoC"
> + select OCTEON_CN7XXX
> +
> +choice
> + prompt "Octeon MIPS family select"
> +
> +config SOC_OCTEON3
> + bool "Octeon III family"
> + help
> + This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx
> + and CNF75XX.
> +
> +endchoice
> +
> +config SYS_DCACHE_SIZE
> + default 32768
> +
> +config SYS_DCACHE_LINE_SIZE
> + default 128
> +
> +config SYS_ICACHE_SIZE
> + default 79872
> +
> +config SYS_ICACHE_LINE_SIZE
> + default 128
> +
> +endmenu
> diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile
> new file mode 100644
> index 0000000000..2e37ca572c
> --- /dev/null
> +++ b/arch/mips/mach-octeon/Makefile
> @@ -0,0 +1,10 @@
> +# (C) Copyright 2019 Marvell, Inc.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += lowlevel_init.o
> +obj-y += cache.o
> +obj-y += clock.o
> +obj-y += cpu.o
> +obj-y += dram.o
> diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c
> new file mode 100644
> index 0000000000..bea846d757
> --- /dev/null
> +++ b/arch/mips/mach-octeon/cache.c
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 Marvell International Ltd.
> + */
> +
> +#include <cpu_func.h>
> +
> +/*
> + * The Octeon platform is cache coherent and cache flushes and invalidates
> + * are not needed. Define some platform specific empty flush_foo()
> + * functions here to overwrite the _weak common function as a no-op.
> + * This effectively disables all cache operations.
> + */
> +void flush_dcache_range(ulong start_addr, ulong stop)
> +{
> +}
> +
> +void flush_cache(ulong start_addr, ulong size)
> +{
> +}
> diff --git a/arch/mips/mach-octeon/clock.c b/arch/mips/mach-octeon/clock.c
> new file mode 100644
> index 0000000000..fc3776dc8f
> --- /dev/null
> +++ b/arch/mips/mach-octeon/clock.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018, 2019 Marvell International Ltd.
> + */
> +
> +#include <asm/global_data.h>
> +#include <mach/clock.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +ulong notrace get_tbclk(void)
> +{
> + return gd->cpu_clk;
> +}
> +
> +int octeon_get_timer_freq(void)
> +{
> + return gd->cpu_clk;
> +}
> +
> +/**
> + * Returns the I/O clock speed in Hz
> + */
> +u64 octeon_get_io_clock(void)
> +{
> + return gd->bus_clk;
> +}
do you plan to add a clock driver later? Than you could use the generic
clock API in driver and wouldn't need to add custom functions ;)
> diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
> new file mode 100644
> index 0000000000..7ef17a7d66
> --- /dev/null
> +++ b/arch/mips/mach-octeon/cpu.c
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 Marvell International Ltd.
> + */
> +
> +#include <asm/global_data.h>
> +#include <linux/bitops.h>
> +#include <linux/compat.h>
> +#include <linux/io.h>
> +#include <mach/clock.h>
> +#include <mach/cavm-reg.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static int get_clocks(void)
> +{
> + const u64 ref_clock = PLL_REF_CLK;
> + union cavm_rst_boot rst_boot;
> +
> + rst_boot.u = ioread64(CAVM_RST_BOOT);
> + gd->cpu_clk = ref_clock * rst_boot.s.c_mul;
> + gd->bus_clk = ref_clock * rst_boot.s.pnr_mul;
> +
> + debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
> +
> + return 0;
> +}
> +
> +/* Early mach init code run from flash */
> +int mach_cpu_init(void)
> +{
> + /* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
> + /* ToDo: Move this to an early running bus (bootbus) DM driver */
> + clrsetbits_be64(CAVM_MIO_BOOT_REG_CFG0, 0xffff, 0x1f40);
> +
> + /* Get clocks and store them in GD */
> + get_clocks();
> +
> + return 0;
> +}
> +
> +/**
> + * Returns number of cores
> + *
> + * @return number of CPU cores for the specified node
> + */
> +static int cavm_octeon_num_cores(void)
> +{
> + return fls64(ioread64(CAVM_CIU_FUSE) & 0xffffffffffff);
> +}
> +
> +int print_cpuinfo(void)
> +{
> + printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
> +
> + return 0;
> +}
> diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
> new file mode 100644
> index 0000000000..ff7a59f2ab
> --- /dev/null
> +++ b/arch/mips/mach-octeon/dram.c
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) Stefan Roese <sr@denx.de>
> + */
> +
> +#include <dm.h>
> +#include <ram.h>
> +#include <asm/global_data.h>
> +#include <linux/compat.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + /*
> + * No DDR init yet -> run in L2 cache
> + */
> + gd->ram_size = (4 << 20);
> + gd->bd->bi_dram[0].size = gd->ram_size;
> + gd->bd->bi_dram[1].size = 0;
> +
> + return 0;
> +}
> +
> +ulong board_get_usable_ram_top(ulong total_size)
> +{
> + return gd->ram_top;
> +}
> diff --git a/arch/mips/mach-octeon/include/ioremap.h b/arch/mips/mach-octeon/include/ioremap.h
> new file mode 100644
> index 0000000000..59b75008a2
> --- /dev/null
> +++ b/arch/mips/mach-octeon/include/ioremap.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __ASM_MACH_OCTEON_IOREMAP_H
> +#define __ASM_MACH_OCTEON_IOREMAP_H
> +
> +#include <linux/types.h>
> +
> +/*
> + * Allow physical addresses to be fixed up to help peripherals located
> + * outside the low 32-bit range -- generic pass-through version.
> + */
> +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
> + phys_addr_t size)
> +{
> + return phys_addr;
> +}
> +
> +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
> + unsigned long flags)
> +{
> + return (void __iomem *)(XKPHYS | offset);
> +}
> +
> +static inline int plat_iounmap(const volatile void __iomem *addr)
> +{
> + return 0;
> +}
> +
> +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
> +
> +#endif /* __ASM_MACH_OCTEON_IOREMAP_H */
> diff --git a/arch/mips/mach-octeon/include/mach/cavm-reg.h b/arch/mips/mach-octeon/include/mach/cavm-reg.h
> new file mode 100644
> index 0000000000..b961e54956
> --- /dev/null
> +++ b/arch/mips/mach-octeon/include/mach/cavm-reg.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020 Marvell International Ltd.
> + */
> +
> +#ifndef __CAVM_REG_H__
> +
> +/* Register offsets */
> +#define CAVM_CIU_FUSE ((u64 *)0x80010100000001a0)
> +#define CAVM_MIO_BOOT_REG_CFG0 ((u64 *)0x8001180000000000)
> +#define CAVM_RST_BOOT ((u64 *)0x8001180006001600)
are those mapped or mappable addresses? The preferred way would be to
just define the physical address and do a ioremap when needed. For
example:
void __iomem *rst_boot = ioremap(CAVM_RST_BOOT, 0);
If not mappable, just define the addresses without the (u64 *) cast and
do that in the code when needed like that:
void __iomem *rst_boot = (void __iomem *)CAVM_RST_BOOT;
> +
> +/* Register structs */
> +
> +/**
> + * Register (RSL) rst_boot
> + *
> + * RST Boot Register
> + */
> +union cavm_rst_boot {
> + u64 u;
> + struct cavm_rst_boot_s {
> + u64 chipkill : 1;
> + u64 jtcsrdis : 1;
> + u64 ejtagdis : 1;
> + u64 romen : 1;
> + u64 ckill_ppdis : 1;
> + u64 jt_tstmode : 1;
> + u64 vrm_err : 1;
> + u64 reserved_37_56 : 20;
> + u64 c_mul : 7;
> + u64 pnr_mul : 6;
> + u64 reserved_21_23 : 3;
> + u64 lboot_oci : 3;
> + u64 lboot_ext : 6;
> + u64 lboot : 10;
> + u64 rboot : 1;
> + u64 rboot_pin : 1;
> + } s;
> +};
I'm not sure but bitfields are maybe frowned upon. I guess the usual
and preferred way would be to just define the really needed bits and
masks with BIT() and GENMASK().
> +
> +#endif /* __CAVM_REG_H__ */
> diff --git a/arch/mips/mach-octeon/include/mach/clock.h b/arch/mips/mach-octeon/include/mach/clock.h
> new file mode 100644
> index 0000000000..a3c1d8b2cd
> --- /dev/null
> +++ b/arch/mips/mach-octeon/include/mach/clock.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2018, 2019 Marvell International Ltd.
> + */
> +
> +#ifndef __CLOCK_H__
> +
> +/** System PLL reference clock */
> +#define PLL_REF_CLK 50000000 /* 50 MHz */
> +#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK)
> +
> +/**
> + * Returns the I/O clock speed in Hz
> + */
> +u64 octeon_get_io_clock(void);
> +
> +/**
> + * Returns the core clock speed in Hz
> + */
> +u64 octeon_get_core_clock(void);
> +
> +#endif /* __CLOCK_H__ */
> diff --git a/arch/mips/mach-octeon/lowlevel_init.S b/arch/mips/mach-octeon/lowlevel_init.S
> new file mode 100644
> index 0000000000..d9aab38cde
> --- /dev/null
> +++ b/arch/mips/mach-octeon/lowlevel_init.S
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020 Stefan Roese <sr@denx.de>
> + */
> +
> +#include <config.h>
> +#include <asm-offsets.h>
> +#include <asm/cacheops.h>
> +#include <asm/regdef.h>
> +#include <asm/mipsregs.h>
> +#include <asm/addrspace.h>
> +#include <asm/asm.h>
> +
> + .set noreorder
> +
> +LEAF(lowlevel_init)
> + jr ra
> + nop
> + END(lowlevel_init)
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index f6bf6f2474..f0e13389d0 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -230,7 +230,6 @@ CONFIG_CPLD_BR_PRELIM
> CONFIG_CPLD_OR_PRELIM
> CONFIG_CPM2
> CONFIG_CPU_ARMV8
> -CONFIG_CPU_CAVIUM_OCTEON
> CONFIG_CPU_FREQ_HZ
> CONFIG_CPU_HAS_LLSC
> CONFIG_CPU_HAS_PREFETCH
--
- Daniel
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 2/4] mips: octeon: Initial minimal support for the Marvell Octeon SoC
2020-06-29 22:34 ` Daniel Schwierzeck
@ 2020-06-30 9:29 ` Stefan Roese
0 siblings, 0 replies; 8+ messages in thread
From: Stefan Roese @ 2020-06-30 9:29 UTC (permalink / raw)
To: u-boot
On 30.06.20 00:34, Daniel Schwierzeck wrote:
> Am Freitag, den 19.06.2020, 15:44 +0200 schrieb Stefan Roese:
>> From: Aaron Williams <awilliams@marvell.com>
>>
>> This patch adds very basic support for the Octeon III SoCs. Only
>> CFI parallel NOR flash and UART is supported for now.
>>
>> Please note that the basic Octeon port does not include the DDR3/4
>> initialization yet. This will be added in some follow-up patches
>> later. To still use U-Boot on with this port, the L2 cache (4MiB on
>> Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
>> prompt on such boards.
>>
>> Signed-off-by: Aaron Williams <awilliams@marvell.com>
>> Signed-off-by: Stefan Roese <sr@denx.de>
>>
>> ---
>>
>> Changes in v3:
>> - Don't "relocate" to L2 cache for now
>> - Remove inclusion of "common.h"
>>
>> Changes in v2:
>> - Remove custom start.S and use common start.S. Minimal custom lowlevel
>> init code is currently added in the custom lowlevel_init.S. This needs
>> to be extended with necessary code, like errata handling etc. But for
>> a very first basic port, this seems to be all thats needed to boot on
>> the EBB7304 to the prompt.
>> - Removed select CREATE_ARCH_SYMLINK
>> - Removed Octeon II support, as its currently no added in this patchset
>> - Added cache.c to add the platform specific cache functions as no-ops
>> for Octeon as the platform is cache coherent
>> - Removed CONFIG_MIPS_CACHE_COHERENT
>> - Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
>> to enable better sync with the Linux files in the future
>> - Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
>>
>> MAINTAINERS | 6 ++
>> arch/mips/Kconfig | 41 +++++++++++++
>> arch/mips/Makefile | 3 +
>> arch/mips/mach-octeon/Kconfig | 46 +++++++++++++++
>> arch/mips/mach-octeon/Makefile | 10 ++++
>> arch/mips/mach-octeon/cache.c | 20 +++++++
>> arch/mips/mach-octeon/clock.c | 27 +++++++++
>> arch/mips/mach-octeon/cpu.c | 57 +++++++++++++++++++
>> arch/mips/mach-octeon/dram.c | 28 +++++++++
>> arch/mips/mach-octeon/include/ioremap.h | 30 ++++++++++
>> arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 ++++++++++++++
>> arch/mips/mach-octeon/include/mach/clock.h | 22 +++++++
>> arch/mips/mach-octeon/lowlevel_init.S | 19 +++++++
>> scripts/config_whitelist.txt | 1 -
>> 14 files changed, 351 insertions(+), 1 deletion(-)
>> create mode 100644 arch/mips/mach-octeon/Kconfig
>> create mode 100644 arch/mips/mach-octeon/Makefile
>> create mode 100644 arch/mips/mach-octeon/cache.c
>> create mode 100644 arch/mips/mach-octeon/clock.c
>> create mode 100644 arch/mips/mach-octeon/cpu.c
>> create mode 100644 arch/mips/mach-octeon/dram.c
>> create mode 100644 arch/mips/mach-octeon/include/ioremap.h
>> create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h
>> create mode 100644 arch/mips/mach-octeon/include/mach/clock.h
>> create mode 100644 arch/mips/mach-octeon/lowlevel_init.S
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 1fd975c72f..0aa0357967 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -763,6 +763,12 @@ M: Ezequiel Garcia <ezequiel@collabora.com>
>> S: Maintained
>> F: arch/mips/mach-jz47xx/
>>
>> +MIPS Octeon
>> +M: Aaron Williams <awilliams@marvell.com>
>> +S: Maintained
>> +F: arch/mips/mach-octeon/
>> +F: arch/mips/include/asm/arch-octeon/
>> +
>> MMC
>> M: Peng Fan <peng.fan@nxp.com>
>> S: Maintained
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index bccd06cb0c..dd56da6dae 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -106,6 +106,23 @@ config ARCH_JZ47XX
>> select OF_CONTROL
>> select DM
>>
>> +config ARCH_OCTEON
>> + bool "Support Marvell Octeon CN7xxx platforms"
>> + select CPU_CAVIUM_OCTEON
>> + select DISPLAY_CPUINFO
>> + select DMA_ADDR_T_64BIT
>> + select DM
>> + select DM_SERIAL
>> + select MIPS_L2_CACHE
>> + select MIPS_TUNE_OCTEON3
>> + select ROM_EXCEPTION_VECTORS
>> + select SUPPORTS_BIG_ENDIAN
>> + select SUPPORTS_CPU_MIPS64_OCTEON
>> + select PHYS_64BIT
>> + select OF_CONTROL
>> + select OF_LIVE
>> + imply CMD_DM
>> +
>> config MACH_PIC32
>> bool "Support Microchip PIC32"
>> select DM
>> @@ -160,6 +177,7 @@ source "arch/mips/mach-bmips/Kconfig"
>> source "arch/mips/mach-jz47xx/Kconfig"
>> source "arch/mips/mach-pic32/Kconfig"
>> source "arch/mips/mach-mtmips/Kconfig"
>> +source "arch/mips/mach-octeon/Kconfig"
>>
>> if MIPS
>>
>> @@ -233,6 +251,14 @@ config CPU_MIPS64_R6
>> Choose this option to build a kernel for release 6 or later of the
>> MIPS64 architecture.
>>
>> +config CPU_MIPS64_OCTEON
>> + bool "Marvell Octeon series of CPUs"
>> + depends on SUPPORTS_CPU_MIPS64_OCTEON
>> + select 64BIT
>> + help
>> + Choose this option for Marvell Octeon CPUs. These CPUs are between
>> + MIPS64 R5 and R6 with other extensions.
>> +
>> endchoice
>>
>> menu "General setup"
>> @@ -408,6 +434,12 @@ config SUPPORTS_CPU_MIPS64_R2
>> config SUPPORTS_CPU_MIPS64_R6
>> bool
>>
>> +config SUPPORTS_CPU_MIPS64_OCTEON
>> + bool
>> +
>> +config CPU_CAVIUM_OCTEON
>> + bool
>> +
>> config CPU_MIPS32
>> bool
>> default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
>> @@ -415,6 +447,7 @@ config CPU_MIPS32
>> config CPU_MIPS64
>> bool
>> default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
>> + default y if CPU_MIPS64_OCTEON
>>
>> config MIPS_TUNE_4KC
>> bool
>> @@ -431,6 +464,9 @@ config MIPS_TUNE_34KC
>> config MIPS_TUNE_74KC
>> bool
>>
>> +config MIPS_TUNE_OCTEON3
>> + bool
>> +
>> config 32BIT
>> bool
>>
>> @@ -463,6 +499,11 @@ config MIPS_SRAM_INIT
>> before it can be used. If enabled, a function mips_sram_init() will
>> be called just before setup_stack_gd.
>>
>> +config DMA_ADDR_T_64BIT
>> + bool
>> + help
>> + Select this to enable 64-bit DMA addressing
>> +
>> config SYS_DCACHE_SIZE
>> int
>> default 0
>> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
>> index af3f227436..6502aebd29 100644
>> --- a/arch/mips/Makefile
>> +++ b/arch/mips/Makefile
>> @@ -17,6 +17,7 @@ machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
>> machine-$(CONFIG_MACH_PIC32) += pic32
>> machine-$(CONFIG_ARCH_MTMIPS) += mtmips
>> machine-$(CONFIG_ARCH_MSCC) += mscc
>> +machine-${CONFIG_ARCH_OCTEON} += octeon
>>
>> machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
>> libs-y += $(machdirs)
>> @@ -30,6 +31,7 @@ arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6
>> arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
>> arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
>> arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
>> +arch-${CONFIG_CPU_MIPS64_OCTEON} += -march=octeon2
>>
>> # Allow extra optimization for specific CPUs/SoCs
>> tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
>> @@ -37,6 +39,7 @@ tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
>> tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
>> tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
>> tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
>> +tune-${CONFIG_MIPS_TUNE_OCTEON3} += -mtune=octeon2
>>
>> # Include default header files
>> cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
>> diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig
>> new file mode 100644
>> index 0000000000..3c8ca8dd36
>> --- /dev/null
>> +++ b/arch/mips/mach-octeon/Kconfig
>> @@ -0,0 +1,46 @@
>> +menu "Octeon platforms"
>> + depends on ARCH_OCTEON
>> +
>> +config SYS_SOC
>> + string
>> + default "octeon"
>> +
>> +config OCTEON_CN7XXX
>> + bool "Octeon CN7XXX SoC"
>> +
>> +config OCTEON_CN70XX
>> + bool "Octeon CN70XX SoC"
>> + select OCTEON_CN7XXX
>> +
>> +config OCTEON_CN73XX
>> + bool "Octeon CN73XX SoC"
>> + select OCTEON_CN7XXX
>> +
>> +config OCTEON_CN78XX
>> + bool "Octeon CN78XX SoC"
>> + select OCTEON_CN7XXX
>> +
>> +choice
>> + prompt "Octeon MIPS family select"
>> +
>> +config SOC_OCTEON3
>> + bool "Octeon III family"
>> + help
>> + This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx
>> + and CNF75XX.
>> +
>> +endchoice
>> +
>> +config SYS_DCACHE_SIZE
>> + default 32768
>> +
>> +config SYS_DCACHE_LINE_SIZE
>> + default 128
>> +
>> +config SYS_ICACHE_SIZE
>> + default 79872
>> +
>> +config SYS_ICACHE_LINE_SIZE
>> + default 128
>> +
>> +endmenu
>> diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile
>> new file mode 100644
>> index 0000000000..2e37ca572c
>> --- /dev/null
>> +++ b/arch/mips/mach-octeon/Makefile
>> @@ -0,0 +1,10 @@
>> +# (C) Copyright 2019 Marvell, Inc.
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-y += lowlevel_init.o
>> +obj-y += cache.o
>> +obj-y += clock.o
>> +obj-y += cpu.o
>> +obj-y += dram.o
>> diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c
>> new file mode 100644
>> index 0000000000..bea846d757
>> --- /dev/null
>> +++ b/arch/mips/mach-octeon/cache.c
>> @@ -0,0 +1,20 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2020 Marvell International Ltd.
>> + */
>> +
>> +#include <cpu_func.h>
>> +
>> +/*
>> + * The Octeon platform is cache coherent and cache flushes and invalidates
>> + * are not needed. Define some platform specific empty flush_foo()
>> + * functions here to overwrite the _weak common function as a no-op.
>> + * This effectively disables all cache operations.
>> + */
>> +void flush_dcache_range(ulong start_addr, ulong stop)
>> +{
>> +}
>> +
>> +void flush_cache(ulong start_addr, ulong size)
>> +{
>> +}
>> diff --git a/arch/mips/mach-octeon/clock.c b/arch/mips/mach-octeon/clock.c
>> new file mode 100644
>> index 0000000000..fc3776dc8f
>> --- /dev/null
>> +++ b/arch/mips/mach-octeon/clock.c
>> @@ -0,0 +1,27 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018, 2019 Marvell International Ltd.
>> + */
>> +
>> +#include <asm/global_data.h>
>> +#include <mach/clock.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +ulong notrace get_tbclk(void)
>> +{
>> + return gd->cpu_clk;
>> +}
>> +
>> +int octeon_get_timer_freq(void)
>> +{
>> + return gd->cpu_clk;
>> +}
>> +
>> +/**
>> + * Returns the I/O clock speed in Hz
>> + */
>> +u64 octeon_get_io_clock(void)
>> +{
>> + return gd->bus_clk;
>> +}
>
> do you plan to add a clock driver later? Than you could use the generic
> clock API in driver and wouldn't need to add custom functions ;)
I know thats a bit cumbersome. I'll remove the custom functions
in the next version.
>> diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
>> new file mode 100644
>> index 0000000000..7ef17a7d66
>> --- /dev/null
>> +++ b/arch/mips/mach-octeon/cpu.c
>> @@ -0,0 +1,57 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2020 Marvell International Ltd.
>> + */
>> +
>> +#include <asm/global_data.h>
>> +#include <linux/bitops.h>
>> +#include <linux/compat.h>
>> +#include <linux/io.h>
>> +#include <mach/clock.h>
>> +#include <mach/cavm-reg.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static int get_clocks(void)
>> +{
>> + const u64 ref_clock = PLL_REF_CLK;
>> + union cavm_rst_boot rst_boot;
>> +
>> + rst_boot.u = ioread64(CAVM_RST_BOOT);
>> + gd->cpu_clk = ref_clock * rst_boot.s.c_mul;
>> + gd->bus_clk = ref_clock * rst_boot.s.pnr_mul;
>> +
>> + debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
>> +
>> + return 0;
>> +}
>> +
>> +/* Early mach init code run from flash */
>> +int mach_cpu_init(void)
>> +{
>> + /* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
>> + /* ToDo: Move this to an early running bus (bootbus) DM driver */
>> + clrsetbits_be64(CAVM_MIO_BOOT_REG_CFG0, 0xffff, 0x1f40);
>> +
>> + /* Get clocks and store them in GD */
>> + get_clocks();
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + * Returns number of cores
>> + *
>> + * @return number of CPU cores for the specified node
>> + */
>> +static int cavm_octeon_num_cores(void)
>> +{
>> + return fls64(ioread64(CAVM_CIU_FUSE) & 0xffffffffffff);
>> +}
>> +
>> +int print_cpuinfo(void)
>> +{
>> + printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
>> +
>> + return 0;
>> +}
>> diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
>> new file mode 100644
>> index 0000000000..ff7a59f2ab
>> --- /dev/null
>> +++ b/arch/mips/mach-octeon/dram.c
>> @@ -0,0 +1,28 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) Stefan Roese <sr@denx.de>
>> + */
>> +
>> +#include <dm.h>
>> +#include <ram.h>
>> +#include <asm/global_data.h>
>> +#include <linux/compat.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int dram_init(void)
>> +{
>> + /*
>> + * No DDR init yet -> run in L2 cache
>> + */
>> + gd->ram_size = (4 << 20);
>> + gd->bd->bi_dram[0].size = gd->ram_size;
>> + gd->bd->bi_dram[1].size = 0;
>> +
>> + return 0;
>> +}
>> +
>> +ulong board_get_usable_ram_top(ulong total_size)
>> +{
>> + return gd->ram_top;
>> +}
>> diff --git a/arch/mips/mach-octeon/include/ioremap.h b/arch/mips/mach-octeon/include/ioremap.h
>> new file mode 100644
>> index 0000000000..59b75008a2
>> --- /dev/null
>> +++ b/arch/mips/mach-octeon/include/ioremap.h
>> @@ -0,0 +1,30 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +#ifndef __ASM_MACH_OCTEON_IOREMAP_H
>> +#define __ASM_MACH_OCTEON_IOREMAP_H
>> +
>> +#include <linux/types.h>
>> +
>> +/*
>> + * Allow physical addresses to be fixed up to help peripherals located
>> + * outside the low 32-bit range -- generic pass-through version.
>> + */
>> +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
>> + phys_addr_t size)
>> +{
>> + return phys_addr;
>> +}
>> +
>> +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
>> + unsigned long flags)
>> +{
>> + return (void __iomem *)(XKPHYS | offset);
>> +}
>> +
>> +static inline int plat_iounmap(const volatile void __iomem *addr)
>> +{
>> + return 0;
>> +}
>> +
>> +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
>> +
>> +#endif /* __ASM_MACH_OCTEON_IOREMAP_H */
>> diff --git a/arch/mips/mach-octeon/include/mach/cavm-reg.h b/arch/mips/mach-octeon/include/mach/cavm-reg.h
>> new file mode 100644
>> index 0000000000..b961e54956
>> --- /dev/null
>> +++ b/arch/mips/mach-octeon/include/mach/cavm-reg.h
>> @@ -0,0 +1,42 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2020 Marvell International Ltd.
>> + */
>> +
>> +#ifndef __CAVM_REG_H__
>> +
>> +/* Register offsets */
>> +#define CAVM_CIU_FUSE ((u64 *)0x80010100000001a0)
>> +#define CAVM_MIO_BOOT_REG_CFG0 ((u64 *)0x8001180000000000)
>> +#define CAVM_RST_BOOT ((u64 *)0x8001180006001600)
>
> are those mapped or mappable addresses? The preferred way would be to
> just define the physical address and do a ioremap when needed. For
> example:
>
> void __iomem *rst_boot = ioremap(CAVM_RST_BOOT, 0);
Will update in next version.
> If not mappable, just define the addresses without the (u64 *) cast and
> do that in the code when needed like that:
>
> void __iomem *rst_boot = (void __iomem *)CAVM_RST_BOOT;
>
>
>> +
>> +/* Register structs */
>> +
>> +/**
>> + * Register (RSL) rst_boot
>> + *
>> + * RST Boot Register
>> + */
>> +union cavm_rst_boot {
>> + u64 u;
>> + struct cavm_rst_boot_s {
>> + u64 chipkill : 1;
>> + u64 jtcsrdis : 1;
>> + u64 ejtagdis : 1;
>> + u64 romen : 1;
>> + u64 ckill_ppdis : 1;
>> + u64 jt_tstmode : 1;
>> + u64 vrm_err : 1;
>> + u64 reserved_37_56 : 20;
>> + u64 c_mul : 7;
>> + u64 pnr_mul : 6;
>> + u64 reserved_21_23 : 3;
>> + u64 lboot_oci : 3;
>> + u64 lboot_ext : 6;
>> + u64 lboot : 10;
>> + u64 rboot : 1;
>> + u64 rboot_pin : 1;
>> + } s;
>> +};
>
> I'm not sure but bitfields are maybe frowned upon.
I'm not too happy with them as well. But that's whats used in the
original Octeon code. I assume that its auto generated.
> I guess the usual
> and preferred way would be to just define the really needed bits and
> masks with BIT() and GENMASK().
I agree. Using bitfields also has the great disadvantage, that it
can't be used with different endianesses. And this hits us when
using drivers for MIPS Octeon and ARM Octeon TX/TX2 (like I2C etc).
I'll move to BIT() etc in the next version here.
>> +
>> +#endif /* __CAVM_REG_H__ */
>> diff --git a/arch/mips/mach-octeon/include/mach/clock.h b/arch/mips/mach-octeon/include/mach/clock.h
>> new file mode 100644
>> index 0000000000..a3c1d8b2cd
>> --- /dev/null
>> +++ b/arch/mips/mach-octeon/include/mach/clock.h
>> @@ -0,0 +1,22 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2018, 2019 Marvell International Ltd.
>> + */
>> +
>> +#ifndef __CLOCK_H__
>> +
>> +/** System PLL reference clock */
>> +#define PLL_REF_CLK 50000000 /* 50 MHz */
>> +#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK)
>> +
>> +/**
>> + * Returns the I/O clock speed in Hz
>> + */
>> +u64 octeon_get_io_clock(void);
>> +
>> +/**
>> + * Returns the core clock speed in Hz
>> + */
>> +u64 octeon_get_core_clock(void);
>> +
>> +#endif /* __CLOCK_H__ */
>> diff --git a/arch/mips/mach-octeon/lowlevel_init.S b/arch/mips/mach-octeon/lowlevel_init.S
>> new file mode 100644
>> index 0000000000..d9aab38cde
>> --- /dev/null
>> +++ b/arch/mips/mach-octeon/lowlevel_init.S
>> @@ -0,0 +1,19 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2020 Stefan Roese <sr@denx.de>
>> + */
>> +
>> +#include <config.h>
>> +#include <asm-offsets.h>
>> +#include <asm/cacheops.h>
>> +#include <asm/regdef.h>
>> +#include <asm/mipsregs.h>
>> +#include <asm/addrspace.h>
>> +#include <asm/asm.h>
>> +
>> + .set noreorder
>> +
>> +LEAF(lowlevel_init)
>> + jr ra
>> + nop
>> + END(lowlevel_init)
>> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
>> index f6bf6f2474..f0e13389d0 100644
>> --- a/scripts/config_whitelist.txt
>> +++ b/scripts/config_whitelist.txt
>> @@ -230,7 +230,6 @@ CONFIG_CPLD_BR_PRELIM
>> CONFIG_CPLD_OR_PRELIM
>> CONFIG_CPM2
>> CONFIG_CPU_ARMV8
>> -CONFIG_CPU_CAVIUM_OCTEON
>> CONFIG_CPU_FREQ_HZ
>> CONFIG_CPU_HAS_LLSC
>> CONFIG_CPU_HAS_PREFETCH
Viele Gr??e,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-06-30 9:29 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-06-19 13:44 [PATCH v3 0/4] mips: Add initial Octeon MIPS64 base support Stefan Roese
2020-06-19 13:44 ` [PATCH v3 1/4] sysreset: Add Octeon sysreset driver Stefan Roese
2020-06-29 22:11 ` Daniel Schwierzeck
2020-06-19 13:44 ` [PATCH v3 2/4] mips: octeon: Initial minimal support for the Marvell Octeon SoC Stefan Roese
2020-06-29 22:34 ` Daniel Schwierzeck
2020-06-30 9:29 ` Stefan Roese
2020-06-19 13:44 ` [PATCH v3 3/4] mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file Stefan Roese
2020-06-19 13:44 ` [PATCH v3 4/4] mips: octeon: Add minimal Octeon 3 EBB7304 EVK support Stefan Roese
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