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[173.73.95.180]) by smtp.gmail.com with ESMTPSA id f4-20020ac840c4000000b003b9bb59543fsm7568882qtm.61.2023.02.12.09.58.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 12 Feb 2023 09:58:24 -0800 (PST) Message-ID: <47ec0b66-5dca-5149-d72f-e2439c0187e8@gmail.com> Date: Sun, 12 Feb 2023 12:58:23 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v3 07/10] clk: uniphier: Add missing USB SS-PHY clocks Content-Language: en-US To: Kunihiko Hayashi , Marek Vasut , Michal Simek , Angus Ainslie , Lukasz Majewski , T Karthik Reddy , Jan Kiszka Cc: u-boot@lists.denx.de References: <20230208091529.31356-1-hayashi.kunihiko@socionext.com> <20230208091529.31356-8-hayashi.kunihiko@socionext.com> From: Sean Anderson In-Reply-To: <20230208091529.31356-8-hayashi.kunihiko@socionext.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 2/8/23 04:15, Kunihiko Hayashi wrote: > The USB SS-PHY needs its own clock, however, some clocks don't have > clock gates. Define missing clock entries for the PHY as reference > clock. > > Signed-off-by: Kunihiko Hayashi > --- > drivers/clk/uniphier/clk-uniphier-sys.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c > index ff5d364f5978..3b8595fe610a 100644 > --- a/drivers/clk/uniphier/clk-uniphier-sys.c > +++ b/drivers/clk/uniphier/clk-uniphier-sys.c > @@ -28,7 +28,10 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { > UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ > UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ > UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */ > + UNIPHIER_CLK_RATE(17, 25000000), /* usb30-phy2 (PXs2) */ > + UNIPHIER_CLK_RATE(18, 25000000), /* usb30-phy3 (PXs2) */ > UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20), /* usb31-phy (PXs2) */ > + UNIPHIER_CLK_RATE(21, 25000000), /* usb31-phy2 (PXs2) */ > UNIPHIER_CLK_GATE_SIMPLE(24, 0x2108, 2), /* pcie (Pro5) */ > { /* sentinel */ } > #endif > @@ -44,6 +47,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { > UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ > UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ > UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13), /* usb30-phy1 (LD20) */ > + UNIPHIER_CLK_RATE(18, 25000000), /* usb30-phy2 (LD20) */ > + UNIPHIER_CLK_RATE(19, 25000000), /* usb30-phy3 (LD20) */ > UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 4), /* pcie */ > { /* sentinel */ } > #endif Acked-by: Sean Anderson