From: Andrew E. Mileski <andrewm@isoar.ca>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] ppc440: EBC 32-bit bus width setting
Date: Wed, 23 Apr 2008 17:45:48 -0400 [thread overview]
Message-ID: <480FAE0C.7040407@isoar.ca> (raw)
This affects EBC_BXCR_BW_32BIT defined in include/ppc440.h
According to the AMCC 440EPx User Manual (v1.14), pg 591, figure 22-18,
BW (bits 17:18) should be 10 for a 32-bit bus width. This is also
repeated for the NAND controller, section 23.4.5 on pg 600.
According to the IBM 440GX User's Manual (November 21, 2003), pg 1037,
figure 30-23, BW (bits 17:18) should be 11. A rather old manual.
Can others help confirm the settings for these processors and other 440
family members.
Thanks.
--
Andrew E. Mileski
next reply other threads:[~2008-04-23 21:45 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-04-23 21:45 Andrew E. Mileski [this message]
2008-04-24 5:19 ` [U-Boot-Users] ppc440: EBC 32-bit bus width setting Stefan Roese
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