From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dave Littell <littelld@verizon.net>
Date: Thu, 24 Apr 2008 21:34:10 -0500
Subject: [U-Boot-Users] [PATCH] PPC440EPx/sequoia TLB question...
In-Reply-To: <200804231442.29687.sr@denx.de>
References: <480EA8E1.4060207@verizon.net> <200804231442.29687.sr@denx.de>
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Stefan Roese wrote:
> On Wednesday 23 April 2008, Dave Littell wrote:
>>> From ?/board/amcc/sequoia/init.S:
>> 
>> /* TLB-entry for Internal Registers & OCM */ tlbentry( 0xe0000000, 
>> SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
>> 
>> Why is this memory region not marked Guarded?  It would seem to 
>> meet the definition of ?non-well-behaved?.
> 
> Why do you think this is the case?
> 
>> Also the TLB entry for SDRAM marks it Guarded, but that?s one area 
>> I would think wouldn't need to be Guarded.
> 
> This could be a mistake. Should work without G bis set too. Please 
> give it a try and send a patch to fix it, if it works fine.
> 

Here goes:

Patch for AMCC Sequoia to remove the TLB Guarded attribute for SDRAM,
and add the Guarded attribute for Internal Registers & OCM.

(Sorry if the wrap monster mangles this - I can't seem to convince
Thunderbird to play nice.)

diff -purN u-boot-1.3.2_base/board/amcc/sequoia/init.S
u-boot-1.3.2/board/amcc/sequoia/init.S
--- u-boot-1.3.2_base/board/amcc/sequoia/init.S 2008-03-09
10:20:02.000000000 -0500
+++ u-boot-1.3.2/board/amcc/sequoia/init.S      2008-04-24
21:24:17.542281994 -0500
@@ -45,9 +45,9 @@ tlbtab:

        /* TLB-entry for DDR SDRAM (Up to 2GB) */
 #ifdef CONFIG_4xx_DCACHE
-       tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0,
AC_R|AC_W|AC_X|SA_G)
+       tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0,
AC_R|AC_W|AC_X)
 #else
-       tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0,
AC_R|AC_W|AC_X|SA_I )
 #endif

        /* TLB-entry for EBC */
@@ -77,7 +77,7 @@ tlbtab:
        tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1,
AC_R|AC_W|AC_X|SA_G|SA_I )

        /* TLB-entry for Internal Registers & OCM */
-       tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
+       tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )

        /*TLB-entry PCI registers*/
        tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,
AC_R|AC_W|AC_X|SA_G|SA_I )