From: Dave Littell <littelld@verizon.net>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] PPC440EPx/sequoia TLB question...
Date: Fri, 25 Apr 2008 20:54:51 -0500 [thread overview]
Message-ID: <48128B6B.8090909@verizon.net> (raw)
In-Reply-To: <200804231442.29687.sr@denx.de>
Stefan Roese wrote:
> On Wednesday 23 April 2008, Dave Littell wrote:
>> >From ?/board/amcc/sequoia/init.S:
>>
>> /* TLB-entry for Internal Registers & OCM */
>> tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
>>
>> Why is this memory region not marked Guarded? It would seem to meet the
>> definition of ?non-well-behaved?.
>
> Why do you think this is the case?
>
>> Also the TLB entry for SDRAM marks it Guarded, but that?s one area I
>> would think wouldn't need to be Guarded.
>
> This could be a mistake. Should work without G bis set too. Please give it a
> try and send a patch to fix it, if it works fine.
>
Here goes (again):
Patch for AMCC Sequoia to remove the TLB Guarded attribute for SDRAM,
and add the Guarded attribute for Internal Registers & OCM.
diff -purN u-boot-1.3.2_base/board/amcc/sequoia/init.S u-boot-1.3.2/board/amcc/sequoia/init.S
--- u-boot-1.3.2_base/board/amcc/sequoia/init.S 2008-03-09 10:20:02.000000000 -0500
+++ u-boot-1.3.2/board/amcc/sequoia/init.S 2008-04-24 21:24:17.542281994 -0500
@@ -45,9 +45,9 @@ tlbtab:
/* TLB-entry for DDR SDRAM (Up to 2GB) */
#ifdef CONFIG_4xx_DCACHE
- tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X)
#else
- tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_I )
#endif
/* TLB-entry for EBC */
@@ -77,7 +77,7 @@ tlbtab:
tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for Internal Registers & OCM */
- tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
/*TLB-entry PCI registers*/
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
I sure hope this is better (from a line-wrapping perspective).
Dave
next prev parent reply other threads:[~2008-04-26 1:54 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-04-23 3:11 [U-Boot-Users] PPC440EPx/sequoia TLB question Dave Littell
2008-04-23 12:42 ` Stefan Roese
2008-04-24 2:27 ` Dave Littell
2008-04-24 5:28 ` Stefan Roese
2008-04-24 11:58 ` Josh Boyer
2008-04-24 13:07 ` Stefan Roese
2008-04-25 2:34 ` [U-Boot-Users] [PATCH] " Dave Littell
2008-04-25 5:31 ` Stefan Roese
2008-04-26 1:54 ` Dave Littell [this message]
2008-04-29 5:54 ` [U-Boot-Users] " Stefan Roese
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