From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shinya Kuribayashi Date: Fri, 02 May 2008 12:35:50 +0900 Subject: [U-Boot-Users] [PATCH][MIPS] cpu/mips/cache.S: Add dcache_enable In-Reply-To: <481A8B97.5030209@ruby.dti.ne.jp> References: <481A8B97.5030209@ruby.dti.ne.jp> Message-ID: <481A8C16.7090502@ruby.dti.ne.jp> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Recent bootelf command fixes (017e9b7925f74878d0e9475388cca9bda5ef9482, "allow ports to override bootelf behavior") requires ports to have this function. Signed-off-by: Shinya Kuribayashi --- cpu/mips/cache.S | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index f593968..428d251 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -285,6 +285,22 @@ LEAF(dcache_disable) jr ra END(dcache_disable) +/******************************************************************************* +* +* dcache_enable - enable cache +* +* RETURNS: N/A +* +*/ +LEAF(dcache_enable) + mfc0 t0, CP0_CONFIG + ori t0, CONF_CM_CMASK + xori t0, CONF_CM_CMASK + ori t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG + jr ra + END(dcache_enable) + #ifdef CFG_INIT_RAM_LOCK_MIPS /******************************************************************************* *