[U-Boot-Users] [PATCH 2/2] add MPC8343 based board mvBlueLYNX-M7

["André Schwarz" <Andre.Schwarz@matrix-vision.de>]

Thanks,

unfortunately I'm out of office right now.

I'll re-send the 23rd try after my vacation at end of may.
If the merge window will be closed at that date it's obviously bad luck.


Cheers,
Andr?


Jean-Christophe PLAGNIOL-VILLARD wrote:
>> + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz at matrix-vision.de
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + *
>> + */
>> +
>> +#include <common.h>
>> +#include <ACEX1K.h>
>> +#include <command.h>
>> +#include "fpga.h"
>> +#include "mvblm7.h"
>> +
>> +#ifdef CONFIG_FPGA
>>     
> Please move it to the Makefile
>   
>> +
>> +#ifdef FPGA_DEBUG
>> +#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
>> +#else
>> +#define fpga_debug(fmt, args...)
>> +#endif
>> +
>> +Altera_CYC2_Passive_Serial_fns altera_fns = {
>> +	fpga_null_fn,
>> +	fpga_config_fn,
>> +	fpga_status_fn,
>> +	fpga_done_fn,
>> +	fpga_wr_fn,
>> +	fpga_null_fn,
>> +	fpga_null_fn,
>> +	0
>> +};
>> +
>> +Altera_desc cyclone2 = {
>> +	Altera_CYC2,
>> +	passive_serial,
>> +	Altera_EP2C20_SIZE,
>> +	(void *) &altera_fns,
>> +	NULL,
>> +	0
>> +};
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int mvblm7_init_fpga(void)
>> +{
>> +	fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
>> +		gd->reloc_off);
>> +	fpga_init(gd->reloc_off);
>> +	fpga_add(fpga_altera, &cyclone2);
>> +	fpga_config_fn(0, 1, 0);
>> +	udelay(60);
>> +
>> +	return 1;
>> +}
>> +
>> +int fpga_null_fn(int cookie)
>> +{
>> +	return 0;
>> +}
>> +
>> +int fpga_config_fn(int assert, int flush, int cookie)
>> +{
>> +	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
>> +	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
>>     
> please remove empty line
>   
>> +
>> +	u32 dvo = gpio->dat;
>>     
> please add empty line
>   
>> +	fpga_debug("SET config : %s\n", assert ? "low" : "high");
>> +	if (assert)
>> +		dvo |= FPGA_CONFIG;
>> +	else
>> +		dvo &= ~FPGA_CONFIG;
>> +
>> +	if (flush)
>> +		gpio->dat = dvo;
>> +
>> +	return assert;
>> +}
>> +
>> +int fpga_done_fn(int cookie)
>> +{
>> +	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
>> +	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
>> +	int result = 0;
>> +
>> +	udelay(10);
>> +	fpga_debug("CONF_DONE check ... ");
>> +	if (gpio->dat & FPGA_CONF_DONE)  {
>> +		fpga_debug("high\n");
>> +		result = 1;
>> +	} else
>> +		fpga_debug("low\n");
>> +
>> +	return result;
>> +}
>> +
>> +int fpga_status_fn(int cookie)
>> +{
>> +	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
>> +	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
>> +	int result = 0;
>> +
>> +	fpga_debug("STATUS check ... ");
>> +	if (gpio->dat & FPGA_STATUS)  {
>> +		fpga_debug("high\n");
>> +		result = 1;
>> +	} else
>> +		fpga_debug("low\n");
>> +
>> +	return result;
>> +}
>> +
>> +int fpga_clk_fn(int assert_clk, int flush, int cookie)
>> +{
>> +	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
>> +	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
>>     
> please remove empty line
>   
>> +
>> +	u32 dvo = gpio->dat;
>>     
> please add empty line
>   
>> +	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
>> +	if (assert_clk)
>> +		dvo |= FPGA_CCLK;
>> +	else
>> +		dvo &= ~FPGA_CCLK;
>> +
>> +	if (flush)
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#include <common.h>
>> +#include <ioports.h>
>> +#include <mpc83xx.h>
>> +#include <asm/mpc8349_pci.h>
>> +#include <pci.h>
>> +#include <asm/mmu.h>
>> +#if defined(CONFIG_OF_LIBFDT)
>> +#include <libfdt.h>
>> +#endif
>> +
>> +#include "mvblm7.h"
>> +
>> +int fixed_sdram(void)
>> +{
>> +	volatile immap_t *im = (immap_t *)CFG_IMMR;
>> +	u32 msize = 0;
>> +	u32 ddr_size;
>> +	u32 ddr_size_log2;
>> +
>> +	msize = CFG_DDR_SIZE;
>> +	for (ddr_size = msize << 20, ddr_size_log2 = 0;
>> +		(ddr_size > 1);
>> +		ddr_size = ddr_size>>1, ddr_size_log2++) {
>>     
>                                   ^  ^
> please add space
>   
>> +		if (ddr_size & 1)
>> +			return -1;
>> +	}
>> +	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
>> +	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
>> +		LAWAR_SIZE);
>> +		*e++ = strlen(ptr);
>> +		while (*ptr)
>> +			*e++ = *ptr++;
>> +	}
>> +	/* DHCP_CLIENT_IDENTIFIER = 61 */
>> +	ptr = getenv("dhcp_client_id");
>> +	if (ptr) {
>> +		*e++ = 61;
>> +		*e++ = strlen(ptr);
>> +		while (*ptr)
>> +			*e++ = *ptr++;
>> +	}
>> +
>> +	return e;
>> +}
>> +
>> +		data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
>> +
>> +	return fpga_load(0, fpga_data, data_size);
>> +}
>> +
>> +static struct pci_region pci_regions[] = {
>> +	{
>> +		bus_start: CFG_PCI1_MEM_BASE,
>> +		phys_start: CFG_PCI1_MEM_PHYS,
>> +		size: CFG_PCI1_MEM_SIZE,
>> +		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
>> +	},
>> +	{
>> +		bus_start: CFG_PCI1_MMIO_BASE,
>> +		phys_start: CFG_PCI1_MMIO_PHYS,
>> +		size: CFG_PCI1_MMIO_SIZE,
>> +		flags: PCI_REGION_MEM
>> +	},
>> +	{
>> +		bus_start: CFG_PCI1_IO_BASE,
>> +		phys_start: CFG_PCI1_IO_PHYS,
>> +		size: CFG_PCI1_IO_SIZE,
>> +		flags: PCI_REGION_IO
>> +	}
>> +};
>> +
>> +void pci_init_board(void)
>> +{
>> +	char *s;
>> +	int i, warmboot, load_fpga=0;
>>     
> Please split it
>   
>> +	volatile immap_t *immr;
>>     
> Best Regards,
> J.
>   



MATRIX VISION GmbH, Talstra?e 16, DE-71570 Oppenweiler  - Registergericht: Amtsgericht Stuttgart, HRB 271090
Gesch?ftsf?hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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