[U-Boot] [PATCH v3] Freescale NFC NAND driver

[Fabio Estevam <fabioestevam@yahoo.com>]

--- On Tue, 11/4/08, John Rigby <jrigby@freescale.com> wrote:

> From: John Rigby <jrigby@freescale.com>
> Subject: [U-Boot] [PATCH v3] Freescale NFC NAND driver
> To: u-boot at lists.denx.de, "Scott Wood" <scottwood@freescale.com>
> Cc: "John Rigby" <jrigby@freescale.com>
> Date: Tuesday, November 4, 2008, 11:02 PM
> v3: Fixed problem with CFG vs CONFIG_SYS in
> board/ads5121/ads5121.c
> 
> v2: Reworked MPC5121 NAND driver.
> Attempted to address all the problems listed by Scott Wood.
> Driver is now board independent.  Will still need more
> work to be SOC independent.
> 
> Driver for the NAND controller on MPC5121.
> 
> This driver has been tested on ADS5121 rev4 / MPC5121e rev2
> only
> which has the following configuration:
>     2K page size
>     8 bit device width
> 
> This should work on other boards with MPC5121 rev2 silicon
> with
> little or no change to the driver.
> 
> Various vintages of this controller exist on some iMX
> parts.
> Getting it to work on an iMX with the same controller
> version
> should be fairly easy.  More work if it is an iMX with a
> different
> version on the controller.
> 
> This controller treats 2K pages as 4 512 byte pages
> and the hw ecc is over the combined 512 byte main
> area and the first 7 bytes of the spare area.
> 
> The hw ecc is stored in the last 9 bytes of the
> spare area.
> 
> This all means the the spare area can not be written
> separately from the main.  This means unmodified JFFS2
> will not work.
...
> +#define NFC_BUF_ADDR			(NFC_REG_BASE + 0x1E04)
> +#define NFC_FLASH_ADDR			(NFC_REG_BASE + 0x1E06)
> +#define NFC_FLASH_CMD			(NFC_REG_BASE + 0x1E08)
> +#define NFC_CONFIG			(NFC_REG_BASE + 0x1E0A)
> +#define NFC_ECC_STATUS1			(NFC_REG_BASE + 0x1E0C)
> +#define NFC_ECC_STATUS2			(NFC_REG_BASE + 0x1E0E)
> +#define NFC_SPAS			(NFC_REG_BASE + 0x1E10)
> +#define NFC_WRPROT			(NFC_REG_BASE + 0x1E12)
> +#define NFC_NF_WRPRST			(NFC_REG_BASE + 0x1E18)
> +#define NFC_CONFIG1			(NFC_REG_BASE + 0x1E1A)
> +#define NFC_CONFIG2			(NFC_REG_BASE + 0x1E1C)
> +#define NFC_UNLOCKSTART_BLKADDR0	(NFC_REG_BASE + 0x1E20)
> +#define NFC_UNLOCKEND_BLKADDR0		(NFC_REG_BASE + 0x1E22)
> +#define NFC_UNLOCKSTART_BLKADDR1	(NFC_REG_BASE + 0x1E24)
> +#define NFC_UNLOCKEND_BLKADDR1		(NFC_REG_BASE + 0x1E26)
> +#define NFC_UNLOCKSTART_BLKADDR2	(NFC_REG_BASE + 0x1E28)
> +#define NFC_UNLOCKEND_BLKADDR2		(NFC_REG_BASE + 0x1E2A)
> +#define NFC_UNLOCKSTART_BLKADDR3	(NFC_REG_BASE + 0x1E2C)
> +#define NFC_UNLOCKEND_BLKADDR3		(NFC_REG_BASE + 0x1E2E)

On MX31 and also according to the current MPC5121 Reference Manual on the web the offsets of the registers above seem to have an extra offset of 0x1000.

MX31 and MPC5121 manuals state the following offsets: 

#define NFC_BUF_ADDR			(NFC_REG_BASE + 0xE04)
#define NFC_FLASH_ADDR			(NFC_REG_BASE + 0xE06)
...

Is there a newer MPC5121 manual that changed the NAND registers offsets?

Regards,

Fabio Estevam