[U-Boot-Users] PXA270 board startup: printf does not work

[JP <jp-linux@att.net>]

JP wrote:
> Jerry Van Baren wrote:
>> Your talk about having a corrupted local char buffer confused me.  If it 
>> were not for that detail, I would have been positive that you have a 
>> problem with handling your UART's Tx busy flag.
>>
>> Your symptoms are typical of not waiting for the UART to complete 
>> transmitting a character before stuffing the next one in once the UART 
>> FIFO is full.  The result is that, if the string has fewer than /n/ 
>> characters (/n/ being the depth of the UART's Tx FIFO, possibly a few 
>> more), it works OK.  If the string is longer than /n/, it gets corrupted 
>> by your s/w overwriting characters in the UART.  Depending on the UART 
>> implementation, this could include the one currently being shifted out, 
>> resulting in garbage characters.
> 
> A very long (already initialized) string prints correctly with puts, so 
> I suspect the FIFO implementation is OK.   We're using the FFUART.
>> What in your processor is 32 bytes long?  UART FIFO?  Cache line? Hmmmm, 
>> could you be having cache consistency problems?  Cache problems would be 
>> consistent with garbage in memory.
>>
>> BIG WARNING NOTE: Writing memory with a debugger is typically very 
>> benign (s.l.o.w.) compared to writing with the processor.  Writing 
>> single memory locations with the processor is typically benign compared 
>> to a cache line burst read/write.  SDRAM (including DDR/DDR2) 
>> initialization problems typically do *not* show up until cache is 
>> enabled because it is the burst read/write that violates the "S" in 
>> SDRAM (you end up out of sync "synchronous").
>> FAQ: <http://www.denx.de/wiki/DULG/SDRAM>
> 
> Thanks for those ideas.  We haven't found many examples to compare our 
> configuration to, but we did have trouble initially getting the SDRAM 
> startup sequence working.  Your description and the wiki entry describe 
> what could be happening.
> 
> JP
This turned out to be a hardware problem: the DQM 0/1 lines that select 
8 bits of a 32 bit location were reversed.