[U-Boot-Users] [PATCH] TQM85xx: Change memory map to support Flash memory > 128 MiB

Wolfgang Grandegger
2008-05-28T18:12:29Z

Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash
memory. The current memory map only supports up to 128 MiB Flash.
This patch adds the configuration option CONFIG_TQM_BIGFLASH. If
set, up to 1 GiB flash is supported. To achieve this, the memory
map has to be adjusted in great parts (for example the CCSRBAR is
moved from 0xE0000000 to 0xA0000000).

If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new
memory map also has to be considered in the kernel (changed
CCSRBAR address, changed PCI IO base address, ...). Please use
an appropriate Flat Device Tree blob (tqm8548.dtb).

Signed-off-by: Martin Krause <martin.krause@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
---
board/tqc/tqm85xx/law.c | 29 ++++++++++++--
board/tqc/tqm85xx/tlb.c | 97 +++++++++++++++++++++++++++++++++++++++++++++
include/configs/TQM85xx.h | 52 +++++++++++++++++++++---
3 files changed, 167 insertions(+), 11 deletions(-)

diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
index 914ce68..b4e663b 100644
--- a/board/tqc/tqm85xx/law.c
+++ b/board/tqc/tqm85xx/law.c
@@ -30,6 +30,8 @@
/*
* LAW(Local Access Window) configuration:
*
+ * Standard mapping:
+ *
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M
@@ -37,22 +39,41 @@
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M
* 0xef00_0000 0xefff_ffff PCI express IO 16M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M
+ *
+ * Big FLASH mapping:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xa000_ffff CCSR 1M
+ * 0xa200_0000 0xa2ff_ffff PCI1 IO 16M
+ * 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M
+ * 0xaf00_0000 0xafff_ffff PCI express IO 16M
+ * 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M
+ * 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/

+#ifdef CONFIG_TQM_BIGFLASH
+#define LAW_3_SIZE LAW_SIZE_1G
+#define LAW_5_SIZE LAW_SIZE_256M
+#else
+#define LAW_3_SIZE LAW_SIZE_128M
+#define LAW_5_SIZE LAW_SIZE_512M
+#endif
+
struct law_entry law_table[] = {
SET_LAW_ENTRY (1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+ SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#ifdef CONFIG_PCIE1
- SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
#else /* !CONFIG_PCIE1 */
- SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
#endif /* CONFIG_PCIE1 */
#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 7f4efc1..380448a 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -44,6 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),

+#ifndef CONFIG_TQM_BIGFLASH
/*
* TLB 0, 1: 128M Non-cacheable, guarded
* 0xf8000000 128M FLASH
@@ -146,6 +147,102 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 9, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */

+#else /* CONFIG_TQM_BIGFLASH */
+
+ /*
+ * TLB 0,1,2,3: 1G Non-cacheable, guarded
+ * 0xc0000000 1G FLASH
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000,
+ CFG_FLASH_BASE + 0x10000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000,
+ CFG_FLASH_BASE + 0x20000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000,
+ CFG_FLASH_BASE + 0x30000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 5: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
+ CFG_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+#ifdef CONFIG_PCIE1
+ /*
+ * TLB 6: 256M Non-cacheable, guarded
+ * 0xc0000000 256M PCI express MEM First half
+ */
+ SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+#else /* !CONFIG_PCIE */
+ /*
+ * TLB 6: 256M Non-cacheable, guarded
+ * 0xb0000000 256M Rapid IO MEM First half
+ */
+ SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+#endif /* CONFIG_PCIE */
+
+ /*
+ * TLB 7: 64M Non-cacheable, guarded
+ * 0xa0000000 1M CCSRBAR
+ * 0xa2000000 16M PCI1 IO
+ * 0xa3000000 16M CAN and NAND Flash
+ */
+ SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 7, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 8+9: 512M DDR, cache disabled (needed for memory test)
+ * 0x00000000 512M DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ * Make sure the TLB count at the top of this table is correct.
+ * Likely it needs to be increased by two for these entries.
+ */
+ SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 8, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
+ CFG_DDR_SDRAM_BASE + 0x10000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 9, BOOKE_PAGESZ_256M, 1),
+
+#ifdef CONFIG_PCIE1
+ /*
+ * TLB 10: 16M Non-cacheable, guarded
+ * 0xaf000000 16M PCI express IO
+ */
+ SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif /* CONFIG_PCIE */
+
+#endif /* CONFIG_TQM_BIGFLASH */
};

int num_tlb_entries = ARRAY_SIZE (tlb_table);
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 1e58066..eb044ab 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -54,6 +54,16 @@

#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */

+ /*
+ * Configuration for big NOR Flashes
+ *
+ * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
+ * Please be aware, that this changes the whole memory map (new CCSRBAR
+ * address, etc). You have to use an adapted Linux kernel or FDT blob
+ * if this option is set.
+ */
+#undef CONFIG_TQM_BIGFLASH
+
/*
* NAND flash support (disabled by default)
*
@@ -109,7 +119,11 @@
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_CCSRBAR 0xA0000000 /* relocated CCSRBAR */
+#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
+#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */

@@ -146,8 +160,13 @@
/*
* Flash on the Local Bus
*/
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_FLASH0 0xE0000000
+#define CFG_FLASH1 0xC0000000
+#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_FLASH0 0xFC000000
#define CFG_FLASH1 0xF8000000
+#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }

#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
@@ -172,10 +191,17 @@
* 25 0x.....020
*
*/
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_BR0_PRELIM 0xE0001801 /* port size 32bit */
+#define CFG_OR0_PRELIM 0xE0000040 /* 512MB Flash */
+#define CFG_BR1_PRELIM 0xC0001801 /* port size 32bit */
+#define CFG_OR1_PRELIM 0xE0000040 /* 512MB Flash */
+#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
+#endif /* CONFIG_TQM_BIGFLASH */

#define CFG_FLASH_CFI /* flash is CFI compat. */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
@@ -206,7 +232,8 @@

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_ADDR (CFG_CCSRBAR \
+ + 0x04010000) /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */

#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
@@ -261,7 +288,8 @@
#define CONFIG_OF_STDOUT_VIA_ALIAS 1

/* CAN */
-#define CFG_CAN_BASE 0xE3000000 /* CAN base address */
+#define CFG_CAN_BASE (CFG_CCSRBAR \
+ + 0x03000000) /* CAN base address */
#ifdef CONFIG_CAN_DRIVER
#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
#define CFG_OR2_CAN (CFG_CAN_OR_AM | ORxU_BI)
@@ -304,9 +332,14 @@

#ifndef CONFIG_PCIE1
/* RapidIO MMU */
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_RIO_MEM_BASE 0xb0000000 /* base address */
+#define CFG_RIO_MEM_SIZE 0x10000000 /* 256M */
+#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
-#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif /* CONFIG_TQM_BIGFLASH */
+#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#endif /* CONFIG_PCIE1 */

/* NAND FLASH */
@@ -322,7 +355,7 @@
#define CFG_NAND_CS_DIST 0x200

#define CFG_NAND_SIZE 0x8000
-#define CFG_NAND0_BASE 0xE3010000
+#define CFG_NAND0_BASE (CFG_CCSRBAR + 0x03010000)
#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
@@ -362,7 +395,7 @@
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_BASE (CFG_CCSRBAR + 0x02000000)
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */

@@ -376,13 +409,18 @@
* General PCI express
* Addresses are mapped 1-1.
*/
+#ifdef CONFIG_TQM_BIGFLASH
+#define CFG_PCIE1_MEM_BASE 0xb0000000
+#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0xaf000000
+#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_PCIE1_MEM_BASE 0xc0000000
-#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCIE1_IO_BASE 0xef000000
+#endif /* CONFIG_TQM_BIGFLASH */
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
#define CFG_PCIE1_IO_PHYS CFG_PCIE1_IO_BASE
#define CFG_PCIE1_IO_SIZE 0x1000000 /* 16M */
-
#endif /* CONFIG_PCIE1 */

#if defined(CONFIG_PCI)
--
1.5.2.2