[U-Boot-Users] [PATCH] MPC85xx: Beatify boot output of L2 cache configuration

Wolfgang Grandegger
2008-05-28T18:12:18Z

The boot output is now aligned poperly with other boot output
lines, e.g.:

FLASH: 128 MB
L2: 512 KB enabled

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
---
cpu/mpc85xx/cpu.c | 2 +-
cpu/mpc85xx/cpu_init.c | 18 ++++++++++--------
2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 9873383..274b486 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -159,7 +159,7 @@ int checkcpu (void)
}

#ifdef CONFIG_CPM2
- printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+ printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
#endif

puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index e3240b5..0fb36c4 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -265,6 +265,8 @@ int cpu_init_r(void)
#endif
#endif

+ puts ("L2: ");
+
#if defined(CONFIG_L2_CACHE)
volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
@@ -281,17 +283,17 @@ int cpu_init_r(void)
case 0x20000000:
if (ver == SVR_8548 || ver == SVR_8548_E ||
ver == SVR_8544 || ver == SVR_8568_E) {
- printf ("L2 cache 512KB:");
+ puts ("512 KB ");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;
} else {
- printf ("L2 cache 256KB:");
+ puts("256 KB ");
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
cache_ctl = 0xc8000000;
}
break;
case 0x10000000:
- printf ("L2 cache 256KB:");
+ puts("256 KB ");
if (ver == SVR_8544 || ver == SVR_8544_E) {
cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
}
@@ -299,18 +301,18 @@ int cpu_init_r(void)
case 0x30000000:
case 0x00000000:
default:
- printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
+ printf(" unknown size (0x%08x)\n", cache_ctl);
return -1;
}

if (l2cache->l2ctl & 0x80000000) {
- printf(" already enabled.");
+ puts("already enabled");
l2srbar = l2cache->l2srbar0;
#ifdef CFG_INIT_L2_ADDR
if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
l2srbar = CFG_INIT_L2_ADDR;
l2cache->l2srbar0 = l2srbar;
- printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR);
+ printf("moving to 0x%08x", CFG_INIT_L2_ADDR);
}
#endif /* CFG_INIT_L2_ADDR */
puts("\n");
@@ -318,10 +320,10 @@ int cpu_init_r(void)
asm("msync;isync");
l2cache->l2ctl = cache_ctl; /* invalidate & enable */
asm("msync;isync");
- printf(" enabled\n");
+ puts("enabled\n");
}
#else
- printf("L2 cache: disabled\n");
+ puts("disabled\n");
#endif
#ifdef CONFIG_QE
uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
--
1.5.2.2