From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Wed, 04 Jun 2008 08:36:58 +0200 Subject: [U-Boot-Users] [patch 0/6] DM9000: Several fixes/cleanups for the DM9000A controller In-Reply-To: <3efb10970806031126p7bc5b96aob62141d5073f5c89@mail.gmail.com> References: <20080603132620.482930912@bohmer.net> <48455D9F.2080501@gmail.com> <484574A6.7070107@denx.de> <3efb10970806031126p7bc5b96aob62141d5073f5c89@mail.gmail.com> Message-ID: <4846380A.9080701@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Remy Bohmer wrote: > In a few minutes I will post a patch which I hope it will solve this. > Can you please try it on your board? I have tried, the old error is gone, but the board hangs probably after getting the first packets: $ tftp 0xa0010000 u-boot.bin dm9000 i/o: 0x8000000, id: 0x90000a46 DM9000: running in 32 bit mode MAC: 00:50:c2:3b:8f:0a operating at 100M full duplex mode TFTP from server 192.168.2.14; our IP address is 192.168.2.77 Filename 'u-boot.bin'. Load address: 0xa0010000 Loading:* Enabling the debug I get this output (so the first packet was received): $ tftp 0xa0010000 u-boot.bin eth_halt phy_write(reg:0x0, value:0x8000) eth_init() resetting DM9000 resetting the DM9000, 1st reset resetting the DM9000, 2nd reset dm9000 i/o: 0x8000000, id: 0x90000a46 DM9000: running in 32 bit mode phy_read(0x3): 0x0 MAC: 00:50:c2:3b:8f:0a 00:50:c2:3b:8f:0a: phy_read(0x1): 0x7809 phy_read(0x1): 0x7809 phy_read(0x1): 0x7809 phy_read(0x1): 0x7809 phy_read(0x1): 0x7809 phy_read(0x1): 0x7809 [snip] phy_read(0x1): 0x780d phy_read(0x1): 0x780d phy_read(0x1): 0x780d phy_read(0x1): 0x780d [snip] phy_read(0x1): 0x780d phy_read(0x1): 0x782d phy_read(0x11): 0x8018 operating at 100M full duplex mode TFTP from server 192.168.2.14; our IP address is 192.168.2.77 Filename 'u-boot.bin'. Load address: 0xa0010000 Loading: eth_send: length: 42 eth_send: 00: ff ff ff ff ff ff 00 50 eth_send: 08: c2 3b 8f 0a 08 06 00 01 eth_send: 10: 08 00 06 04 00 01 00 50 eth_send: 18: c2 3b 8f 0a c0 a8 02 4d eth_send: 20: 00 00 00 00 00 00 c0 a8 eth_send: 28: 02 0e transmit done receiving packet rx status: 0x0001 rx len: 64 eth_rx: length: 64 eth_rx: 00: 01 00 40 00 00 50 c2 3b eth_rx: 08: 8f 0a 00 0b 2b 12 e3 3c eth_rx: 10: 08 06 00 01 08 00 06 04 eth_rx: 18: 00 02 00 0b 2b 12 e3 3c eth_rx: 20: c0 a8 02 0e 00 50 c2 3b eth_rx: 28: 8f 0a c0 a8 02 4d 00 00 eth_rx: 30: 00 00 00 00 00 00 00 00 eth_rx: 38: 00 00 00 00 00 00 00 00 passing packet to upper layer receiving packet rx status: 0x806d rx len: 24529 ^^^ ^^^^^--> wrong Stefano -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================