[U-Boot-Users] CPU (405ep) clock upgrade..

[U-Boot-Users] CPU (405ep) clock upgrade..

["Yi-Neng Lin (林義能)"]

Hi there,
We've got a board powered by 405ep running at 266MHz. Now we want to
upgrade the clock rate to 333MHz (model: 3LB333C), can anyone give us
some pointers doing this? I've tried to search the mailing list but
found nothing quite related. Also there seems to exist very limited
ports, if not none, of this model to which I may reference.
Below are questions that are more specific:
1. For CPU clock rate configuration, exactly what parameters should I
modify? The suspected ones are FWDV (Feedback Divide) and FBDVB (Forward
Divide B) which according to the processor user manual determines the
PLLOUT A.
2. SDRAM clocking. I guess the clocking should be adapted to something
like 111MHz (given the 333MHz CPU clock); however, the manual shows
there there seems to be only two options, namely 100MHz and 133MHz.
3. Clocking of others such as PCI (on-chip PLB clock, sync/async PCI
clock) and serial port. Are they supposed to be modified accordingly?
4. Any other parameters?

Thank you very much for your guidance.

Yi-Neng

[U-Boot-Users] CPU (405ep) clock upgrade..

[Stefan Roese]

On Monday 30 June 2008, Yi-Neng Lin (???) wrote:
> We've got a board powered by 405ep running at 266MHz. Now we want to
> upgrade the clock rate to 333MHz (model: 3LB333C), can anyone give us
> some pointers doing this? I've tried to search the mailing list but
> found nothing quite related. Also there seems to exist very limited
> ports, if not none, of this model to which I may reference.

There are quite a big number of 405EP board ports. I suspect that some of them 
are capable of running with 333MHz. The frequencies are usually configured 
via the I2C bootstrap EEPROM.

> Below are questions that are more specific:
> 1. For CPU clock rate configuration, exactly what parameters should I
> modify? The suspected ones are FWDV (Feedback Divide) and FBDVB (Forward
> Divide B) which according to the processor user manual determines the
> PLLOUT A.

Sure. You need to configure the PLL parameters accordingly. The 405EP users 
manual should give you all the infos you need.

> 2. SDRAM clocking. I guess the clocking should be adapted to something
> like 111MHz (given the 333MHz CPU clock); however, the manual shows
> there there seems to be only two options, namely 100MHz and 133MHz.

Which SDRAM init code are you using? I suggest that you take a look at 
cpu/ppc4xx/sdram.c and use this file on your system too. You "only" need to 
configure some SDRAM chip parameters (for example include/configs/zeus.h):

/*
 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 */
#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
#define CONFIG_SDRAM_BANK1      1       /* init onboard SDRAM bank 1 */

/* SDRAM timings used in datasheet */
#define CFG_SDRAM_CL            3       /* CAS latency */
#define CFG_SDRAM_tRP           20      /* PRECHARGE command period */
#define CFG_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
#define CFG_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
#define CFG_SDRAM_tRFC          66      /* Auto refresh period */

> 3. Clocking of others such as PCI (on-chip PLB clock, sync/async PCI
> clock) and serial port. Are they supposed to be modified accordingly?
> 4. Any other parameters?

You need to make sure that all frequencies are in range.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
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[U-Boot-Users] CPU (405ep) clock upgrade..

["Yi-Neng Lin (林義能)"]

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[U-Boot-Users] CPU (405ep) clock upgrade..

[Stefan Roese]

On Monday 30 June 2008, Yi-Neng Lin (???) wrote:
>  Thanks a lot for your reply, Stefan. However, in my understanding, only
> memory-related info is stored in the EEPROM in the memory module, isn't it?

Yes, the I2C EEPROM on the DIMM has of course only memory module related 
stuff. But I was referring to the 405EX bootstrap EEPROM (see chapter 9.2 IIC 
serial EPROM controller (IEC) Operation in the 405EP users manual).

> The CPU and bus related info is hard-coded in the code. This is what I saw
> from my code. Not very sure of it, though.

Yes, could be that you are using the fixed, compiled-in speed configuration.

>  ? I think it's the spd_sdram() [cpu/ppc4xx] who does the job, which could
> have been an outdated method.

It was renamed and is now called 40x_spd_sdram.c. For board with DIMM modules 
on 405EP this is the way to go.

> The timing info is read from the SPD (Serial 
> Presence Detect) EEPROM on the SDRAM module. My question is, with the
> upgraded CPU clock (333MHz), ordinary SDRAMs (PC100 and PC133) may not be
> able to support it, which means I may have to use PC2700 (333MHz; too
> fast?) or PC66(66MHz; too slow?). Am I correct? Any other comment or
> solution for this?

I'm pretty sure that you still can use the "ordinary" DIMMs. The driver should 
configure the needed parameters like CAS latency accordingly.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot-Users] CPU (405ep) clock upgrade..

[Yi-Neng Lin]

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[U-Boot-Users] CPU (405ep) clock upgrade..

[Stefan Roese]

On Wednesday 02 July 2008, Yi-Neng Lin wrote:
>  This arises another question. Assume that both configurations (CPU and
> SDRAM) are obtained from the EEPROM, how can C program/function be adopted
> to use these parameters before CPU/memory is initiated? C
> programs/functions need memory space to setup the stacks, which means
> CPU/memory initialization should be done (via assembly) before any C
> programs/functions can be used.

All this is already taken care of. U-Boot uses a small area for initial RAM. 
Sometimes in D-cache, sometimes in onboard SRAM (SoC). IIRC, the 405EP has 
OCM, so this could be used here. You just need to configure this correctly in 
your board config file. Again I suggest you take a look at the zeus board as 
an example.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================