[U-Boot-Users] [PATCH 00/10] [ARM] TQMA31: new board

[U-Boot-Users] [PATCH 00/10] [ARM] TQMA31: new board

[Jens Gehrlein]

Hi,

the following patches introduce the i.MX31 (ARM1136) based board TQMA31.
Used toolchain was ELDK 4.1.

The first three patches fix some bugs in mxc/mx31 common parts. I compiled
the im31_phycore, the imx31_litekit and the mx31ads U-Boots for this.
But I don't have boards to test them.

Patch 04/10 cannot successfully be compiled without having Patch 03/10 applied.

Patch 03/10 has been on the mailing list in a similar form, but it seems that
nobody picked it up. So I want give it a chance with my patch series.

Who will pick up this patch series (if there are no complaints)? Peter?

Kind regards,
Jens

---

Jens Gehrlein (10):
      [ARM] TQMA31: new kernel param. to pass the eth MAC addr to the Linux eth chip driver
      [ARM] TQMA31: add FPGA configuration flash
      [ARM] TQMA31: adjust pad property of IPU pin FPSHIFT for the display
      [ARM] TQMA31: adjust voltage regulators in PMIC MC13738
      [ARM] TQMA31: add support for SPI and SPI device MC13783-RTC
      [ARM] TQMA31: add support for I2C, I2C temperature sensor and I2C-EEPROM
      [ARM] TQMA31: add new board with i.MX31 processor
      [ARM] MX31: fix typos in defines for UART and SPI IO multiplexer pins
      [ARM] MX31: fix bit masks in function mx31_decode_pll()
      [ARM] MXC: insert bus busy check in i2c_probe


 MAINTAINERS                           |    4 
 MAKEALL                               |    1 
 Makefile                              |    3 
 board/imx31_litekit/imx31_litekit.c   |    2 
 board/imx31_phycore/imx31_phycore.c   |    4 
 board/mx31ads/mx31ads.c               |    2 
 board/tqc/tqma31/Makefile             |   48 ++++
 board/tqc/tqma31/config.mk            |    2 
 board/tqc/tqma31/lowlevel_init.S      |  375 +++++++++++++++++++++++++++++++++
 board/tqc/tqma31/tqma31.c             |  269 ++++++++++++++++++++++++
 board/tqc/tqma31/u-boot.lds           |   72 ++++++
 cpu/arm1136/mx31/generic.c            |   21 ++
 drivers/i2c/mxc_i2c.c                 |   23 ++
 include/asm-arm/arch-mx31/mx31-regs.h |   92 ++++++++
 include/asm-arm/arch-mx31/mx31.h      |    1 
 include/configs/TQMA31.h              |  337 ++++++++++++++++++++++++++++++
 16 files changed, 1248 insertions(+), 8 deletions(-)
 create mode 100644 board/tqc/tqma31/Makefile
 create mode 100644 board/tqc/tqma31/config.mk
 create mode 100644 board/tqc/tqma31/lowlevel_init.S
 create mode 100644 board/tqc/tqma31/tqma31.c
 create mode 100644 board/tqc/tqma31/u-boot.lds
 create mode 100644 include/configs/TQMA31.h

[U-Boot-Users] [PATCH 01/10] [ARM] MXC: insert bus busy check in i2c_probe

[Jens Gehrlein]

On fast CPUs the time between two chip queries can become too short
to issue clear start and stop conditions. The bus seems to be blocked.
This cannot be compensated by just waiting for completed byte transfer.
The patch introduces polling of the bus busy bit in the I2C
controller's status register before the next bus access is possible.

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

 drivers/i2c/mxc_i2c.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)


diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index a218329..6f9306f 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -115,6 +115,16 @@ static int rx_byte(void)
 int i2c_probe(uchar chip)
 {
 	int ret;
+	int timeout = 100000;
+
+	/* Check if bus is busy before probing next chip */
+	while ((__REG16(I2C_BASE + I2SR) & I2SR_IBB) && --timeout)
+		udelay(1);
+
+	if (timeout == 0) {
+		printf ("\nerror: bus blocked\n");
+		return -1;
+	}
 
 	__REG16(I2C_BASE + I2CR) = 0; /* Reset module */
 	__REG16(I2C_BASE + I2CR) = I2CR_IEN;

[U-Boot-Users] [PATCH 01/10] [ARM] MXC: insert bus busy check in i2c_probe

[Jean-Christophe PLAGNIOL-VILLARD]

On 16:50 Fri 04 Jul     , Jens Gehrlein wrote:
> On fast CPUs the time between two chip queries can become too short
> to issue clear start and stop conditions. The bus seems to be blocked.
> This cannot be compensated by just waiting for completed byte transfer.
> The patch introduces polling of the bus busy bit in the I2C
> controller's status register before the next bus access is possible.
> 
> Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
> ---
> 
>  drivers/i2c/mxc_i2c.c |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> 
> diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
> index a218329..6f9306f 100644
> --- a/drivers/i2c/mxc_i2c.c
> +++ b/drivers/i2c/mxc_i2c.c
> @@ -115,6 +115,16 @@ static int rx_byte(void)
>  int i2c_probe(uchar chip)
>  {
>  	int ret;
> +	int timeout = 100000;
Could you explain why 100000?
> +
> +	/* Check if bus is busy before probing next chip */
> +	while ((__REG16(I2C_BASE + I2SR) & I2SR_IBB) && --timeout)
> +		udelay(1);
> +
> +	if (timeout == 0) {
> +		printf ("\nerror: bus blocked\n");
> +		return -1;
> +	}
>  
>  	__REG16(I2C_BASE + I2CR) = 0; /* Reset module */
>  	__REG16(I2C_BASE + I2CR) = I2CR_IEN;
Best Regards,
J.

[U-Boot-Users] [PATCH 01/10] [ARM] MXC: insert bus busy check in i2c_probe

[Jens Gehrlein]

Jean-Christophe PLAGNIOL-VILLARD schrieb:
> On 16:50 Fri 04 Jul     , Jens Gehrlein wrote:
>> On fast CPUs the time between two chip queries can become too short
>> to issue clear start and stop conditions. The bus seems to be blocked.
>> This cannot be compensated by just waiting for completed byte transfer.
>> The patch introduces polling of the bus busy bit in the I2C
>> controller's status register before the next bus access is possible.
>>
>> Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
>> ---
>>
>>  drivers/i2c/mxc_i2c.c |   10 ++++++++++
>>  1 files changed, 10 insertions(+), 0 deletions(-)
>>
>>
>> diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
>> index a218329..6f9306f 100644
>> --- a/drivers/i2c/mxc_i2c.c
>> +++ b/drivers/i2c/mxc_i2c.c
>> @@ -115,6 +115,16 @@ static int rx_byte(void)
>>  int i2c_probe(uchar chip)
>>  {
>>  	int ret;
>> +	int timeout = 100000;
> Could you explain why 100000?
>> +
>> +	/* Check if bus is busy before probing next chip */
>> +	while ((__REG16(I2C_BASE + I2SR) & I2SR_IBB) && --timeout)
>> +		udelay(1);
>> +
>> +	if (timeout == 0) {
>> +		printf ("\nerror: bus blocked\n");
>> +		return -1;
>> +	}
>>  
>>  	__REG16(I2C_BASE + I2CR) = 0; /* Reset module */
>>  	__REG16(I2C_BASE + I2CR) = I2CR_IEN;

You are right. 100 ms is too high, although it should be irrelevant for 
a U-Boot command. Measurement showed, that some 100 microseconds would 
be enough. Do you agree if I set the timeout value to 1 ms? Other proposals?

Kind regards,
Jens

[U-Boot-Users] [PATCH 01/10] [ARM] MXC: insert bus busy check in i2c_probe

[Wolfgang Denk]

In message <48720A3C.4040206@tqs.de> you wrote:
>
> You are right. 100 ms is too high, although it should be irrelevant for 
> a U-Boot command. Measurement showed, that some 100 microseconds would 
> be enough. Do you agree if I set the timeout value to 1 ms? Other proposals?

Never say 100 ms is irrelevant for U-Boot. It's 100 ms of total boot
time that you burn for nothing.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The price one pays for pursuing any profession,  or  calling,  is  an
intimate knowledge of its ugly side.                  - James Baldwin

[U-Boot-Users] [PATCH 01/10] [ARM] MXC: insert bus busy check in i2c_probe

[Jens Gehrlein]

Wolfgang Denk schrieb:
> In message <48720A3C.4040206@tqs.de> you wrote:
>> You are right. 100 ms is too high, although it should be irrelevant for 
>> a U-Boot command. Measurement showed, that some 100 microseconds would 
>> be enough. Do you agree if I set the timeout value to 1 ms? Other proposals?
> 
> Never say 100 ms is irrelevant for U-Boot. It's 100 ms of total boot
> time that you burn for nothing.

If it was relevant for booting, you would be right. But this routine 
isn't executed at boot time. It's called by the iprobe command invoked 
by the user on the command line.

As I proposed, 1 ms should be sufficient.

Kind regards,
Jens

[U-Boot-Users] [PATCH 02/10] [ARM] MX31: fix bit masks in function mx31_decode_pll()

[Jens Gehrlein]

Bits MPCTL[MFN] and MPCTL[MFD] were not fully covered.

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

 cpu/arm1136/mx31/generic.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c
index 29c08c1..bf4c99c 100644
--- a/cpu/arm1136/mx31/generic.c
+++ b/cpu/arm1136/mx31/generic.c
@@ -27,8 +27,8 @@
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
 	u32 mfi = (reg >> 10) & 0xf;
-	u32 mfn = reg & 0x3f;
-	u32 mfd = (reg >> 16) & 0x3f;
+	u32 mfn = reg & 0x3ff;
+	u32 mfd = (reg >> 16) & 0x3ff;
 	u32 pd =  (reg >> 26) & 0xf;
 
 	mfi = mfi <= 5 ? 5 : mfi;

[U-Boot-Users] [PATCH 03/10] [ARM] MX31: fix typos in defines for UART and SPI IO multiplexer pins

[Jens Gehrlein]

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

 board/imx31_litekit/imx31_litekit.c   |    2 +-
 board/imx31_phycore/imx31_phycore.c   |    4 ++--
 board/mx31ads/mx31ads.c               |    2 +-
 include/asm-arm/arch-mx31/mx31-regs.h |    4 ++--
 4 files changed, 6 insertions(+), 6 deletions(-)


diff --git a/board/imx31_litekit/imx31_litekit.c b/board/imx31_litekit/imx31_litekit.c
index 263dd9f..8cbc26e 100644
--- a/board/imx31_litekit/imx31_litekit.c
+++ b/board/imx31_litekit/imx31_litekit.c
@@ -50,7 +50,7 @@ int board_init (void)
 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
 	/* SPI2 */
 	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index 42ecb1e..ae93444 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -54,11 +54,11 @@ int board_init (void)
 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
 	/* setup pins for I2C2 (for EEPROM, RTC) */
 	mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
-	mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SCL);
+	mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
 
 	gd->bd->bi_arch_number = 447;		/* board id for linux */
 	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */
diff --git a/board/mx31ads/mx31ads.c b/board/mx31ads/mx31ads.c
index dd0e150..b6928fc 100644
--- a/board/mx31ads/mx31ads.c
+++ b/board/mx31ads/mx31ads.c
@@ -55,7 +55,7 @@ int board_init (void)
 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
 	/* SPI2 */
 	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index 02b7dcb..abe61f0 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -133,10 +133,10 @@
 #define MUX_RXD1__UART1_RXD_MUX	((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
 #define MUX_TXD1__UART1_TXD_MUX	((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
 #define MUX_RTS1__UART1_RTS_B	((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
-#define MUX_RTS1__UART1_CTS_B	((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
+#define MUX_CTS1__UART1_CTS_B	((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
 
 #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
-#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
+#define MUX_CSPI2_MISO__I2C2_SDA ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
 
 /*
  * Memory regions and CS

[U-Boot-Users] [PATCH 04/10] [ARM] TQMA31: add new board with i.MX31 processor

[Jens Gehrlein]

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

 MAINTAINERS                           |    4 
 MAKEALL                               |    1 
 Makefile                              |    3 
 board/tqc/tqma31/Makefile             |   48 ++++
 board/tqc/tqma31/config.mk            |    2 
 board/tqc/tqma31/lowlevel_init.S      |  375 +++++++++++++++++++++++++++++++++
 board/tqc/tqma31/tqma31.c             |   95 ++++++++
 board/tqc/tqma31/u-boot.lds           |   72 ++++++
 include/asm-arm/arch-mx31/mx31-regs.h |   42 ++++
 include/configs/TQMA31.h              |  271 ++++++++++++++++++++++++
 10 files changed, 913 insertions(+), 0 deletions(-)
 create mode 100644 board/tqc/tqma31/Makefile
 create mode 100644 board/tqc/tqma31/config.mk
 create mode 100644 board/tqc/tqma31/lowlevel_init.S
 create mode 100644 board/tqc/tqma31/tqma31.c
 create mode 100644 board/tqc/tqma31/u-boot.lds
 create mode 100644 include/configs/TQMA31.h


diff --git a/MAINTAINERS b/MAINTAINERS
index a3d70b1..dff1757 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -591,6 +591,10 @@ Michael Schwingen <michael@schwingen.org>
 	actux3			xscale
 	actux4			xscale
 
+Jens Gehrlein <sew_s@tqs.de>
+
+	TQMA31			i.MX31
+
 #########################################################################
 # x86 Systems:								#
 #									#
diff --git a/MAKEALL b/MAKEALL
index 32caab7..4e442c5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -524,6 +524,7 @@ LIST_ARM11="		\
 	imx31_litekit	\
 	imx31_phycore	\
 	mx31ads		\
+	TQMA31		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 8bfc891..e3ade25 100644
--- a/Makefile
+++ b/Makefile
@@ -2664,6 +2664,9 @@ imx31_phycore_config	: unconfig
 mx31ads_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31
 
+TQMA31_config		: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 tqma31 tqc mx31
+
 #========================================================================
 # i386
 #========================================================================
diff --git a/board/tqc/tqma31/Makefile b/board/tqc/tqma31/Makefile
new file mode 100644
index 0000000..ed403e8
--- /dev/null
+++ b/board/tqc/tqma31/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+# Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= tqma31.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/tqc/tqma31/config.mk b/board/tqc/tqma31/config.mk
new file mode 100644
index 0000000..19df69e
--- /dev/null
+++ b/board/tqc/tqma31/config.mk
@@ -0,0 +1,2 @@
+TEXT_BASE = 0x8ff00000
+
diff --git a/board/tqc/tqma31/lowlevel_init.S b/board/tqc/tqma31/lowlevel_init.S
new file mode 100644
index 0000000..50db3a1
--- /dev/null
+++ b/board/tqc/tqma31/lowlevel_init.S
@@ -0,0 +1,375 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ * Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+#include <config.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ */
+.macro init_aips
+
+	/* Setup the Peripheral Port Remap register inside the core */
+	ldr r0, =0x40000015        /* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
+
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x77777777
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+	ldr r0, =0x53F00000
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+
+	ldr r0, =0x53F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+.endm /* init_aips */
+
+
+/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+	ldr r0, =0x43F04000
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+	ldr r1, =0x00302154
+	str r1, [r0, #0x000]        /* for S0 */
+	str r1, [r0, #0x100]        /* for S1 */
+	str r1, [r0, #0x200]        /* for S2 */
+	str r1, [r0, #0x300]        /* for S3 */
+	str r1, [r0, #0x400]        /* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =0x10
+	str r1, [r0, #0x010]        /* for S0 */
+	str r1, [r0, #0x110]        /* for S1 */
+	str r1, [r0, #0x210]        /* for S2 */
+	str r1, [r0, #0x310]        /* for S3 */
+	str r1, [r0, #0x410]        /* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =0x0
+	str r1, [r0, #0x800]        /* for M0 */
+	str r1, [r0, #0x900]        /* for M1 */
+	str r1, [r0, #0xA00]        /* for M2 */
+	str r1, [r0, #0xB00]        /* for M3 */
+	str r1, [r0, #0xC00]        /* for M4 */
+	str r1, [r0, #0xD00]        /* for M5 */
+.endm /* init_max */
+
+
+/* RedBoot: M3IF setup */
+.macro init_m3if
+	/* Configure M3IF registers */
+	ldr r1, =0xB8003000
+	/*
+	* M3IF Control Register (M3IFCTL)
+	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
+	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
+	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
+	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
+	*						------------
+	*						  0x00000040
+	*/
+	ldr r0, =0x00000040
+	str r0, [r1]  /* M3IF control reg */
+.endm /* init_m3if */
+
+
+/* RedBoot: To support 133MHz DDR */
+.macro  init_drive_strength
+	/*
+	 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+	 * in SW_PAD_CTL registers
+	 */
+
+	/* SDCLK */
+	ldr r1, =0x43FAC200
+	ldr r0, [r1, #0x6C]
+	bic r0, r0, #(1 << 12)
+	str r0, [r1, #0x6C]
+
+	/* CAS */
+	ldr r0, [r1, #0x70]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x70]
+
+	/* RAS */
+	ldr r0, [r1, #0x74]
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x74]
+
+	/* CS2 (CSD0) */
+	ldr r0, [r1, #0x7C]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x7C]
+
+	/* DQM3 */
+	ldr r0, [r1, #0x84]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x84]
+
+	/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+	ldr r2, =22	/* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+	ldr r0, [r1, #0x88]
+	bic r0, r0, #(1 << 22)
+	bic r0, r0, #(1 << 12)
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x88]
+	add r1, r1, #4
+	subs r2, r2, #0x1
+	bne pad_loop
+.endm /* init_drive_strength */
+
+
+/* initialize PLL */
+.macro init_pll
+	/*
+	 * Switch on Display Interface because of the change of the clock
+	 * divider. According to the description of PDR0[HSP_PODF] in the
+	 * processor reference manual the CCM waits for an ackn. of the IPU.
+	 */
+	REG	IPU_CONF, IPU_CONF_DI_EN
+
+	/* Clock Control Module: */
+	REG	CCM_CCMR, 0x074B0BF5				/* Use CKIH, MCU PLL off */
+	DELAY	0x40000
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE			/* MCU PLL on */
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS	/* Switch to MCU PLL */
+
+#if defined CONFIG_MX31_CPU_399_MHZ
+	/* Platform clocks */
+	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff)	/* camera sensor interface */		\
+			| PDR0_PER_PODF(6-1)	/* periph. if derived from USB clock */ \
+			| PDR0_HSP_PODF(3-1)	/* IPU 133 MHz */                       \
+			| PDR0_NFC_PODF(7-1)	/* NAND FC 19 MHz */                    \
+			| PDR0_IPG_PODF(2-1)	/* peripherals 66.5 MHz */              \
+			| PDR0_MAX_PODF(3-1)	/* AHB 133 MHz */                       \
+			| PDR0_MCU_PODF(1-1)	/* core 399 MHz */
+	/* MCU PLL */
+	REG	CCM_MPCTL, PLL_PD(1-1) | PLL_MFD(52-1) | PLL_MFI(7) | PLL_MFN(35)
+#elif defined CONFIG_MX31_CPU_532_MHZ
+	/* Platform clocks */
+	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff)	/* camera sensor interface */		\
+			| PDR0_PER_PODF(8-1)	/* periph. if derived from USB clock */	\
+			| PDR0_HSP_PODF(4-1)	/* IPU 133 MHz */                      	\
+			| PDR0_NFC_PODF(7-1)	/* NAND FC 19 MHz */                   	\
+			| PDR0_IPG_PODF(2-1)	/* peripherals 66.5 MHz */             	\
+			| PDR0_MAX_PODF(4-1)	/* AHB 133 MHz */                      	\
+			| PDR0_MCU_PODF(1-1)	/* core 532 MHz */
+	/* MCU PLL */
+	REG	CCM_MPCTL, PLL_PD(1-1) | PLL_MFD(52-1) | PLL_MFI(10) | PLL_MFN(12)
+#else
+#error Please define CPU core frequency (CONFIG_CPU_399_MHZ or CONFIG_CPU_532_MHZ)!
+#endif /* CONFIG_CPU_xxx_MHZ */
+
+	/* Serial PLL. Default: 1, 4, 12, 1 */
+	REG	CCM_SPCTL, PLL_PD(2-1) | PLL_MFD(5-1) | PLL_MFI(12) | PLL_MFN(1)
+.endm /* init_sdram */
+
+
+/* setup SDRAM on CSD0 */
+.macro init_sdram
+	/*
+	 * Enhanced SDRAM Miscellaneous Register
+	 *	Latency Hiding Enable
+	 *	LPDDR delay line measure unit is enabled
+	 *	LPDDR Delay Line is not reset
+	 *	Enable Mobile DDR SDRAM operation
+	 *	Soft Reset is disabled
+	 */
+	REG	ESDMISC, 0x00000004
+
+	/*
+	 * Enhanced SDRAM Configuration Register 0
+	 *	tXP 4 clock delay before new COMMAND issued to LPDDR
+	 *	tWTR tLPDDR WRITE to READ Command Delay = 2 clock
+	 *	tRP SDRAM Row Precharge Delay = 3 clock
+	 *	tMRD?SDRAM Load Mode Register to ACTIVE Command = 3 clock
+	 *	tWR SDRAM WRITE to PRECHARGE Command = 3 clock
+	 *	tRAS SDRAM ACTIVE to PRECHARGE Command = 6 clock
+	 *	tRRD ACTIVE Bank A to ACTIVE Bank B Command = 2 clock
+	 *	tCAS CAS Latency = 3 clock
+	 *	tRCD SDRAM Row to Column Delay = 3 clock
+	 *	tRC SDRAM Row Cycle Delay = 13 clocks
+	 */
+	REG	ESDCFG0, 0x006ac73c
+
+	/*
+	 * Enhanced SDRAM Control Register 0
+	 *	Enhanced SDRAM Controller Enable = 1
+	 *	SDRAM Controller Operating Mode = 001 Precharge Command
+	 *	Supervisor Protect = 0 User mode accesses are allowed to this
+	 *		chip select region
+	 *	ROW Row Address Width. = 011 14 Row Addresses
+	 *	COL Column Address Width = 01 9 Col Addresses
+	 *	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
+	 *		aligned to D[31:16]
+	 *	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
+	 *		(bit field reset value)
+	 *	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
+	 *	FP Full Page = 0 0 Burst Length of the external memory device
+	 *		is not set to Full Page
+	 *	BL Burst Length = 0
+	 *	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
+	 */
+	REG	ESDCTL0, 0x92200000
+	REG	0x80000f00, 0x12344321
+
+
+  	/*
+  	 * Enhanced SDRAM Control Register 0
+	 *	Enhanced SDRAM Controller Enable = 1
+	 *	SDRAM Controller Operating Mode = 010 Auto-Refresh Command
+	 *	Supervisor Protect = 0 User mode accesses are allowed to this
+	 *		chip select region
+	 *	ROW Row Address Width. = 011 14 Row Addresses
+	 *	COL Column Address Width = 01 9 Col Addresses
+	 *	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
+	 *		aligned to D[31:16]
+	 *	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
+	 *		(bit field reset value)
+	 *	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
+	 *	FP Full Page = 0 0 Burst Length of the external memory device
+	 *		is not set to Full Page
+	 *	BL Burst Length = 0
+	 *	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
+	 */
+	REG	ESDCTL0, 0xa2200000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+
+	/*
+	 * Enhanced SDRAM Control Register 0
+	 * 	Enhanced SDRAM Controller Enable = 1
+	 * 	SDRAM Controller Operating Mode = 001 Precharge Command
+	 * 	Supervisor Protect = 0 User mode accesses are allowed to this
+	 *		chip select region
+	 * 	ROW Row Address Width. = 011 14 Row Addresses
+	 * 	COL Column Address Width = 01 9 Col Addresses
+	 * 	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
+	 *		aligned to D[31:16]
+	 * 	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
+	 *		(bit field reset value)
+	 * 	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
+	 * 	FP Full Page = 0 0 Burst Length of the external memory device
+	 *		is not set to Full Page.
+	 * 	BL Burst Length = 0
+	 * 	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
+	 */
+	REG	ESDCTL0, 0xb2200000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+
+	/*
+	 * Enhanced SDRAM Control Register 0
+	 *	Enhanced SDRAM Controller Enable = 1
+	 *	SDRAM Controller Operating Mode = 000 Normal Read/Write
+	 *	Supervisor Protect = 0 User mode accesses are allowed to this
+	 *		chip select region
+	 *	ROW Row Address Width. = 011 14 Row Addresses
+	 *	COL Column Address Width = 10 10 Col Addresses
+	 *	DSIZ SDRAM Memory Data Width = 10 32-bit memory width
+	 *	SREFR SDRAM Refresh Rate  = 011 Refresh 7,81 ?s
+	 *	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
+	 *	FP Full Page = 0 0 Burst Length of the external memory device
+	 *		is not set to Full Page
+	 *	BL Burst Length = 8
+	 *	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
+	 */
+	REG	ESDCTL0, 0x83226080
+	REG	0x80000000, 0xDEADBEEF
+
+	/*
+	 * Enhanced SDRAM Miscellaneous Register
+	 *	Latency Hiding Enable
+	 *	LPDDR delay line measure unit is enabled
+	 *	LPDDR Delay Line is reset
+	 *	Enable Mobile DDR SDRAM operation
+	 *	Soft Reset is disabled
+	 */
+	REG	ESDMISC, 0x0000000c
+.endm /* init_sdram */
+
+
+.globl lowlevel_init
+lowlevel_init:
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	init_drive_strength
+
+	init_pll
+
+	init_sdram
+
+	mov pc, lr
diff --git a/board/tqc/tqma31/tqma31.c b/board/tqc/tqma31/tqma31.c
new file mode 100644
index 0000000..7cec8db
--- /dev/null
+++ b/board/tqc/tqma31/tqma31.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void setup_chipselects (void)
+{
+	/* NOR Flash on CS0 */
+	__REG (CSCR_U(0)) = CSCR_U_CNC_3 | CSCR_U_WSC_12 | CSCR_U_EDC_4;
+	__REG (CSCR_A(0)) = CSCR_A_RWA_2 | CSCR_A_RWN_2 | CSCR_A_LBN_2_MUM0;
+	__REG (CSCR_L(0)) = CSCR_L_OEA_10 | CSCR_L_EBWA_3 | CSCR_L_EBWN_3 \
+		| CSCR_L_EBC_ONLY_WA | CSCR_L_DSZ_16_MUM0 | CSCR_L_CSEN;
+
+	/* Ethernet controller on CS4 */
+	__REG (CSCR_U(4)) = CSCR_U_CNC_1 | CSCR_U_WSC_22 | CSCR_U_EDC_4;
+	__REG (CSCR_A(4)) = CSCR_A_RWA_2 | CSCR_A_RWN_15;
+	__REG (CSCR_L(4)) = CSCR_L_OEA_2 | CSCR_L_OEN_15 | CSCR_L_CSN_15 \
+		| CSCR_L_DSZ_16_MUM0 | CSCR_L_CSEN;
+}
+
+static void setup_iomux (void)
+{
+	/* Pins for UART1 */
+	mx31_gpio_mux (MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux (MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux (MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux (MUX_CTS1__UART1_CTS_B);
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init (void)
+{
+	/* WEIM burst clock runs all the time */
+	__REG (WCR) = WCR_BCM_1;
+
+	setup_chipselects ();
+	setup_iomux ();
+
+	/*
+	 * FIXME:
+	 * Replace machine type ID by symbolic define MACH_TYPE_TQMA31 as soon
+	 * as updated file mach-types.h is available in U-Boot tree.
+	 * Machine type ID 1810 for TQMA31 has been registered on 2008-06-25.
+	 */
+	/* Machine type ID for ARM linux */
+	gd->bd->bi_arch_number = 1810;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = 0x80000100;
+
+	/*
+	 * Tell other U-Boot entities: relocation done. For instance, needed
+	 * to enable command line history.
+	 */
+	gd->flags |= GD_FLG_RELOC;
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf ("Board: TQMA31\n");
+	return 0;
+}
diff --git a/board/tqc/tqma31/u-boot.lds b/board/tqc/tqma31/u-boot.lds
new file mode 100644
index 0000000..6b1c06a
--- /dev/null
+++ b/board/tqc/tqma31/u-boot.lds
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+	  cpu/arm1136/start.o		(.text)
+	  board/tqc/tqma31/libtqma31.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/environment.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index abe61f0..ea15108 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -61,11 +61,53 @@
 #define PLL_MFI(x)		(((x) & 0xf) << 10)
 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
 
+#define ESDCTL_BASE	0xB8001000
+#define ESDCTL0		(ESDCTL_BASE + 0x00)
+#define ESDCFG0		(ESDCTL_BASE + 0x04)
+#define ESDCTL1		(ESDCTL_BASE + 0x08)
+#define ESDCFG1		(ESDCTL_BASE + 0x0C)
+#define ESDMISC		(ESDCTL_BASE + 0x10)
+#define ESDCDLY1	(ESDCTL_BASE + 0x20)
+#define ESDCDLY2	(ESDCTL_BASE + 0x24)
+#define ESDCDLY3	(ESDCTL_BASE + 0x28)
+#define ESDCDLY4	(ESDCTL_BASE + 0x2C)
+#define ESDCDLY5	(ESDCTL_BASE + 0x30)
+#define ESDCDLYL	(ESDCTL_BASE + 0x34)
+
 #define WEIM_BASE	0xb8002000
 #define CSCR_U(x)	(WEIM_BASE + (x) * 0x10)
 #define CSCR_L(x)	(WEIM_BASE + 4 + (x) * 0x10)
 #define CSCR_A(x)	(WEIM_BASE + 8 + (x) * 0x10)
 
+#define CSCR_U_CNC_1		0x00004000
+#define CSCR_U_CNC_3		0x0000C000
+#define CSCR_U_WSC_9		0x00000900
+#define CSCR_U_WSC_12		0x00000C00
+#define CSCR_U_WSC_22		0x00001600
+#define CSCR_U_EDC_4		0x00000004
+#define CSCR_U_EDC_13		0x0000000D
+
+#define CSCR_L_OEA_2		0x20000000
+#define CSCR_L_OEA_4		0x40000000
+#define CSCR_L_OEA_10		0xA0000000
+#define CSCR_L_OEN_15		0x0F000000
+#define CSCR_L_EBWA_3		0x00300000
+#define CSCR_L_EBWN_3		0x00030000
+#define CSCR_L_CSA_4		0x00004000
+#define CSCR_L_CSN_15		0x000000F0
+#define CSCR_L_EBC_ONLY_WA	0x00000800
+#define CSCR_L_DSZ_16_MUM0	0x00000500
+#define CSCR_L_CSEN		0x00000001
+
+#define CSCR_A_RWA_2		0x00200000
+#define CSCR_A_RWN_2		0x00020000
+#define CSCR_A_RWN_15		0x000F0000
+#define CSCR_A_LBN_2_MUM0	0x00000800
+
+#define WCR			(WEIM_BASE + 0x60)
+#define WCR_BCM_1		0x00000004
+#define WCR_BCM_0		0x00000000
+
 #define IOMUXC_BASE	0x43FAC000
 #define IOMUXC_GPR	(IOMUXC_BASE + 0x8)
 #define IOMUXC_SW_MUX_CTL(x)	(IOMUXC_BASE + 0xc + (x) * 4)
diff --git a/include/configs/TQMA31.h b/include/configs/TQMA31.h
new file mode 100644
index 0000000..255355d
--- /dev/null
+++ b/include/configs/TQMA31.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
+ *
+ * Configuration settings for the TQMA31 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*******************************************************************************
+ * CPU
+ ******************************************************************************/
+
+#include <asm/arch/mx31-regs.h>
+
+/* This is an ARM1136 core */
+#define CONFIG_ARM1136			1
+
+/* in an i.MX31 processor */
+#define CONFIG_MX31			1
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+
+/*******************************************************************************
+ * Clocks
+ ******************************************************************************/
+
+ /* Frequency on CKIH in Hz. This is the MCU PLL input clock on TQMA31. */
+#define CONFIG_MX31_HCLK_FREQ		26000000
+
+/* Desired CPU core frequency (see PLL settings in lowlevel_init.S) */
+#define CONFIG_MX31_CPU_399_MHZ
+#undef CONFIG_MX31_CPU_532_MHZ
+
+/* Timer tick */
+#define CFG_HZ				32768
+
+/*
+ * Alternative clock input for MCU PLL.
+ * Unused on TQMA31, but must be defined to avoid compiler errors.
+ */
+#define CONFIG_MX31_CLK32		32000
+
+
+/*******************************************************************************
+ * RAM
+ ******************************************************************************/
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+/*
+ * PHYS_SDRAM_1 and PHYS_SDRAM_1_SIZE are passed to the Linux kernel.
+ * The size can be overridden by the kernel boot parameter "mem=".
+ */
+#define PHYS_SDRAM_1			CSD0_BASE
+#define PHYS_SDRAM_1_SIZE		(256 * 1024 * 1024)
+
+/* Default values for command mtest */
+#define CFG_MEMTEST_START		PHYS_SDRAM_1
+#define CFG_MEMTEST_END			(PHYS_SDRAM_1_SIZE - 0x100000)
+
+
+/*******************************************************************************
+ * NOR-Flash
+ ******************************************************************************/
+
+#define CFG_FLASH_BASE			CS0_BASE
+
+/* Max number of memory banks */
+#define CFG_MAX_FLASH_BANKS		4
+
+/*
+ * Bank start addresses.
+ * 4 x 32 MiB is the maximum for user and U-Boot code. Please adapt the list
+ * as well as CFG_MAX_FLASH_BANKS to your TQM. Also consider dual die chips
+ * or single die chips, e.g. one dual die chip represents two banks.
+ */
+#define CFG_FLASH_BANKS_LIST		{CFG_FLASH_BASE, 		\
+					CFG_FLASH_BASE + 32*1024*1024,	\
+					CFG_FLASH_BASE + 64*1024*1024,	\
+					CFG_FLASH_BASE + 96*1024*1024}
+
+/* Max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT		259
+
+/* Monitor at beginning of flash */
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+
+/* Reserved flash space for U-Boot image in bytes */
+#define CFG_MONITOR_LEN			(128 * 1024)
+
+/* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI			1
+
+/* Use drivers/cfi_flash.c */
+#define CFG_FLASH_CFI_DRIVER		1
+
+/* Use buffered writes (~10x faster) */
+#define CFG_FLASH_USE_BUFFER_WRITE	1
+
+/* Use hardware sector protection */
+#define CFG_FLASH_PROTECTION		1
+
+
+/*******************************************************************************
+ * Serial
+ ******************************************************************************/
+
+/* Configure processor internal UART */
+#define CONFIG_MX31_UART		1
+
+/* Configure UART1 */
+#define CFG_MX31_UART1			1
+
+/* Use UART1 for console */
+#define CONFIG_CONS_INDEX		1
+
+/* Default baudrate */
+#define CONFIG_BAUDRATE			115200
+
+/* Possible baudrates */
+#define CFG_BAUDRATE_TABLE		{9600, 19200, 38400, 57600, 115200}
+
+
+/*******************************************************************************
+ * Ethernet
+ ******************************************************************************/
+
+#define CONFIG_DRIVER_SMC911X		1
+#define CONFIG_DRIVER_SMC911X_32_BIT	1
+#define CONFIG_DRIVER_SMC911X_BASE	CS4_BASE
+
+
+/*******************************************************************************
+ * Commands
+ ******************************************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+
+/*******************************************************************************
+ * Environment
+ ******************************************************************************/
+
+#define CONFIG_BOOTDELAY		4
+
+/* Default values */
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_IPADDR			172.20.5.100
+#define CONFIG_SERVERIP			172.20.5.121
+
+/*
+ * Default value for env. variable "loadaddr".
+ * Don't use arithmetic here, because it will be converted
+ * into a string (see common/environment.c)
+ */
+#define CONFIG_LOADADDR			0x80800000
+
+/* Default load address */
+#define CFG_LOAD_ADDR			CONFIG_LOADADDR
+
+/* Allow to modify environment variables "serial#" and "ethaddr" */
+#define CONFIG_ENV_OVERWRITE
+
+#define	CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_OFFSET			0x20000
+#define CFG_ENV_ADDR			(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#define CFG_ENV_SECT_SIZE		0x20000
+#define CFG_ENV_SIZE			CFG_ENV_SECT_SIZE
+
+/* Address and size of redundant environment sector */
+#define CFG_ENV_OFFSET_REDUND		(CFG_ENV_OFFSET + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND		CFG_ENV_SECT_SIZE
+
+/*
+ * Kernel parameter "jtag=on" is Freescale-specific extension of the
+ * mx31ads BSP. Use it to enable serial console output in Linux.
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=tqma31\0"						\
+	"uboot_addr=0xa0000000\0"					\
+	"uboot=tqma31/u-boot.bin\0"					\
+	"kernel=tqma31/uImage\0"					\
+	"nfsroot=/opt/eldk/arm\0"					\
+	"bootargs_base=setenv bootargs "				\
+		"jtag=on "						\
+		"console=ttymxc0,115200\0"				\
+	"bootargs_nfs=setenv bootargs ${bootargs} "			\
+		"root=/dev/nfs "					\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+			"${netmask}:${hostname}:${netdev}:off "		\
+		"panic=1 "						\
+		"nfsroot=${serverip}:${nfsroot}\0"			\
+	"bootcmd=run bootcmd_net\0"					\
+	"bootcmd_net=run bootargs_base bootargs_nfs; "			\
+		"tftpboot ${loadaddr} ${kernel}; bootm\0"		\
+	"prg_uboot=tftpboot ${loadaddr} ${uboot}; "			\
+		"protect off ${uboot_addr} 0xa001ffff; "		\
+		"erase ${uboot_addr} 0xa001ffff; "			\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}; "		\
+		"setenv filesize; saveenv\0"
+
+
+/*******************************************************************************
+ * JFFS2 partitions
+ ******************************************************************************/
+
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+
+
+/*******************************************************************************
+ * Miscellaneous
+ ******************************************************************************/
+
+/* Total available space for malloc in bytes */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+
+/* Regular stack size in bytes */
+#define CONFIG_STACKSIZE		(128 * 1024)
+
+/* Size in bytes reserved for initial global data */
+#define CFG_GBL_DATA_SIZE		128
+
+/* Console I/O buffer size in bytes */
+#define CFG_CBSIZE			256
+
+/* Print buffer size in bytes */
+#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+/* Max number of command arguments */
+#define CFG_MAXARGS			16
+
+/* Boot argument buffer size in bytes */
+#define CFG_BARGSIZE			CFG_CBSIZE
+
+#define CFG_LONGHELP
+#define CFG_PROMPT			"=> "
+
+/* Add command line history and command line edit possibility */
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_ARP_TIMEOUT		200UL
+
+#endif /* __CONFIG_H */

[U-Boot-Users] [PATCH 04/10] [ARM] TQMA31: add new board with i.MX31 processor

[Magnus Lilja]

Hi,

Jens Gehrlein wrote:
> diff --git a/board/tqc/tqma31/lowlevel_init.S b/board/tqc/tqma31/lowlevel_init.S
> new file mode 100644
> index 0000000..50db3a1
> --- /dev/null
> +++ b/board/tqc/tqma31/lowlevel_init.S
> @@ -0,0 +1,375 @@
> +/*
> + * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
> + * Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <asm/arch/mx31-regs.h>
> +#include <config.h>
> +
> +.macro REG reg, val
> +	ldr r2, =\reg
> +	ldr r3, =\val
> +	str r3, [r2]
> +.endm
> +
> +.macro REG8 reg, val
> +	ldr r2, =\reg
> +	ldr r3, =\val
> +	strb r3, [r2]
> +.endm
> +
> +.macro DELAY loops
> +	ldr r2, =\loops
> +1:
> +	subs	r2, r2, #1
> +	nop
> +	bcs 1b
> +.endm
> +
> +
> +/*
> + * AIPS setup - Only setup MPROTx registers.
> + * The PACR default values are good.
> + */
> +.macro init_aips
> +
> +	/* Setup the Peripheral Port Remap register inside the core */
> +	ldr r0, =0x40000015        /* start from AIPS 2GB region */
> +	mcr p15, 0, r0, c15, c2, 4
> +
> +	/*
> +	 * Set all MPROTx to be non-bufferable, trusted for R/W,
> +	 * not forced to user-mode.
> +	 */
> +	ldr r0, =0x43F00000

How about adding/using symbolic names for i.MX31 register addresses also in the init_aips, init_max, init_m3if and init_drive_strength macros? It helps readability IMO.


Regards, Magnus

[U-Boot-Users] [PATCH 04/10] [ARM] TQMA31: add new board with i.MX31 processor

[Magnus Lilja]

Hi again

> diff --git a/board/tqc/tqma31/Makefile b/board/tqc/tqma31/Makefile
> new file mode 100644
> index 0000000..ed403e8
> --- /dev/null
> +++ b/board/tqc/tqma31/Makefile
> @@ -0,0 +1,48 @@
> +#
> +# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
> +# Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB    = $(obj)lib$(BOARD).a
> +
> +COBJS  := tqma31.o
> +SOBJS  := lowlevel_init.o
> +
> +SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS   := $(addprefix $(obj),$(COBJS))
> +SOBJS  := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
> +       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
> +
> +clean:
> +       rm -f $(SOBJS) $(OBJS)
> +
> +distclean:     clean
> +       rm -f $(LIB) core *.bak .depend

The .depend file needs a $(obj)-prefix here (Wolfgang recenty
corrected this in a number of Makefiles):
rm -f $(LIB) core *.bak $(obj).depend

Regards, Magnus

[U-Boot-Users] [PATCH 04/10] [ARM] TQMA31: add new board with i.MX31 processor

[Detlev Zundel]

Hi Jens,

> +int dram_init (void)
> +{
> +	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> +	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> +
> +	return 0;
> +}

Can't you use autodetection code like we do on many (hopefully most)
PowerPC boards?

Cheers
  Detlev

-- 
If we knew what it was we were doing, we wouldn't call it research.
                                            -- Einstein
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de

[U-Boot-Users] [PATCH 04/10] [ARM] TQMA31: add new board with i.MX31 processor

[Jens Gehrlein]

Hi Detlev,

Detlev Zundel schrieb:
> Hi Jens,
> 
>> +int dram_init (void)
>> +{
>> +	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
>> +	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
>> +
>> +	return 0;
>> +}
> 
> Can't you use autodetection code like we do on many (hopefully most)
> PowerPC boards?

I wish I could, believe me. But for a nice C-routine I need a stack 
while running in flash. Unlike the PowerPC code, current U-Boot ARM code 
doesn't provide such mechanism. I think, the effort to provide it isn't 
little.

Kind regards,
Jens

[U-Boot-Users] [PATCH 05/10] [ARM] TQMA31: add support for I2C, I2C temperature sensor and I2C-EEPROM

[Jens Gehrlein]

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

 board/tqc/tqma31/tqma31.c             |    6 +++++
 cpu/arm1136/mx31/generic.c            |   17 ++++++++++++++
 drivers/i2c/mxc_i2c.c                 |   13 +++++++++++
 include/asm-arm/arch-mx31/mx31-regs.h |   32 ++++++++++++++++++++++++++
 include/asm-arm/arch-mx31/mx31.h      |    1 +
 include/configs/TQMA31.h              |   40 +++++++++++++++++++++++++++++++++
 6 files changed, 109 insertions(+), 0 deletions(-)


diff --git a/board/tqc/tqma31/tqma31.c b/board/tqc/tqma31/tqma31.c
index 7cec8db..0c67af3 100644
--- a/board/tqc/tqma31/tqma31.c
+++ b/board/tqc/tqma31/tqma31.c
@@ -49,6 +49,12 @@ static void setup_iomux (void)
 	mx31_gpio_mux (MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux (MUX_RTS1__UART1_RTS_B);
 	mx31_gpio_mux (MUX_CTS1__UART1_CTS_B);
+
+	/* Pins for I2C1 */
+	mx31_gpio_mux (MUX_I2C_CLK__I2C1_SCL);
+	mx31_gpio_mux (MUX_I2C_DAT__I2C1_SDA);
+	mx31_pad_ctl (PAD_CTL_I2C_CLK, PAD_CTL_IPP_ODE_OD);
+	mx31_pad_ctl (PAD_CTL_I2C_DAT, PAD_CTL_IPP_ODE_OD);
 }
 
 int dram_init (void)
diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c
index bf4c99c..9999e12 100644
--- a/cpu/arm1136/mx31/generic.c
+++ b/cpu/arm1136/mx31/generic.c
@@ -90,6 +90,23 @@ void mx31_gpio_mux(unsigned long mode)
 	__REG(reg) = tmp;
 }
 
+void mx31_pad_ctl (u32 field, u32 val)
+{
+	u32 reg, shift, mask, tmp;
+
+	/* extract 32 bit register address and shifter for bit field */
+	reg = IOMUXC_BASE + (field >> 8);
+	shift = field & 0xFF;
+
+	/* field consists of 10 bits */
+	mask = 0x3FF << shift;
+
+	tmp = __REG(reg);
+	tmp &= ~mask;
+	tmp |= (val << shift) & mask;
+	__REG(reg) = tmp;
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo (void)
 {
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 6f9306f..68d2720 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -209,4 +209,17 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
 	return 0;
 }
 
+int i2c_get_bus_speed(void)
+{
+	return -1;
+}
+
+int i2c_set_bus_speed (unsigned int speed)
+{
+	if (speed != CFG_I2C_SPEED)
+		return -1;
+
+	return 0;
+}
+
 #endif /* CONFIG_HARD_I2C */
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index ea15108..c0e516f 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -168,6 +168,9 @@
 #define MUX_CTL_CSPI2_SS2	0x87
 #define MUX_CTL_CSPI2_MOSI	0x8b
 
+#define MUX_CTL_I2C_CLK		0xa2
+#define MUX_CTL_I2C_DAT		0xa3
+
 /* The modes a specific pin can be in
  * these macros can be used in mx31_gpio_mux() and have the form
  * MUX_[contact name]__[pin function]
@@ -180,6 +183,35 @@
 #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
 #define MUX_CSPI2_MISO__I2C2_SDA ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
 
+#define MUX_I2C_CLK__I2C1_SCL	((MUX_CTL_FUNC << 8) | MUX_CTL_I2C_CLK)
+#define MUX_I2C_DAT__I2C1_SDA	((MUX_CTL_FUNC << 8) | MUX_CTL_I2C_DAT)
+
+/* bits in the SW_PAD_CTL registers */
+#define PAD_CTL_LOOPBACK_DIS		(0 << 9)
+#define PAD_CTL_LOOPBACK_ENA		(1 << 9)
+#define PAD_CTL_IPP_PUE_DIS		(0 << 7)
+#define PAD_CTL_IPP_PUE_KEEPER		(2 << 7)
+#define PAD_CTL_IPP_PUE_PULL		(3 << 7)
+#define PAD_CTL_IPP_PUS_100K_DN		(0 << 5)
+#define PAD_CTL_IPP_PUS_100K_UP		(1 << 5)
+#define PAD_CTL_IPP_HYS_STD		(0 << 4)
+#define PAD_CTL_IPP_HYS_SCHMITT		(1 << 4)
+#define PAD_CTL_IPP_ODE_STD		(0 << 3)
+#define PAD_CTL_IPP_ODE_OD		(1 << 3)
+#define PAD_CTL_IPP_DSE_STD		(0 << 1)
+#define PAD_CTL_IPP_DSE_HIGH		(1 << 1)
+#define PAD_CTL_IPP_DSE_MAX		(2 << 1)
+#define PAD_CTL_IPP_SRE_SLOW		(0 << 0)
+#define PAD_CTL_IPP_SRE_FAST		(1 << 0)
+
+/* bit fields in the SW_PAD_CTL registers, offsets based on IOMUXC_BASE */
+#define	PAD_CTL_IO1_SHIFT		0
+#define	PAD_CTL_IO2_SHIFT		10
+#define	PAD_CTL_IO3_SHIFT		20
+#define PAD_CTL_I2C_CLK			((0x21C << 8) | PAD_CTL_IO2_SHIFT)
+#define PAD_CTL_I2C_DAT			((0x21C << 8) | PAD_CTL_IO1_SHIFT)
+
+
 /*
  * Memory regions and CS
  */
diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h
index 0552c27..7b784e6 100644
--- a/include/asm-arm/arch-mx31/mx31.h
+++ b/include/asm-arm/arch-mx31/mx31.h
@@ -26,5 +26,6 @@
 
 extern u32 mx31_get_ipg_clk(void);
 extern void mx31_gpio_mux(unsigned long mode);
+extern void mx31_pad_ctl (u32 field, u32 val);
 
 #endif /* __ASM_ARCH_MX31_H */
diff --git a/include/configs/TQMA31.h b/include/configs/TQMA31.h
index 255355d..f96fd74 100644
--- a/include/configs/TQMA31.h
+++ b/include/configs/TQMA31.h
@@ -154,6 +154,43 @@
 
 
 /*******************************************************************************
+ * I2C
+ ******************************************************************************/
+
+/* Use the processor internal controller */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+
+/* Configure I2C1 */
+#define CFG_I2C_MX31_PORT1
+
+#define CFG_I2C_SPEED 			100000
+#define CFG_I2C_SLAVE 			0
+
+/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES		{0x00}
+
+/* I2C EEPROM, configuration for onboard EEPROM */
+#define CFG_I2C_EEPROM_ADDR		0x50
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+
+/* 32 bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/* 10ms +/- 20% */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75			1	/* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses */
+#define CFG_DTT_MAX_TEMP		70
+#define CFG_DTT_LOW_TEMP		-30
+#define CFG_DTT_HYSTERESIS		3
+
+
+/*******************************************************************************
  * Commands
  ******************************************************************************/
 
@@ -161,6 +198,9 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
 
 
 /*******************************************************************************

[U-Boot-Users] [PATCH 05/10] [ARM] TQMA31: add support for I2C, I2C temperature sensor and I2C-EEPROM

[Jean-Christophe PLAGNIOL-VILLARD]

>  #if defined(CONFIG_DISPLAY_CPUINFO)
>  int print_cpuinfo (void)
>  {
> diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
> index 6f9306f..68d2720 100644
> --- a/drivers/i2c/mxc_i2c.c
> +++ b/drivers/i2c/mxc_i2c.c
> @@ -209,4 +209,17 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
>  	return 0;
>  }
>  
> +int i2c_get_bus_speed(void)
> +{
> +	return -1;
> +}
> +
> +int i2c_set_bus_speed (unsigned int speed)
> +{
> +	if (speed != CFG_I2C_SPEED)
> +		return -1;
> +
> +	return 0;
> +}
why do you refuse to change the i2c bus speed?
> +
>  #endif /* CONFIG_HARD_I2C */
> diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
> index ea15108..c0e516f 100644
> --- a/include/asm-arm/arch-mx31/mx31-regs.h
> +++ b/include/asm-arm/arch-mx31/mx31-regs.h
> @@ -168,6 +168,9 @@
>  
>  extern u32 mx31_get_ipg_clk(void);
>  extern void mx31_gpio_mux(unsigned long mode);
> +extern void mx31_pad_ctl (u32 field, u32 val);
>  
>  #endif /* __ASM_ARCH_MX31_H */
> diff --git a/include/configs/TQMA31.h b/include/configs/TQMA31.h
> index 255355d..f96fd74 100644
> --- a/include/configs/TQMA31.h
> +++ b/include/configs/TQMA31.h
> @@ -154,6 +154,43 @@
>  
>  
>  /*******************************************************************************
> + * I2C
> + ******************************************************************************/
> +
> +/* Use the processor internal controller */
> +#define CONFIG_HARD_I2C
> +#define CONFIG_I2C_MXC
> +
> +/* Configure I2C1 */
> +#define CFG_I2C_MX31_PORT1
> +
> +#define CFG_I2C_SPEED 			100000
please use tab instead of whitespace
> +#define CFG_I2C_SLAVE 			0
please use tab instead of whitespace
> +
> +/* Don't probe these addrs */
> +#define CFG_I2C_NOPROBES		{0x00}
> +
Best Regards,
J.

[U-Boot-Users] [PATCH 05/10] [ARM] TQMA31: add support for I2C, I2C temperature sensor and I2C-EEPROM

[Jens Gehrlein]

Jean-Christophe PLAGNIOL-VILLARD schrieb:
>>  #if defined(CONFIG_DISPLAY_CPUINFO)
>>  int print_cpuinfo (void)
>>  {
>> diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
>> index 6f9306f..68d2720 100644
>> --- a/drivers/i2c/mxc_i2c.c
>> +++ b/drivers/i2c/mxc_i2c.c
>> @@ -209,4 +209,17 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
>>  	return 0;
>>  }
>>  
>> +int i2c_get_bus_speed(void)
>> +{
>> +	return -1;
>> +}
>> +
>> +int i2c_set_bus_speed (unsigned int speed)
>> +{
>> +	if (speed != CFG_I2C_SPEED)
>> +		return -1;
>> +
>> +	return 0;
>> +}
> why do you refuse to change the i2c bus speed?

Those two routines were missing at all before I started the board BSP. I 
just added them to compile the U-Boot successfully. Or did I miss 
something (e.g. overlaying-of-functions-technique or so)?
I copied the source code from another driver (can't remember from 
where). It's no real excuse, I know.
So, shall I change it or can I leave it for now?


>> +#define CFG_I2C_SPEED 			100000
> please use tab instead of whitespace
>> +#define CFG_I2C_SLAVE 			0
> please use tab instead of whitespace

Will do. Thank you.


Kind regards,
Jens

[U-Boot-Users] [PATCH 06/10] [ARM] TQMA31: add support for SPI and SPI device MC13783-RTC

[Jens Gehrlein]

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

 board/tqc/tqma31/tqma31.c             |   13 +++++++++++++
 include/asm-arm/arch-mx31/mx31-regs.h |   12 ++++++++++++
 include/configs/TQMA31.h              |   20 ++++++++++++++++++++
 3 files changed, 45 insertions(+), 0 deletions(-)


diff --git a/board/tqc/tqma31/tqma31.c b/board/tqc/tqma31/tqma31.c
index 0c67af3..c704c41 100644
--- a/board/tqc/tqma31/tqma31.c
+++ b/board/tqc/tqma31/tqma31.c
@@ -55,6 +55,19 @@ static void setup_iomux (void)
 	mx31_gpio_mux (MUX_I2C_DAT__I2C1_SDA);
 	mx31_pad_ctl (PAD_CTL_I2C_CLK, PAD_CTL_IPP_ODE_OD);
 	mx31_pad_ctl (PAD_CTL_I2C_DAT, PAD_CTL_IPP_ODE_OD);
+
+	/* Pins for SPI2 */
+	mx31_gpio_mux (MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux (MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux (MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux (MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_pad_ctl (PAD_CTL_CSPI2_SS0, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_SS1, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_SS2, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_SCLK, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_SPI_RDY, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_MISO, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_MOSI, 0);
 }
 
 int dram_init (void)
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index c0e516f..4d661e8 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -183,6 +183,11 @@
 #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
 #define MUX_CSPI2_MISO__I2C2_SDA ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
 
+#define MUX_CSPI2_MOSI__CSPI2_MOSI ((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI)
+#define MUX_CSPI2_MISO__CSPI2_MISO ((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO)
+#define MUX_CSPI2_SS0__CSPI2_SS0_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0)
+#define MUX_CSPI2_SCLK__CSPI2_CLK  ((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK)
+
 #define MUX_I2C_CLK__I2C1_SCL	((MUX_CTL_FUNC << 8) | MUX_CTL_I2C_CLK)
 #define MUX_I2C_DAT__I2C1_SDA	((MUX_CTL_FUNC << 8) | MUX_CTL_I2C_DAT)
 
@@ -208,6 +213,13 @@
 #define	PAD_CTL_IO1_SHIFT		0
 #define	PAD_CTL_IO2_SHIFT		10
 #define	PAD_CTL_IO3_SHIFT		20
+#define PAD_CTL_CSPI2_SS2		((0x1F4 << 8) | PAD_CTL_IO3_SHIFT)
+#define PAD_CTL_CSPI2_SCLK		((0x1F4 << 8) | PAD_CTL_IO2_SHIFT)
+#define PAD_CTL_CSPI2_SPI_RDY		((0x1F4 << 8) | PAD_CTL_IO1_SHIFT)
+#define PAD_CTL_CSPI2_MISO		((0x1F8 << 8) | PAD_CTL_IO3_SHIFT)
+#define PAD_CTL_CSPI2_SS0		((0x1F8 << 8) | PAD_CTL_IO2_SHIFT)
+#define PAD_CTL_CSPI2_SS1		((0x1F8 << 8) | PAD_CTL_IO1_SHIFT)
+#define PAD_CTL_CSPI2_MOSI		((0x1FC << 8) | PAD_CTL_IO1_SHIFT)
 #define PAD_CTL_I2C_CLK			((0x21C << 8) | PAD_CTL_IO2_SHIFT)
 #define PAD_CTL_I2C_DAT			((0x21C << 8) | PAD_CTL_IO1_SHIFT)
 
diff --git a/include/configs/TQMA31.h b/include/configs/TQMA31.h
index f96fd74..ac81a32 100644
--- a/include/configs/TQMA31.h
+++ b/include/configs/TQMA31.h
@@ -191,6 +191,24 @@
 
 
 /*******************************************************************************
+ * SPI
+ ******************************************************************************/
+
+/* Use the processor internal controller */
+#define CONFIG_HARD_SPI			1
+#define CONFIG_MXC_SPI			1
+
+/* 0=CSPI1, 1=CSPI2, 2=CSPI3 */
+#define CONFIG_DEFAULT_SPI_BUS		1
+
+/* SCLK polarity: high; chipselect: active high */
+#define CONFIG_DEFAULT_SPI_MODE		(SPI_MODE_2 | SPI_CS_HIGH)
+
+/* Add PMIC RTC driver */
+#define CONFIG_RTC_MC13783		1
+
+
+/*******************************************************************************
  * Commands
  ******************************************************************************/
 
@@ -201,6 +219,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
 
 
 /*******************************************************************************

[U-Boot-Users] [PATCH 07/10] [ARM] TQMA31: adjust voltage regulators in PMIC MC13738

[Jens Gehrlein]

VRFDIG: 1.875 V -> 1.8 V
VGEN:   1.5 V -> 1.8 V
VDIG:   1.5 V -> 1.3 V
Unused PMIC switchers and regulators are disabled

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

 board/tqc/tqma31/tqma31.c |  142 +++++++++++++++++++++++++++++++++++++++++++++
 include/configs/TQMA31.h  |    2 +
 2 files changed, 144 insertions(+), 0 deletions(-)


diff --git a/board/tqc/tqma31/tqma31.c b/board/tqc/tqma31/tqma31.c
index c704c41..abb8db0 100644
--- a/board/tqc/tqma31/tqma31.c
+++ b/board/tqc/tqma31/tqma31.c
@@ -22,6 +22,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <spi.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
 
@@ -70,6 +71,132 @@ static void setup_iomux (void)
 	mx31_pad_ctl (PAD_CTL_CSPI2_MOSI, 0);
 }
 
+static int adjust_voltages (void)
+{
+	u32 reg;
+	u32 val;
+	static struct spi_slave *slave = NULL;
+
+	slave = spi_setup_slave(1, 0, 1000000,
+		SPI_MODE_2 | SPI_CS_HIGH);
+	if (!slave)
+		return -1;
+
+	if (spi_claim_bus(slave))
+		return -1;
+
+	/* Set PMIC arbitration switchers */
+	val = 0x000020;
+	reg = 0x14000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	/* Set PMIC regulator enable to 0x0 */
+	val = 0x000000;
+	reg = 0x20000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	/*
+	 * Set PMIC regulator setting 0
+	 *	VRFDIG = 1,8V / reset value = 1,875V
+	 *	VGEN   = 1,8V / reset value = 1,5V
+	 *	VDIG   = 1,3V / reset value = 1,5V
+	 */
+	val = 0x63cdc;
+	reg = 0x3c000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	/*
+	 * Set PMIC regulator mode 0 to 0x24924
+	 *	VAUDIO	= on
+	 *	VIOH	= off
+	 *	VIOLO	= on
+	 *	VDIG	= on
+	 *	VGEN	= on
+	 *	VRFDIG	= on
+	 *	VRFREF	= on
+	 *	VRFCP	= on
+	 */
+	val = 0x249241;
+	reg = 0x40000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	/*
+	 * Set PMIC regulator mode 1 to 0x0
+	 *	VSIM	= off
+	 *	VESIM	= off
+	 *	VCAM	= off
+	 *	VRFBG	= off
+	 *	VVIB	= off
+	 *	VRF1	= off
+	 *	VRF2	= off
+	 *	VMMC1	= off
+	 *	VMMC2	= off
+	 */
+	val = 0x0;
+	reg = 0x42000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	/*
+	 * FIXME: switcher settings 0 and 1.
+	 * Kernel hangs when unpacking itself.
+	 * Workaround:
+	 * Up to now CPU can operate at maximum allowed voltage 1.6 V.
+	 */
+	/*
+	 * Set PMIC switcher setting 0
+	 *	SW1A     = 1,2V / reset value = 1,6V
+	 *	SW1ADVS  = 1,6V / reset value = 1,6V
+	 *	SW1ASTBY = 1,2V / reset value = 1,6V
+	 */
+	/*
+	val = 0xc70c;
+	reg = 0x30000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+	*/
+
+	/*
+	 * Set PMIC switcher setting 1
+	 *	SW1A     = 1,2V / reset value = 1,6V
+	 *	SW1ADVS  = 1,6V / reset value = 1,6V
+	 *	SW1ASTBY = 1,2V / reset value = 1,6V
+	 */
+	/*
+	val = 0xc70c;
+	reg = 0x32000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+	*/
+
+	/*
+	 * Set PMIC switcher setting 5
+	 *	SW5 = 5V
+	 *	SW5 = off
+	 */
+	val = 0x021605;
+	reg = 0x3A000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	spi_release_bus(slave);
+	spi_free_slave(slave);
+
+	return 0;
+}
+
 int dram_init (void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
@@ -112,3 +239,18 @@ int checkboard (void)
 	printf ("Board: TQMA31\n");
 	return 0;
 }
+
+int board_late_init(void)
+{
+	/*
+	 * Must call this function in late init stage, because the SPI driver,
+	 * required by this function, uses malloc(). The malloc space has not
+	 * been setup in the board_init() stage.
+	 */
+	if (adjust_voltages ()) {
+		printf ("Adjusting voltages failed!\n");
+		return -1;
+	}
+	return 0;
+}
+
diff --git a/include/configs/TQMA31.h b/include/configs/TQMA31.h
index ac81a32..a174940 100644
--- a/include/configs/TQMA31.h
+++ b/include/configs/TQMA31.h
@@ -299,6 +299,8 @@
  * Miscellaneous
  ******************************************************************************/
 
+#define BOARD_LATE_INIT
+
 /* Total available space for malloc in bytes */
 #define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
 

[U-Boot-Users] [PATCH 07/10] [ARM] TQMA31: adjust voltage regulators in PMIC MC13738

[Magnus Lilja]

Hi,

Jens Gehrlein wrote:
> +static int adjust_voltages (void)
> +{
> +	u32 reg;
> +	u32 val;
> +	static struct spi_slave *slave = NULL;
> +
> +	slave = spi_setup_slave(1, 0, 1000000,
> +		SPI_MODE_2 | SPI_CS_HIGH);
> +	if (!slave)
> +		return -1;
> +
> +	if (spi_claim_bus(slave))
> +		return -1;
> +
> +	/* Set PMIC arbitration switchers */
> +	val = 0x000020;
> +	reg = 0x14000000 | val | 0x80000000;

It seems like it's time to create a MC13783 header file containing some helper macros and symbolic names to the 13783's registers so we can write:
reg = MC13783_READ_CMD(MC_REG_FOO);
...
val = something_symbolic | something_symbolic2;
reg = MC13783_WRITE_CMD(MC_REG_FOO, val);
...
etc..


Also, I'm pretty sure some other i.MX31 boards could benefit from changing some voltages in U-boot so perhaps we could have a mc13783-reg.c (-reg as in regulators) file containing stuff like mc13783_set_regulator(MC_VRFDIG, VRFDIG_1V8)?


> +	/*
> +	 * FIXME: switcher settings 0 and 1.
> +	 * Kernel hangs when unpacking itself.
> +	 * Workaround:
> +	 * Up to now CPU can operate at maximum allowed voltage 1.6 V.
> +	 */

I suppose you know that 1.6V is only needed if the CPU is clocked at 532MHz, if it's clocked at 399MHz it can be supplied with 1.2V.


Regards, Magnus

[U-Boot-Users] [PATCH 07/10] [ARM] TQMA31: adjust voltage regulators in PMIC MC13738

[Jens Gehrlein]

Hi Magnus,

Magnus Lilja schrieb:
> Hi,
> 
> Jens Gehrlein wrote:
>> +static int adjust_voltages (void)
>> +{
>> +	u32 reg;
>> +	u32 val;
>> +	static struct spi_slave *slave = NULL;
>> +
>> +	slave = spi_setup_slave(1, 0, 1000000,
>> +		SPI_MODE_2 | SPI_CS_HIGH);
>> +	if (!slave)
>> +		return -1;
>> +
>> +	if (spi_claim_bus(slave))
>> +		return -1;
>> +
>> +	/* Set PMIC arbitration switchers */
>> +	val = 0x000020;
>> +	reg = 0x14000000 | val | 0x80000000;
> 
> It seems like it's time to create a MC13783 header file containing some helper macros and symbolic names to the 13783's registers so we can write:
> reg = MC13783_READ_CMD(MC_REG_FOO);
> ...
> val = something_symbolic | something_symbolic2;
> reg = MC13783_WRITE_CMD(MC_REG_FOO, val);
> ...
> etc..
> 
> 
> Also, I'm pretty sure some other i.MX31 boards could benefit from changing some voltages in U-boot so perhaps we could have a mc13783-reg.c (-reg as in regulators) file containing stuff like mc13783_set_regulator(MC_VRFDIG, VRFDIG_1V8)?

Basically, I agree. But would you accept the current patch for now? The 
new routines and macros later could be implemented later.

Kind regards,
Jens

[U-Boot-Users] [PATCH 07/10] [ARM] TQMA31: adjust voltage regulators in PMIC MC13738

[Magnus Lilja]

Hi Jens,

On Tue, Jul 8, 2008 at 10:55 AM, Jens Gehrlein <sew_s@tqs.de> wrote:
> Hi Magnus,
>
> Magnus Lilja schrieb:
>>
>> Hi,
>>
>> Jens Gehrlein wrote:
>>>
>>> +static int adjust_voltages (void)
>>> +{
>>> +       u32 reg;
>>> +       u32 val;
>>> +       static struct spi_slave *slave = NULL;
>>> +
>>> +       slave = spi_setup_slave(1, 0, 1000000,
>>> +               SPI_MODE_2 | SPI_CS_HIGH);
>>> +       if (!slave)
>>> +               return -1;
>>> +
>>> +       if (spi_claim_bus(slave))
>>> +               return -1;
>>> +
>>> +       /* Set PMIC arbitration switchers */
>>> +       val = 0x000020;
>>> +       reg = 0x14000000 | val | 0x80000000;
>>
>> It seems like it's time to create a MC13783 header file containing some
>> helper macros and symbolic names to the 13783's registers so we can write:
>> reg = MC13783_READ_CMD(MC_REG_FOO);
>> ...
>> val = something_symbolic | something_symbolic2;
>> reg = MC13783_WRITE_CMD(MC_REG_FOO, val);
>> ...
>> etc..
>>
>>
>> Also, I'm pretty sure some other i.MX31 boards could benefit from changing
>> some voltages in U-boot so perhaps we could have a mc13783-reg.c (-reg as in
>> regulators) file containing stuff like mc13783_set_regulator(MC_VRFDIG,
>> VRFDIG_1V8)?
>
> Basically, I agree. But would you accept the current patch for now? The new
> routines and macros later could be implemented later.

I don't think it's up to me to ACK or NAK this, but I can accept the
current patch.


Regards, Magnus Lilja

[U-Boot-Users] [PATCH 07/10] [ARM] TQMA31: adjust voltage regulators in PMIC MC13738

[Detlev Zundel]

Hi Magnus and Jens,

>> Basically, I agree. But would you accept the current patch for now? The new
>> routines and macros later could be implemented later.
>
> I don't think it's up to me to ACK or NAK this, but I can accept the
> current patch.

Yes, this decision is up to the custodian.  But lets be honest here, we
all know what "we can implement this later" means.  

We really need to fix problems as they arise.  Especially in this case I
don't think that it is such a significant effort to fix it now.  Fixing
it later will only need even more effort.  

Usually this effort(t-[detection time]) is an exponential function and I
am not kidding on this.

Cheers
  Detlev


-- 
Among the  -) the .-) is king
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de

[U-Boot-Users] [PATCH 07/10] [ARM] TQMA31: adjust voltage regulators in PMIC MC13738

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:11 Wed 09 Jul     , Detlev Zundel wrote:
> Hi Magnus and Jens,
> 
> >> Basically, I agree. But would you accept the current patch for now? The new
> >> routines and macros later could be implemented later.
> >
> > I don't think it's up to me to ACK or NAK this, but I can accept the
> > current patch.
> 
> Yes, this decision is up to the custodian.  But lets be honest here, we
> all know what "we can implement this later" means.  
> 
> We really need to fix problems as they arise.  Especially in this case I
> don't think that it is such a significant effort to fix it now.  Fixing
> it later will only need even more effort.  
> 
> Usually this effort(t-[detection time]) is an exponential function and I
> am not kidding on this.

I fully agree with you.

We need to fix this and not use a workaround which will became the
status quo.

Best Regards,
J.

[U-Boot-Users] [PATCH 08/10] [ARM] TQMA31: adjust pad property of IPU pin FPSHIFT for the display

[Jens Gehrlein]

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

 board/tqc/tqma31/tqma31.c             |    7 +++++++
 include/asm-arm/arch-mx31/mx31-regs.h |    1 +
 2 files changed, 8 insertions(+), 0 deletions(-)


diff --git a/board/tqc/tqma31/tqma31.c b/board/tqc/tqma31/tqma31.c
index abb8db0..dd2bb0a 100644
--- a/board/tqc/tqma31/tqma31.c
+++ b/board/tqc/tqma31/tqma31.c
@@ -69,6 +69,13 @@ static void setup_iomux (void)
 	mx31_pad_ctl (PAD_CTL_CSPI2_SPI_RDY, 0);
 	mx31_pad_ctl (PAD_CTL_CSPI2_MISO, 0);
 	mx31_pad_ctl (PAD_CTL_CSPI2_MOSI, 0);
+
+	/* Pins for IPU */
+	mx31_pad_ctl (PAD_CTL_FPSHIFT, PAD_CTL_IPP_PUE_PULL \
+					| PAD_CTL_IPP_PUS_100K_DN \
+					| PAD_CTL_IPP_HYS_STD \
+					| PAD_CTL_IPP_ODE_STD \
+					| PAD_CTL_IPP_SRE_FAST);
 }
 
 static int adjust_voltages (void)
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index 4d661e8..407b2c6 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -213,6 +213,7 @@
 #define	PAD_CTL_IO1_SHIFT		0
 #define	PAD_CTL_IO2_SHIFT		10
 #define	PAD_CTL_IO3_SHIFT		20
+#define PAD_CTL_FPSHIFT			((0x184 << 8) | PAD_CTL_IO1_SHIFT)
 #define PAD_CTL_CSPI2_SS2		((0x1F4 << 8) | PAD_CTL_IO3_SHIFT)
 #define PAD_CTL_CSPI2_SCLK		((0x1F4 << 8) | PAD_CTL_IO2_SHIFT)
 #define PAD_CTL_CSPI2_SPI_RDY		((0x1F4 << 8) | PAD_CTL_IO1_SHIFT)

[U-Boot-Users] [PATCH 09/10] [ARM] TQMA31: add FPGA configuration flash

[Jens Gehrlein]

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

 board/tqc/tqma31/tqma31.c             |    6 ++++++
 include/asm-arm/arch-mx31/mx31-regs.h |    1 +
 include/configs/TQMA31.h              |    7 +++++--
 3 files changed, 12 insertions(+), 2 deletions(-)


diff --git a/board/tqc/tqma31/tqma31.c b/board/tqc/tqma31/tqma31.c
index dd2bb0a..30584fe 100644
--- a/board/tqc/tqma31/tqma31.c
+++ b/board/tqc/tqma31/tqma31.c
@@ -36,6 +36,12 @@ static void setup_chipselects (void)
 	__REG (CSCR_L(0)) = CSCR_L_OEA_10 | CSCR_L_EBWA_3 | CSCR_L_EBWN_3 \
 		| CSCR_L_EBC_ONLY_WA | CSCR_L_DSZ_16_MUM0 | CSCR_L_CSEN;
 
+	/* FPGA configuration flash on CS1 */
+	__REG (CSCR_U(1)) = CSCR_U_CNC_3 | CSCR_U_WSC_13 | CSCR_U_EDC_4;
+	__REG (CSCR_A(1)) = CSCR_A_RWA_2 | CSCR_A_RWN_2 | CSCR_A_LBN_2_MUM0;
+	__REG (CSCR_L(1)) = CSCR_L_OEA_10 | CSCR_L_EBWA_3 | CSCR_L_EBWN_3 \
+		| CSCR_L_EBC_ONLY_WA | CSCR_L_DSZ_16_MUM0 | CSCR_L_CSEN;
+
 	/* Ethernet controller on CS4 */
 	__REG (CSCR_U(4)) = CSCR_U_CNC_1 | CSCR_U_WSC_22 | CSCR_U_EDC_4;
 	__REG (CSCR_A(4)) = CSCR_A_RWA_2 | CSCR_A_RWN_15;
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index 407b2c6..69d7614 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -84,6 +84,7 @@
 #define CSCR_U_WSC_9		0x00000900
 #define CSCR_U_WSC_12		0x00000C00
 #define CSCR_U_WSC_22		0x00001600
+#define CSCR_U_WSC_13		0x00000D00
 #define CSCR_U_EDC_4		0x00000004
 #define CSCR_U_EDC_13		0x0000000D
 
diff --git a/include/configs/TQMA31.h b/include/configs/TQMA31.h
index a174940..504cb57 100644
--- a/include/configs/TQMA31.h
+++ b/include/configs/TQMA31.h
@@ -89,18 +89,21 @@
 #define CFG_FLASH_BASE			CS0_BASE
 
 /* Max number of memory banks */
-#define CFG_MAX_FLASH_BANKS		4
+#define CFG_MAX_FLASH_BANKS		5
 
 /*
  * Bank start addresses.
  * 4 x 32 MiB is the maximum for user and U-Boot code. Please adapt the list
  * as well as CFG_MAX_FLASH_BANKS to your TQM. Also consider dual die chips
  * or single die chips, e.g. one dual die chip represents two banks.
+ * The fifth bank is a separate chip for the FPGA configuration. It's
+ * controlled by chipselect 1.
  */
 #define CFG_FLASH_BANKS_LIST		{CFG_FLASH_BASE, 		\
 					CFG_FLASH_BASE + 32*1024*1024,	\
 					CFG_FLASH_BASE + 64*1024*1024,	\
-					CFG_FLASH_BASE + 96*1024*1024}
+					CFG_FLASH_BASE + 96*1024*1024,  \
+					CS1_BASE}
 
 /* Max number of sectors on one chip */
 #define CFG_MAX_FLASH_SECT		259

[U-Boot-Users] [PATCH 09/10] [ARM] TQMA31: add FPGA configuration flash

[Jean-Christophe PLAGNIOL-VILLARD]

>  /*
>   * Bank start addresses.
>   * 4 x 32 MiB is the maximum for user and U-Boot code. Please adapt the list
>   * as well as CFG_MAX_FLASH_BANKS to your TQM. Also consider dual die chips
>   * or single die chips, e.g. one dual die chip represents two banks.
> + * The fifth bank is a separate chip for the FPGA configuration. It's
> + * controlled by chipselect 1.
>   */
same commnets as patch 04
>  #define CFG_FLASH_BANKS_LIST		{CFG_FLASH_BASE, 		\
>  					CFG_FLASH_BASE + 32*1024*1024,	\
>  					CFG_FLASH_BASE + 64*1024*1024,	\
> -					CFG_FLASH_BASE + 96*1024*1024}
> +					CFG_FLASH_BASE + 96*1024*1024,  \
> +					CS1_BASE}
>  
>  /* Max number of sectors on one chip */
>  #define CFG_MAX_FLASH_SECT		259
> 
Best Regards,
J.

[U-Boot-Users] [PATCH 10/10] [ARM] TQMA31: new kernel param. to pass the eth MAC addr to the Linux eth chip driver

[Jens Gehrlein]

Some Linux drivers like the smc911x driver, as used on TQMA31, rely on the MAC address
in the appropriate register, but U-Boot resets the controller after every transfer.
A patch for the Linux driver is necessary to extract the MAC address from the kernel
boot parameter line and set the MAC address register accordingly.
This patch adds the paramater "ethaddr" to the U-Boot default environment so that the
user cannot forget it.

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

 include/configs/TQMA31.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)


diff --git a/include/configs/TQMA31.h b/include/configs/TQMA31.h
index 504cb57..e9e5d78 100644
--- a/include/configs/TQMA31.h
+++ b/include/configs/TQMA31.h
@@ -275,6 +275,7 @@
 		"jtag=on "						\
 		"console=ttymxc0,115200\0"				\
 	"bootargs_nfs=setenv bootargs ${bootargs} "			\
+		"ethaddr=${ethaddr} "				        \
 		"root=/dev/nfs "					\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
 			"${netmask}:${hostname}:${netdev}:off "		\

[U-Boot-Users] [PATCH 10/10] [ARM] TQMA31: new kernel param. to pass the eth MAC addr to the Linux eth chip driver

[Jean-Christophe PLAGNIOL-VILLARD]

On 16:50 Fri 04 Jul     , Jens Gehrlein wrote:
> Some Linux drivers like the smc911x driver, as used on TQMA31, rely on the MAC address
> in the appropriate register, but U-Boot resets the controller after every transfer.
> A patch for the Linux driver is necessary to extract the MAC address from the kernel
> boot parameter line and set the MAC address register accordingly.
> This patch adds the paramater "ethaddr" to the U-Boot default environment so that the
> user cannot forget it.
> 
> Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
> ---
> 
>  include/configs/TQMA31.h |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> 
> diff --git a/include/configs/TQMA31.h b/include/configs/TQMA31.h
> index 504cb57..e9e5d78 100644
> --- a/include/configs/TQMA31.h
> +++ b/include/configs/TQMA31.h
> @@ -275,6 +275,7 @@
>  		"jtag=on "						\
>  		"console=ttymxc0,115200\0"				\
>  	"bootargs_nfs=setenv bootargs ${bootargs} "			\
> +		"ethaddr=${ethaddr} "				        \
why don't you use nwhwconf parameter?

Best Regards,
J.

[U-Boot-Users] [PATCH 10/10] [ARM] TQMA31: new kernel param. to pass the eth MAC addr to the Linux eth chip driver

[Jens Gehrlein]

Hi Jean-Christophe,

Jean-Christophe PLAGNIOL-VILLARD schrieb:

> why don't you use nwhwconf parameter?

Thank you for response.
I found some U-Boot examples how to pass this parameter. But were can I 
find Linux related information? nwhwconf is new to me. I have never 
heard before.
I use Kernel 2.6.22-6 from the LTIB for mx31ads.

Kind regards,
Jens

[U-Boot-Users] [PATCH 00/10] [ARM] TQMA31: new board

[Jens Gehrlein]

Jens Gehrlein schrieb:

> Who will pick up this patch series (if there are no complaints)? Peter?

Of course, we could put them into the TQ custodian tree.
Awkward, that I forgot this.

Kind regards,
Jens

[U-Boot-Users] [PATCH 00/10] [ARM] TQMA31: new board

[Peter Pearse]

 

> -----Original Message-----
> From: u-boot-users-bounces at lists.sourceforge.net 
> [mailto:u-boot-users-bounces at lists.sourceforge.net] On Behalf 
> Of Jens Gehrlein
> Sent: 04 July 2008 16:02
> To: u-boot-users at lists.sourceforge.net
> Subject: Re: [U-Boot-Users] [PATCH 00/10] [ARM] TQMA31: new board
> 
> Jens Gehrlein schrieb:
> 
> > Who will pick up this patch series (if there are no 
> complaints)? Peter?
> 
> Of course, we could put them into the TQ custodian tree.
> Awkward, that I forgot this.
> 

So I'm assuming I need take no u-boot-arm actions

Regards

Peter

[U-Boot-Users] [PATCH 00/10] [ARM] TQMA31: new board

[Wolfgang Denk]

In message <000001c8ddf5$222eaf30$3a4d010a@Emea.Arm.com> you wrote:
>  
> > Of course, we could put them into the TQ custodian tree.
> > Awkward, that I forgot this.
> 
> So I'm assuming I need take no u-boot-arm actions

But please do. It's ARM specific code, and needs to be reviewed and
confirmed by an independent ARM expert.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is surely a great calamity for  a  human  being  to  have  no  ob-
sessions.                                                - Robert Bly

[U-Boot-Users] [PATCH 00/10] [ARM] TQMA31: new board

[Wolfgang Denk]

In message <486E3B67.8030203@tqs.de> you wrote:
> Jens Gehrlein schrieb:
> 
> > Who will pick up this patch series (if there are no complaints)? Peter?
> 
> Of course, we could put them into the TQ custodian tree.
> Awkward, that I forgot this.

But it still has to go through the respective custodian.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
2000 pounds of chinese soup                               = 1 Won Ton

[U-Boot-Users] [PATCH 00/10] [ARM] TQMA31: new board

[Magnus Lilja]

Hi,

Jens Gehrlein skrev:
> Hi,
> 
> the following patches introduce the i.MX31 (ARM1136) based board TQMA31.
> Used toolchain was ELDK 4.1.
> 
> The first three patches fix some bugs in mxc/mx31 common parts. I compiled
> the im31_phycore, the imx31_litekit and the mx31ads U-Boots for this.
> But I don't have boards to test them.
> 
> Patch 04/10 cannot successfully be compiled without having Patch 03/10 applied.
> 
> Patch 03/10 has been on the mailing list in a similar form, but it seems that
> nobody picked it up. So I want give it a chance with my patch series.

Don't know why those patches weren't picked up, I think they were submitted before the merge window closed. Your patch doesn't fix the bug in mx31_gpio_mux() though.


Regards, Magnus