[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Jens Gehrlein]

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
---

Fixed two bugs:
a) added NFS mount option "rw" to default environment
b) added prefix $(obj) in front of .depend in Makefile. Thank you Magnus for catching that.


 MAINTAINERS                           |    4 
 MAKEALL                               |    1 
 Makefile                              |    3 
 board/tqc/tqma31/Makefile             |   48 ++++
 board/tqc/tqma31/config.mk            |    2 
 board/tqc/tqma31/lowlevel_init.S      |  375 +++++++++++++++++++++++++++++++++
 board/tqc/tqma31/tqma31.c             |   95 ++++++++
 board/tqc/tqma31/u-boot.lds           |   72 ++++++
 include/asm-arm/arch-mx31/mx31-regs.h |   42 ++++
 include/configs/TQMA31.h              |  271 ++++++++++++++++++++++++
 10 files changed, 913 insertions(+), 0 deletions(-)
 create mode 100644 board/tqc/tqma31/Makefile
 create mode 100644 board/tqc/tqma31/config.mk
 create mode 100644 board/tqc/tqma31/lowlevel_init.S
 create mode 100644 board/tqc/tqma31/tqma31.c
 create mode 100644 board/tqc/tqma31/u-boot.lds
 create mode 100644 include/configs/TQMA31.h


diff --git a/MAINTAINERS b/MAINTAINERS
index a3d70b1..dff1757 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -591,6 +591,10 @@ Michael Schwingen <michael@schwingen.org>
 	actux3			xscale
 	actux4			xscale
 
+Jens Gehrlein <sew_s@tqs.de>
+
+	TQMA31			i.MX31
+
 #########################################################################
 # x86 Systems:								#
 #									#
diff --git a/MAKEALL b/MAKEALL
index 32caab7..4e442c5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -524,6 +524,7 @@ LIST_ARM11="		\
 	imx31_litekit	\
 	imx31_phycore	\
 	mx31ads		\
+	TQMA31		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 8bfc891..e3ade25 100644
--- a/Makefile
+++ b/Makefile
@@ -2664,6 +2664,9 @@ imx31_phycore_config	: unconfig
 mx31ads_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31
 
+TQMA31_config		: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 tqma31 tqc mx31
+
 #========================================================================
 # i386
 #========================================================================
diff --git a/board/tqc/tqma31/Makefile b/board/tqc/tqma31/Makefile
new file mode 100644
index 0000000..f7e17c8
--- /dev/null
+++ b/board/tqc/tqma31/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+# Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= tqma31.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/tqc/tqma31/config.mk b/board/tqc/tqma31/config.mk
new file mode 100644
index 0000000..19df69e
--- /dev/null
+++ b/board/tqc/tqma31/config.mk
@@ -0,0 +1,2 @@
+TEXT_BASE = 0x8ff00000
+
diff --git a/board/tqc/tqma31/lowlevel_init.S b/board/tqc/tqma31/lowlevel_init.S
new file mode 100644
index 0000000..50db3a1
--- /dev/null
+++ b/board/tqc/tqma31/lowlevel_init.S
@@ -0,0 +1,375 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ * Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+#include <config.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ */
+.macro init_aips
+
+	/* Setup the Peripheral Port Remap register inside the core */
+	ldr r0, =0x40000015        /* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
+
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x77777777
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+	ldr r0, =0x53F00000
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+
+	ldr r0, =0x53F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+.endm /* init_aips */
+
+
+/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+	ldr r0, =0x43F04000
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+	ldr r1, =0x00302154
+	str r1, [r0, #0x000]        /* for S0 */
+	str r1, [r0, #0x100]        /* for S1 */
+	str r1, [r0, #0x200]        /* for S2 */
+	str r1, [r0, #0x300]        /* for S3 */
+	str r1, [r0, #0x400]        /* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =0x10
+	str r1, [r0, #0x010]        /* for S0 */
+	str r1, [r0, #0x110]        /* for S1 */
+	str r1, [r0, #0x210]        /* for S2 */
+	str r1, [r0, #0x310]        /* for S3 */
+	str r1, [r0, #0x410]        /* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =0x0
+	str r1, [r0, #0x800]        /* for M0 */
+	str r1, [r0, #0x900]        /* for M1 */
+	str r1, [r0, #0xA00]        /* for M2 */
+	str r1, [r0, #0xB00]        /* for M3 */
+	str r1, [r0, #0xC00]        /* for M4 */
+	str r1, [r0, #0xD00]        /* for M5 */
+.endm /* init_max */
+
+
+/* RedBoot: M3IF setup */
+.macro init_m3if
+	/* Configure M3IF registers */
+	ldr r1, =0xB8003000
+	/*
+	* M3IF Control Register (M3IFCTL)
+	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
+	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
+	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
+	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
+	*						------------
+	*						  0x00000040
+	*/
+	ldr r0, =0x00000040
+	str r0, [r1]  /* M3IF control reg */
+.endm /* init_m3if */
+
+
+/* RedBoot: To support 133MHz DDR */
+.macro  init_drive_strength
+	/*
+	 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+	 * in SW_PAD_CTL registers
+	 */
+
+	/* SDCLK */
+	ldr r1, =0x43FAC200
+	ldr r0, [r1, #0x6C]
+	bic r0, r0, #(1 << 12)
+	str r0, [r1, #0x6C]
+
+	/* CAS */
+	ldr r0, [r1, #0x70]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x70]
+
+	/* RAS */
+	ldr r0, [r1, #0x74]
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x74]
+
+	/* CS2 (CSD0) */
+	ldr r0, [r1, #0x7C]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x7C]
+
+	/* DQM3 */
+	ldr r0, [r1, #0x84]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x84]
+
+	/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+	ldr r2, =22	/* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+	ldr r0, [r1, #0x88]
+	bic r0, r0, #(1 << 22)
+	bic r0, r0, #(1 << 12)
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x88]
+	add r1, r1, #4
+	subs r2, r2, #0x1
+	bne pad_loop
+.endm /* init_drive_strength */
+
+
+/* initialize PLL */
+.macro init_pll
+	/*
+	 * Switch on Display Interface because of the change of the clock
+	 * divider. According to the description of PDR0[HSP_PODF] in the
+	 * processor reference manual the CCM waits for an ackn. of the IPU.
+	 */
+	REG	IPU_CONF, IPU_CONF_DI_EN
+
+	/* Clock Control Module: */
+	REG	CCM_CCMR, 0x074B0BF5				/* Use CKIH, MCU PLL off */
+	DELAY	0x40000
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE			/* MCU PLL on */
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS	/* Switch to MCU PLL */
+
+#if defined CONFIG_MX31_CPU_399_MHZ
+	/* Platform clocks */
+	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff)	/* camera sensor interface */		\
+			| PDR0_PER_PODF(6-1)	/* periph. if derived from USB clock */ \
+			| PDR0_HSP_PODF(3-1)	/* IPU 133 MHz */                       \
+			| PDR0_NFC_PODF(7-1)	/* NAND FC 19 MHz */                    \
+			| PDR0_IPG_PODF(2-1)	/* peripherals 66.5 MHz */              \
+			| PDR0_MAX_PODF(3-1)	/* AHB 133 MHz */                       \
+			| PDR0_MCU_PODF(1-1)	/* core 399 MHz */
+	/* MCU PLL */
+	REG	CCM_MPCTL, PLL_PD(1-1) | PLL_MFD(52-1) | PLL_MFI(7) | PLL_MFN(35)
+#elif defined CONFIG_MX31_CPU_532_MHZ
+	/* Platform clocks */
+	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff)	/* camera sensor interface */		\
+			| PDR0_PER_PODF(8-1)	/* periph. if derived from USB clock */	\
+			| PDR0_HSP_PODF(4-1)	/* IPU 133 MHz */                      	\
+			| PDR0_NFC_PODF(7-1)	/* NAND FC 19 MHz */                   	\
+			| PDR0_IPG_PODF(2-1)	/* peripherals 66.5 MHz */             	\
+			| PDR0_MAX_PODF(4-1)	/* AHB 133 MHz */                      	\
+			| PDR0_MCU_PODF(1-1)	/* core 532 MHz */
+	/* MCU PLL */
+	REG	CCM_MPCTL, PLL_PD(1-1) | PLL_MFD(52-1) | PLL_MFI(10) | PLL_MFN(12)
+#else
+#error Please define CPU core frequency (CONFIG_CPU_399_MHZ or CONFIG_CPU_532_MHZ)!
+#endif /* CONFIG_CPU_xxx_MHZ */
+
+	/* Serial PLL. Default: 1, 4, 12, 1 */
+	REG	CCM_SPCTL, PLL_PD(2-1) | PLL_MFD(5-1) | PLL_MFI(12) | PLL_MFN(1)
+.endm /* init_sdram */
+
+
+/* setup SDRAM on CSD0 */
+.macro init_sdram
+	/*
+	 * Enhanced SDRAM Miscellaneous Register
+	 *	Latency Hiding Enable
+	 *	LPDDR delay line measure unit is enabled
+	 *	LPDDR Delay Line is not reset
+	 *	Enable Mobile DDR SDRAM operation
+	 *	Soft Reset is disabled
+	 */
+	REG	ESDMISC, 0x00000004
+
+	/*
+	 * Enhanced SDRAM Configuration Register 0
+	 *	tXP 4 clock delay before new COMMAND issued to LPDDR
+	 *	tWTR tLPDDR WRITE to READ Command Delay = 2 clock
+	 *	tRP SDRAM Row Precharge Delay = 3 clock
+	 *	tMRD?SDRAM Load Mode Register to ACTIVE Command = 3 clock
+	 *	tWR SDRAM WRITE to PRECHARGE Command = 3 clock
+	 *	tRAS SDRAM ACTIVE to PRECHARGE Command = 6 clock
+	 *	tRRD ACTIVE Bank A to ACTIVE Bank B Command = 2 clock
+	 *	tCAS CAS Latency = 3 clock
+	 *	tRCD SDRAM Row to Column Delay = 3 clock
+	 *	tRC SDRAM Row Cycle Delay = 13 clocks
+	 */
+	REG	ESDCFG0, 0x006ac73c
+
+	/*
+	 * Enhanced SDRAM Control Register 0
+	 *	Enhanced SDRAM Controller Enable = 1
+	 *	SDRAM Controller Operating Mode = 001 Precharge Command
+	 *	Supervisor Protect = 0 User mode accesses are allowed to this
+	 *		chip select region
+	 *	ROW Row Address Width. = 011 14 Row Addresses
+	 *	COL Column Address Width = 01 9 Col Addresses
+	 *	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
+	 *		aligned to D[31:16]
+	 *	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
+	 *		(bit field reset value)
+	 *	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
+	 *	FP Full Page = 0 0 Burst Length of the external memory device
+	 *		is not set to Full Page
+	 *	BL Burst Length = 0
+	 *	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
+	 */
+	REG	ESDCTL0, 0x92200000
+	REG	0x80000f00, 0x12344321
+
+
+  	/*
+  	 * Enhanced SDRAM Control Register 0
+	 *	Enhanced SDRAM Controller Enable = 1
+	 *	SDRAM Controller Operating Mode = 010 Auto-Refresh Command
+	 *	Supervisor Protect = 0 User mode accesses are allowed to this
+	 *		chip select region
+	 *	ROW Row Address Width. = 011 14 Row Addresses
+	 *	COL Column Address Width = 01 9 Col Addresses
+	 *	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
+	 *		aligned to D[31:16]
+	 *	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
+	 *		(bit field reset value)
+	 *	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
+	 *	FP Full Page = 0 0 Burst Length of the external memory device
+	 *		is not set to Full Page
+	 *	BL Burst Length = 0
+	 *	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
+	 */
+	REG	ESDCTL0, 0xa2200000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+
+	/*
+	 * Enhanced SDRAM Control Register 0
+	 * 	Enhanced SDRAM Controller Enable = 1
+	 * 	SDRAM Controller Operating Mode = 001 Precharge Command
+	 * 	Supervisor Protect = 0 User mode accesses are allowed to this
+	 *		chip select region
+	 * 	ROW Row Address Width. = 011 14 Row Addresses
+	 * 	COL Column Address Width = 01 9 Col Addresses
+	 * 	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
+	 *		aligned to D[31:16]
+	 * 	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
+	 *		(bit field reset value)
+	 * 	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
+	 * 	FP Full Page = 0 0 Burst Length of the external memory device
+	 *		is not set to Full Page.
+	 * 	BL Burst Length = 0
+	 * 	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
+	 */
+	REG	ESDCTL0, 0xb2200000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+
+	/*
+	 * Enhanced SDRAM Control Register 0
+	 *	Enhanced SDRAM Controller Enable = 1
+	 *	SDRAM Controller Operating Mode = 000 Normal Read/Write
+	 *	Supervisor Protect = 0 User mode accesses are allowed to this
+	 *		chip select region
+	 *	ROW Row Address Width. = 011 14 Row Addresses
+	 *	COL Column Address Width = 10 10 Col Addresses
+	 *	DSIZ SDRAM Memory Data Width = 10 32-bit memory width
+	 *	SREFR SDRAM Refresh Rate  = 011 Refresh 7,81 ?s
+	 *	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
+	 *	FP Full Page = 0 0 Burst Length of the external memory device
+	 *		is not set to Full Page
+	 *	BL Burst Length = 8
+	 *	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
+	 */
+	REG	ESDCTL0, 0x83226080
+	REG	0x80000000, 0xDEADBEEF
+
+	/*
+	 * Enhanced SDRAM Miscellaneous Register
+	 *	Latency Hiding Enable
+	 *	LPDDR delay line measure unit is enabled
+	 *	LPDDR Delay Line is reset
+	 *	Enable Mobile DDR SDRAM operation
+	 *	Soft Reset is disabled
+	 */
+	REG	ESDMISC, 0x0000000c
+.endm /* init_sdram */
+
+
+.globl lowlevel_init
+lowlevel_init:
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	init_drive_strength
+
+	init_pll
+
+	init_sdram
+
+	mov pc, lr
diff --git a/board/tqc/tqma31/tqma31.c b/board/tqc/tqma31/tqma31.c
new file mode 100644
index 0000000..7cec8db
--- /dev/null
+++ b/board/tqc/tqma31/tqma31.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void setup_chipselects (void)
+{
+	/* NOR Flash on CS0 */
+	__REG (CSCR_U(0)) = CSCR_U_CNC_3 | CSCR_U_WSC_12 | CSCR_U_EDC_4;
+	__REG (CSCR_A(0)) = CSCR_A_RWA_2 | CSCR_A_RWN_2 | CSCR_A_LBN_2_MUM0;
+	__REG (CSCR_L(0)) = CSCR_L_OEA_10 | CSCR_L_EBWA_3 | CSCR_L_EBWN_3 \
+		| CSCR_L_EBC_ONLY_WA | CSCR_L_DSZ_16_MUM0 | CSCR_L_CSEN;
+
+	/* Ethernet controller on CS4 */
+	__REG (CSCR_U(4)) = CSCR_U_CNC_1 | CSCR_U_WSC_22 | CSCR_U_EDC_4;
+	__REG (CSCR_A(4)) = CSCR_A_RWA_2 | CSCR_A_RWN_15;
+	__REG (CSCR_L(4)) = CSCR_L_OEA_2 | CSCR_L_OEN_15 | CSCR_L_CSN_15 \
+		| CSCR_L_DSZ_16_MUM0 | CSCR_L_CSEN;
+}
+
+static void setup_iomux (void)
+{
+	/* Pins for UART1 */
+	mx31_gpio_mux (MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux (MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux (MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux (MUX_CTS1__UART1_CTS_B);
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init (void)
+{
+	/* WEIM burst clock runs all the time */
+	__REG (WCR) = WCR_BCM_1;
+
+	setup_chipselects ();
+	setup_iomux ();
+
+	/*
+	 * FIXME:
+	 * Replace machine type ID by symbolic define MACH_TYPE_TQMA31 as soon
+	 * as updated file mach-types.h is available in U-Boot tree.
+	 * Machine type ID 1810 for TQMA31 has been registered on 2008-06-25.
+	 */
+	/* Machine type ID for ARM linux */
+	gd->bd->bi_arch_number = 1810;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = 0x80000100;
+
+	/*
+	 * Tell other U-Boot entities: relocation done. For instance, needed
+	 * to enable command line history.
+	 */
+	gd->flags |= GD_FLG_RELOC;
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf ("Board: TQMA31\n");
+	return 0;
+}
diff --git a/board/tqc/tqma31/u-boot.lds b/board/tqc/tqma31/u-boot.lds
new file mode 100644
index 0000000..6b1c06a
--- /dev/null
+++ b/board/tqc/tqma31/u-boot.lds
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+	  cpu/arm1136/start.o		(.text)
+	  board/tqc/tqma31/libtqma31.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/environment.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index abe61f0..ea15108 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -61,11 +61,53 @@
 #define PLL_MFI(x)		(((x) & 0xf) << 10)
 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
 
+#define ESDCTL_BASE	0xB8001000
+#define ESDCTL0		(ESDCTL_BASE + 0x00)
+#define ESDCFG0		(ESDCTL_BASE + 0x04)
+#define ESDCTL1		(ESDCTL_BASE + 0x08)
+#define ESDCFG1		(ESDCTL_BASE + 0x0C)
+#define ESDMISC		(ESDCTL_BASE + 0x10)
+#define ESDCDLY1	(ESDCTL_BASE + 0x20)
+#define ESDCDLY2	(ESDCTL_BASE + 0x24)
+#define ESDCDLY3	(ESDCTL_BASE + 0x28)
+#define ESDCDLY4	(ESDCTL_BASE + 0x2C)
+#define ESDCDLY5	(ESDCTL_BASE + 0x30)
+#define ESDCDLYL	(ESDCTL_BASE + 0x34)
+
 #define WEIM_BASE	0xb8002000
 #define CSCR_U(x)	(WEIM_BASE + (x) * 0x10)
 #define CSCR_L(x)	(WEIM_BASE + 4 + (x) * 0x10)
 #define CSCR_A(x)	(WEIM_BASE + 8 + (x) * 0x10)
 
+#define CSCR_U_CNC_1		0x00004000
+#define CSCR_U_CNC_3		0x0000C000
+#define CSCR_U_WSC_9		0x00000900
+#define CSCR_U_WSC_12		0x00000C00
+#define CSCR_U_WSC_22		0x00001600
+#define CSCR_U_EDC_4		0x00000004
+#define CSCR_U_EDC_13		0x0000000D
+
+#define CSCR_L_OEA_2		0x20000000
+#define CSCR_L_OEA_4		0x40000000
+#define CSCR_L_OEA_10		0xA0000000
+#define CSCR_L_OEN_15		0x0F000000
+#define CSCR_L_EBWA_3		0x00300000
+#define CSCR_L_EBWN_3		0x00030000
+#define CSCR_L_CSA_4		0x00004000
+#define CSCR_L_CSN_15		0x000000F0
+#define CSCR_L_EBC_ONLY_WA	0x00000800
+#define CSCR_L_DSZ_16_MUM0	0x00000500
+#define CSCR_L_CSEN		0x00000001
+
+#define CSCR_A_RWA_2		0x00200000
+#define CSCR_A_RWN_2		0x00020000
+#define CSCR_A_RWN_15		0x000F0000
+#define CSCR_A_LBN_2_MUM0	0x00000800
+
+#define WCR			(WEIM_BASE + 0x60)
+#define WCR_BCM_1		0x00000004
+#define WCR_BCM_0		0x00000000
+
 #define IOMUXC_BASE	0x43FAC000
 #define IOMUXC_GPR	(IOMUXC_BASE + 0x8)
 #define IOMUXC_SW_MUX_CTL(x)	(IOMUXC_BASE + 0xc + (x) * 4)
diff --git a/include/configs/TQMA31.h b/include/configs/TQMA31.h
new file mode 100644
index 0000000..81b0a04
--- /dev/null
+++ b/include/configs/TQMA31.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
+ *
+ * Configuration settings for the TQMA31 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*******************************************************************************
+ * CPU
+ ******************************************************************************/
+
+#include <asm/arch/mx31-regs.h>
+
+/* This is an ARM1136 core */
+#define CONFIG_ARM1136			1
+
+/* in an i.MX31 processor */
+#define CONFIG_MX31			1
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+
+/*******************************************************************************
+ * Clocks
+ ******************************************************************************/
+
+ /* Frequency on CKIH in Hz. This is the MCU PLL input clock on TQMA31. */
+#define CONFIG_MX31_HCLK_FREQ		26000000
+
+/* Desired CPU core frequency (see PLL settings in lowlevel_init.S) */
+#define CONFIG_MX31_CPU_399_MHZ
+#undef CONFIG_MX31_CPU_532_MHZ
+
+/* Timer tick */
+#define CFG_HZ				32768
+
+/*
+ * Alternative clock input for MCU PLL.
+ * Unused on TQMA31, but must be defined to avoid compiler errors.
+ */
+#define CONFIG_MX31_CLK32		32000
+
+
+/*******************************************************************************
+ * RAM
+ ******************************************************************************/
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+/*
+ * PHYS_SDRAM_1 and PHYS_SDRAM_1_SIZE are passed to the Linux kernel.
+ * The size can be overridden by the kernel boot parameter "mem=".
+ */
+#define PHYS_SDRAM_1			CSD0_BASE
+#define PHYS_SDRAM_1_SIZE		(256 * 1024 * 1024)
+
+/* Default values for command mtest */
+#define CFG_MEMTEST_START		PHYS_SDRAM_1
+#define CFG_MEMTEST_END			(PHYS_SDRAM_1_SIZE - 0x100000)
+
+
+/*******************************************************************************
+ * NOR-Flash
+ ******************************************************************************/
+
+#define CFG_FLASH_BASE			CS0_BASE
+
+/* Max number of memory banks */
+#define CFG_MAX_FLASH_BANKS		4
+
+/*
+ * Bank start addresses.
+ * 4 x 32 MiB is the maximum for user and U-Boot code. Please adapt the list
+ * as well as CFG_MAX_FLASH_BANKS to your TQM. Also consider dual die chips
+ * or single die chips, e.g. one dual die chip represents two banks.
+ */
+#define CFG_FLASH_BANKS_LIST		{CFG_FLASH_BASE, 		\
+					CFG_FLASH_BASE + 32*1024*1024,	\
+					CFG_FLASH_BASE + 64*1024*1024,	\
+					CFG_FLASH_BASE + 96*1024*1024}
+
+/* Max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT		259
+
+/* Monitor at beginning of flash */
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+
+/* Reserved flash space for U-Boot image in bytes */
+#define CFG_MONITOR_LEN			(128 * 1024)
+
+/* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI			1
+
+/* Use drivers/cfi_flash.c */
+#define CFG_FLASH_CFI_DRIVER		1
+
+/* Use buffered writes (~10x faster) */
+#define CFG_FLASH_USE_BUFFER_WRITE	1
+
+/* Use hardware sector protection */
+#define CFG_FLASH_PROTECTION		1
+
+
+/*******************************************************************************
+ * Serial
+ ******************************************************************************/
+
+/* Configure processor internal UART */
+#define CONFIG_MX31_UART		1
+
+/* Configure UART1 */
+#define CFG_MX31_UART1			1
+
+/* Use UART1 for console */
+#define CONFIG_CONS_INDEX		1
+
+/* Default baudrate */
+#define CONFIG_BAUDRATE			115200
+
+/* Possible baudrates */
+#define CFG_BAUDRATE_TABLE		{9600, 19200, 38400, 57600, 115200}
+
+
+/*******************************************************************************
+ * Ethernet
+ ******************************************************************************/
+
+#define CONFIG_DRIVER_SMC911X		1
+#define CONFIG_DRIVER_SMC911X_32_BIT	1
+#define CONFIG_DRIVER_SMC911X_BASE	CS4_BASE
+
+
+/*******************************************************************************
+ * Commands
+ ******************************************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+
+/*******************************************************************************
+ * Environment
+ ******************************************************************************/
+
+#define CONFIG_BOOTDELAY		4
+
+/* Default values */
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_IPADDR			172.20.5.100
+#define CONFIG_SERVERIP			172.20.5.121
+
+/*
+ * Default value for env. variable "loadaddr".
+ * Don't use arithmetic here, because it will be converted
+ * into a string (see common/environment.c)
+ */
+#define CONFIG_LOADADDR			0x80800000
+
+/* Default load address */
+#define CFG_LOAD_ADDR			CONFIG_LOADADDR
+
+/* Allow to modify environment variables "serial#" and "ethaddr" */
+#define CONFIG_ENV_OVERWRITE
+
+#define	CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_OFFSET			0x20000
+#define CFG_ENV_ADDR			(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#define CFG_ENV_SECT_SIZE		0x20000
+#define CFG_ENV_SIZE			CFG_ENV_SECT_SIZE
+
+/* Address and size of redundant environment sector */
+#define CFG_ENV_OFFSET_REDUND		(CFG_ENV_OFFSET + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND		CFG_ENV_SECT_SIZE
+
+/*
+ * Kernel parameter "jtag=on" is Freescale-specific extension of the
+ * mx31ads BSP. Use it to enable serial console output in Linux.
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=tqma31\0"						\
+	"uboot_addr=0xa0000000\0"					\
+	"uboot=tqma31/u-boot.bin\0"					\
+	"kernel=tqma31/uImage\0"					\
+	"nfsroot=/opt/eldk/arm\0"					\
+	"bootargs_base=setenv bootargs "				\
+		"jtag=on "						\
+		"console=ttymxc0,115200\0"				\
+	"bootargs_nfs=setenv bootargs ${bootargs} "			\
+		"root=/dev/nfs rw "					\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+			"${netmask}:${hostname}:${netdev}:off "		\
+		"panic=1 "						\
+		"nfsroot=${serverip}:${nfsroot}\0"			\
+	"bootcmd=run bootcmd_net\0"					\
+	"bootcmd_net=run bootargs_base bootargs_nfs; "			\
+		"tftpboot ${loadaddr} ${kernel}; bootm\0"		\
+	"prg_uboot=tftpboot ${loadaddr} ${uboot}; "			\
+		"protect off ${uboot_addr} 0xa001ffff; "		\
+		"erase ${uboot_addr} 0xa001ffff; "			\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}; "		\
+		"setenv filesize; saveenv\0"
+
+
+/*******************************************************************************
+ * JFFS2 partitions
+ ******************************************************************************/
+
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+
+
+/*******************************************************************************
+ * Miscellaneous
+ ******************************************************************************/
+
+/* Total available space for malloc in bytes */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+
+/* Regular stack size in bytes */
+#define CONFIG_STACKSIZE		(128 * 1024)
+
+/* Size in bytes reserved for initial global data */
+#define CFG_GBL_DATA_SIZE		128
+
+/* Console I/O buffer size in bytes */
+#define CFG_CBSIZE			256
+
+/* Print buffer size in bytes */
+#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+/* Max number of command arguments */
+#define CFG_MAXARGS			16
+
+/* Boot argument buffer size in bytes */
+#define CFG_BARGSIZE			CFG_CBSIZE
+
+#define CFG_LONGHELP
+#define CFG_PROMPT			"=> "
+
+/* Add command line history and command line edit possibility */
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_ARP_TIMEOUT		200UL
+
+#endif /* __CONFIG_H */

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Jean-Christophe PLAGNIOL-VILLARD]

On 11:33 Tue 08 Jul     , Jens Gehrlein wrote:
> Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
> ---
> 
> Fixed two bugs:
> a) added NFS mount option "rw" to default environment
> b) added prefix $(obj) in front of .depend in Makefile. Thank you Magnus for catching that.
> 
> 
>  MAINTAINERS                           |    4 
>  MAKEALL                               |    1 
>  Makefile                              |    3 
>  board/tqc/tqma31/Makefile             |   48 ++++
>  board/tqc/tqma31/config.mk            |    2 
>  board/tqc/tqma31/lowlevel_init.S      |  375 +++++++++++++++++++++++++++++++++
>  board/tqc/tqma31/tqma31.c             |   95 ++++++++
>  board/tqc/tqma31/u-boot.lds           |   72 ++++++
>  include/asm-arm/arch-mx31/mx31-regs.h |   42 ++++
>  include/configs/TQMA31.h              |  271 ++++++++++++++++++++++++
>  10 files changed, 913 insertions(+), 0 deletions(-)
>  create mode 100644 board/tqc/tqma31/Makefile
>  create mode 100644 board/tqc/tqma31/config.mk
>  create mode 100644 board/tqc/tqma31/lowlevel_init.S
>  create mode 100644 board/tqc/tqma31/tqma31.c
>  create mode 100644 board/tqc/tqma31/u-boot.lds
>  create mode 100644 include/configs/TQMA31.h
> 
> +
> +COBJS	:= tqma31.o
why not use $(BOARD)?
COBJS	:= $(BOARD).o
> +SOBJS	:= lowlevel_init.o
> +
> +SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS	:= $(addprefix $(obj),$(COBJS))
> +SOBJS	:= $(addprefix $(obj),$(SOBJS))
> +
> +#elif defined CONFIG_MX31_CPU_532_MHZ
> +	/* Platform clocks */
> +	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff)	/* camera sensor interface */		\
> +			| PDR0_PER_PODF(8-1)	/* periph. if derived from USB clock */	\
> +			| PDR0_HSP_PODF(4-1)	/* IPU 133 MHz */                      	\
Please use tab instead of whitespace
> +			| PDR0_NFC_PODF(7-1)	/* NAND FC 19 MHz */                   	\
Please use tab instead of whitespace
> +			| PDR0_IPG_PODF(2-1)	/* peripherals 66.5 MHz */             	\
Please use tab instead of whitespace
> +			| PDR0_MAX_PODF(4-1)	/* AHB 133 MHz */                      	\
Please use tab instead of whitespace
> +			| PDR0_MCU_PODF(1-1)	/* core 532 MHz */
> +	/* MCU PLL */
> +	REG	CCM_MPCTL, PLL_PD(1-1) | PLL_MFD(52-1) | PLL_MFI(10) | PLL_MFN(12)
> +#else
> +#error Please define CPU core frequency (CONFIG_CPU_399_MHZ or CONFIG_CPU_532_MHZ)!
> +#endif /* CONFIG_CPU_xxx_MHZ */
> +
> +	/* Serial PLL. Default: 1, 4, 12, 1 */
> +	REG	CCM_SPCTL, PLL_PD(2-1) | PLL_MFD(5-1) | PLL_MFI(12) | PLL_MFN(1)
> +.endm /* init_sdram */
> +
> +
> +/* setup SDRAM on CSD0 */
> +.macro init_sdram
> +	/*
> +	 * Enhanced SDRAM Miscellaneous Register
> +	 *	Latency Hiding Enable
> +	 *	LPDDR delay line measure unit is enabled
> +	 *	LPDDR Delay Line is not reset
> +	 *	Enable Mobile DDR SDRAM operation
> +	 *	Soft Reset is disabled
> +	 */
> +	REG	ESDMISC, 0x00000004
> +
> +	/*
> +	 * Enhanced SDRAM Configuration Register 0
> +	 *	tXP 4 clock delay before new COMMAND issued to LPDDR
> +	 *	tWTR tLPDDR WRITE to READ Command Delay = 2 clock
> +	 *	tRP SDRAM Row Precharge Delay = 3 clock
> +	 *	tMRD?SDRAM Load Mode Register to ACTIVE Command = 3 clock
you have a nice char here '<96>' in vim
> +	 *	tWR SDRAM WRITE to PRECHARGE Command = 3 clock
> +	 *	tRAS SDRAM ACTIVE to PRECHARGE Command = 6 clock
> +	 *	tRRD ACTIVE Bank A to ACTIVE Bank B Command = 2 clock
> +	 *	tCAS CAS Latency = 3 clock
> +	 *	tRCD SDRAM Row to Column Delay = 3 clock
> +	 *	tRC SDRAM Row Cycle Delay = 13 clocks
> +	 */
> +	REG	ESDCFG0, 0x006ac73c
> +
> +	/*
> +	 * Enhanced SDRAM Control Register 0
> +	 *	Enhanced SDRAM Controller Enable = 1
> +	 *	SDRAM Controller Operating Mode = 001 Precharge Command
> +	 *	Supervisor Protect = 0 User mode accesses are allowed to this
> +	 *		chip select region
> +	 *	ROW Row Address Width. = 011 14 Row Addresses
> +	 *	COL Column Address Width = 01 9 Col Addresses
> +	 *	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
> +	 *		aligned to D[31:16]
> +	 *	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
> +	 *		(bit field reset value)
> +	 *	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
> +	 *	FP Full Page = 0 0 Burst Length of the external memory device
> +	 *		is not set to Full Page
> +	 *	BL Burst Length = 0
> +	 *	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
> +	 */
> +	REG	ESDCTL0, 0x92200000
> +	REG	0x80000f00, 0x12344321
> +
> +
> +  	/*
Please use tab instead of whitespace
> +  	 * Enhanced SDRAM Control Register 0
Please use tab instead of whitespace
> +	 *	Enhanced SDRAM Controller Enable = 1
> +	 *	SDRAM Controller Operating Mode = 010 Auto-Refresh Command
> +	 *	Supervisor Protect = 0 User mode accesses are allowed to this
> +	 *		chip select region
> +	 *	ROW Row Address Width. = 011 14 Row Addresses
> +	 *	COL Column Address Width = 01 9 Col Addresses
> +	 *	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
> +	 *		aligned to D[31:16]
> +	 *	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
> +	 *		(bit field reset value)
> +	 *	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
> +	 *	FP Full Page = 0 0 Burst Length of the external memory device
> +	 *		is not set to Full Page
> +	 *	BL Burst Length = 0
> +	 *	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
> +	 */
> +	REG	ESDCTL0, 0xa2200000
> +	REG	0x80000000, 0x12344321
> +	REG	0x80000000, 0x12344321
> +
> +	/*
> +	 * Enhanced SDRAM Control Register 0
> +	 * 	Enhanced SDRAM Controller Enable = 1
Please use tab instead of whitespace
> +	 * 	SDRAM Controller Operating Mode = 001 Precharge Command
Please use tab instead of whitespace
> +	 * 	Supervisor Protect = 0 User mode accesses are allowed to this
Please use tab instead of whitespace
> +	 *		chip select region
> +	 * 	ROW Row Address Width. = 011 14 Row Addresses
Please use tab instead of whitespace
> +	 * 	COL Column Address Width = 01 9 Col Addresses
Please use tab instead of whitespace
> +	 * 	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
Please use tab instead of whitespace
> +	 *		aligned to D[31:16]
> +	 * 	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
Please use tab instead of whitespace
> +	 *		(bit field reset value)
> +	 * 	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
Please use tab instead of whitespace
> +	 * 	FP Full Page = 0 0 Burst Length of the external memory device
Please use tab instead of whitespace
> +	 *		is not set to Full Page.
> +	 * 	BL Burst Length = 0
Please use tab instead of whitespace
> +	 * 	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
Please use tab instead of whitespace
> +	 */
> +	REG	ESDCTL0, 0xb2200000
> +	REG8	0x80000033, 0xda
> +	REG8	0x81000000, 0xff
> +
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +
> +	return 0;
> +}
> +
> +int board_init (void)
> +{
> +	/* WEIM burst clock runs all the time */
> +	__REG (WCR) = WCR_BCM_1;
> +
> +	setup_chipselects ();
> +	setup_iomux ();
> +
> +	/*
> +	 * FIXME:
> +	 * Replace machine type ID by symbolic define MACH_TYPE_TQMA31 as soon
> +	 * as updated file mach-types.h is available in U-Boot tree.
> +	 * Machine type ID 1810 for TQMA31 has been registered on 2008-06-25.
> +	 */
> +	/* Machine type ID for ARM linux */
> +	gd->bd->bi_arch_number = 1810;
No please update the mach-types.h
> +
> +	/* Address of boot parameters */
> +	gd->bd->bi_boot_params = 0x80000100;
> +
 +
> +/*
> + * Bank start addresses.
> + * 4 x 32 MiB is the maximum for user and U-Boot code. Please adapt the list
> + * as well as CFG_MAX_FLASH_BANKS to your TQM. Also consider dual die chips
> + * or single die chips, e.g. one dual die chip represents two banks.
> + */
> +#define CFG_FLASH_BANKS_LIST		{CFG_FLASH_BASE, 		\
Please use tab instead of whitespace
> +					CFG_FLASH_BASE + 32*1024*1024,	\
							please add space
							between operators
> +					CFG_FLASH_BASE + 64*1024*1024,	\
> +					CFG_FLASH_BASE + 96*1024*1024}
> +
> +/* Max number of sectors on one chip */
> +#define CFG_MAX_FLASH_SECT		259
> +
> +/* Monitor at beginning of flash *

Best Regards,
J.

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Heiko Schocher]

Hello Jens,

one comment to your patch:

Jens Gehrlein wrote:

> Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
> ---
>
> Fixed two bugs:
> a) added NFS mount option "rw" to default environment
> b) added prefix $(obj) in front of .depend in Makefile. Thank you Magnus for catching that.
>   
[...]
> +
> +/*******************************************************************************
> + * Environment
> + ******************************************************************************/
> +
> +#define CONFIG_BOOTDELAY		4
> +
> +/* Default values */
> +#define CONFIG_NETMASK			255.255.255.0
> +#define CONFIG_IPADDR			172.20.5.100
> +#define CONFIG_SERVERIP			172.20.5.121
>   
Please delete this block. We do not accept such settings in default
config files.


bye,
Heiko

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany 

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Jens Gehrlein]

Hi Heiko,

Heiko Schocher schrieb:
> Hello Jens,
> 
> one comment to your patch:
> 
> Jens Gehrlein wrote:
> 
>> Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
>> ---
>>
>> Fixed two bugs:
>> a) added NFS mount option "rw" to default environment
>> b) added prefix $(obj) in front of .depend in Makefile. Thank you Magnus for catching that.
>>   
> [...]
>> +
>> +/*******************************************************************************
>> + * Environment
>> + ******************************************************************************/
>> +
>> +#define CONFIG_BOOTDELAY		4
>> +
>> +/* Default values */
>> +#define CONFIG_NETMASK			255.255.255.0
>> +#define CONFIG_IPADDR			172.20.5.100
>> +#define CONFIG_SERVERIP			172.20.5.121
>>   
> Please delete this block. We do not accept such settings in default
> config files.

To understand you properly: do you mean the defines for netmask, ipaddr 
and serverip, i.e. bootdelay and headerline are okay? I ask, because you 
quoted the upper lines, too.

Kind regards,
Jens

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Jens Gehrlein]

Hi Jean-Christophe,

Jean-Christophe PLAGNIOL-VILLARD schrieb:

>> +COBJS	:= tqma31.o
> why not use $(BOARD)?
> COBJS	:= $(BOARD).o

Okay.

>> +SOBJS	:= lowlevel_init.o
>> +
>> +SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
>> +OBJS	:= $(addprefix $(obj),$(COBJS))
>> +SOBJS	:= $(addprefix $(obj),$(SOBJS))
>> +
>> +#elif defined CONFIG_MX31_CPU_532_MHZ
>> +	/* Platform clocks */
>> +	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff)	/* camera sensor interface */		\
>> +			| PDR0_PER_PODF(8-1)	/* periph. if derived from USB clock */	\
>> +			| PDR0_HSP_PODF(4-1)	/* IPU 133 MHz */                      	\
> Please use tab instead of whitespace
>> +			| PDR0_NFC_PODF(7-1)	/* NAND FC 19 MHz */                   	\
> Please use tab instead of whitespace
>> +			| PDR0_IPG_PODF(2-1)	/* peripherals 66.5 MHz */             	\
> Please use tab instead of whitespace
>> +			| PDR0_MAX_PODF(4-1)	/* AHB 133 MHz */                      	\
> Please use tab instead of whitespace
>> +			| PDR0_MCU_PODF(1-1)	/* core 532 MHz */

Okay.

>> +	/* MCU PLL */
>> +	REG	CCM_MPCTL, PLL_PD(1-1) | PLL_MFD(52-1) | PLL_MFI(10) | PLL_MFN(12)
>> +#else
>> +#error Please define CPU core frequency (CONFIG_CPU_399_MHZ or CONFIG_CPU_532_MHZ)!
>> +#endif /* CONFIG_CPU_xxx_MHZ */
>> +
>> +	/* Serial PLL. Default: 1, 4, 12, 1 */
>> +	REG	CCM_SPCTL, PLL_PD(2-1) | PLL_MFD(5-1) | PLL_MFI(12) | PLL_MFN(1)
>> +.endm /* init_sdram */
>> +
>> +
>> +/* setup SDRAM on CSD0 */
>> +.macro init_sdram
>> +	/*
>> +	 * Enhanced SDRAM Miscellaneous Register
>> +	 *	Latency Hiding Enable
>> +	 *	LPDDR delay line measure unit is enabled
>> +	 *	LPDDR Delay Line is not reset
>> +	 *	Enable Mobile DDR SDRAM operation
>> +	 *	Soft Reset is disabled
>> +	 */
>> +	REG	ESDMISC, 0x00000004
>> +
>> +	/*
>> +	 * Enhanced SDRAM Configuration Register 0
>> +	 *	tXP 4 clock delay before new COMMAND issued to LPDDR
>> +	 *	tWTR tLPDDR WRITE to READ Command Delay = 2 clock
>> +	 *	tRP SDRAM Row Precharge Delay = 3 clock
>> +	 *	tMRD?SDRAM Load Mode Register to ACTIVE Command = 3 clock
> you have a nice char here '<96>' in vim

Uups. Well catched. Got this code from my colleague and missed that. 
Thank you.


>> +
>> +
>> +  	/*
> Please use tab instead of whitespace
>> +  	 * Enhanced SDRAM Control Register 0
> Please use tab instead of whitespace
>> +	 *	Enhanced SDRAM Controller Enable = 1
>> +	 *	SDRAM Controller Operating Mode = 010 Auto-Refresh Command
>> +	 *	Supervisor Protect = 0 User mode accesses are allowed to this
>> +	 *		chip select region
>> +	 *	ROW Row Address Width. = 011 14 Row Addresses
>> +	 *	COL Column Address Width = 01 9 Col Addresses
>> +	 *	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
>> +	 *		aligned to D[31:16]
>> +	 *	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
>> +	 *		(bit field reset value)
>> +	 *	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
>> +	 *	FP Full Page = 0 0 Burst Length of the external memory device
>> +	 *		is not set to Full Page
>> +	 *	BL Burst Length = 0
>> +	 *	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
>> +	 */
>> +	REG	ESDCTL0, 0xa2200000
>> +	REG	0x80000000, 0x12344321
>> +	REG	0x80000000, 0x12344321
>> +
>> +	/*
>> +	 * Enhanced SDRAM Control Register 0
>> +	 * 	Enhanced SDRAM Controller Enable = 1
> Please use tab instead of whitespace
>> +	 * 	SDRAM Controller Operating Mode = 001 Precharge Command
> Please use tab instead of whitespace
>> +	 * 	Supervisor Protect = 0 User mode accesses are allowed to this
> Please use tab instead of whitespace
>> +	 *		chip select region
>> +	 * 	ROW Row Address Width. = 011 14 Row Addresses
> Please use tab instead of whitespace
>> +	 * 	COL Column Address Width = 01 9 Col Addresses
> Please use tab instead of whitespace
>> +	 * 	DSIZ SDRAM Memory Data Width = 00 00 16-bit memory width
> Please use tab instead of whitespace
>> +	 *		aligned to D[31:16]
>> +	 * 	SREFR SDRAM Refresh Rate  = 000 Refresh Disabled
> Please use tab instead of whitespace
>> +	 *		(bit field reset value)
>> +	 * 	PWDT Power Down = 00 Disabled (bit field reset value) Run Mode
> Please use tab instead of whitespace
>> +	 * 	FP Full Page = 0 0 Burst Length of the external memory device
> Please use tab instead of whitespace
>> +	 *		is not set to Full Page.
>> +	 * 	BL Burst Length = 0
> Please use tab instead of whitespace
>> +	 * 	PRCT Precharge Timer 000000 Disabled (Bit field reset value)
> Please use tab instead of whitespace

Okay.

>> +	 */
>> +	REG	ESDCTL0, 0xb2200000
>> +	REG8	0x80000033, 0xda
>> +	REG8	0x81000000, 0xff
>> +
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +
>> +	return 0;
>> +}
>> +
>> +int board_init (void)
>> +{
>> +	/* WEIM burst clock runs all the time */
>> +	__REG (WCR) = WCR_BCM_1;
>> +
>> +	setup_chipselects ();
>> +	setup_iomux ();
>> +
>> +	/*
>> +	 * FIXME:
>> +	 * Replace machine type ID by symbolic define MACH_TYPE_TQMA31 as soon
>> +	 * as updated file mach-types.h is available in U-Boot tree.
>> +	 * Machine type ID 1810 for TQMA31 has been registered on 2008-06-25.
>> +	 */
>> +	/* Machine type ID for ARM linux */
>> +	gd->bd->bi_arch_number = 1810;
> No please update the mach-types.h

I thought this file gets updated from time to time by copying from the 
kernel. But after having a look into the git history of this file, it is 
not so. I will update directly.

>> +
>> +	/* Address of boot parameters */
>> +	gd->bd->bi_boot_params = 0x80000100;
>> +
>  +
>> +/*
>> + * Bank start addresses.
>> + * 4 x 32 MiB is the maximum for user and U-Boot code. Please adapt the list
>> + * as well as CFG_MAX_FLASH_BANKS to your TQM. Also consider dual die chips
>> + * or single die chips, e.g. one dual die chip represents two banks.
>> + */
>> +#define CFG_FLASH_BANKS_LIST		{CFG_FLASH_BASE, 		\
> Please use tab instead of whitespace

Okay.

>> +					CFG_FLASH_BASE + 32*1024*1024,	\
> 							please add space
> 							between operators

Okay.


Thank you very much for catching all these silly mistakes.

A last question:
When I want to "reply all", your e-mail address doesn't appear in the 
to-field. I have to add the address manually. Is this intended?

Kind regards,
Jens

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Heiko Schocher]

Hello Jens,

Jens Gehrlein wrote:
> Heiko Schocher schrieb:
>> Hello Jens,
>>
>> one comment to your patch:
>>
>> Jens Gehrlein wrote:
>>
>>> Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
>>> ---
>>>
>>> Fixed two bugs:
>>> a) added NFS mount option "rw" to default environment
>>> b) added prefix $(obj) in front of .depend in Makefile. Thank you
>>> Magnus for catching that.
>>>   
>> [...]
>>> +
>>> +/*******************************************************************************
>>>
>>> + * Environment
>>> +
>>> ******************************************************************************/
>>>
>>> +
>>> +#define CONFIG_BOOTDELAY        4
>>> +
>>> +/* Default values */
>>> +#define CONFIG_NETMASK            255.255.255.0
>>> +#define CONFIG_IPADDR            172.20.5.100
>>> +#define CONFIG_SERVERIP            172.20.5.121
>>>   
>> Please delete this block. We do not accept such settings in default
>> config files.
> 
> To understand you properly: do you mean the defines for netmask, ipaddr
> and serverip, i.e. bootdelay and headerline are okay? I ask, because you
> quoted the upper lines, too.

Yes, I only meant netmask, ipaddr and serverip.

bye
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Wolfgang Denk]

In message <20080708093022.9272.4677.stgit@tq-sewsrv-4.tq-net.de> you wrote:
>
> +/* Timer tick */
> +#define CFG_HZ				32768

CFG_HZ is a constant and has to be 1000.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Hokey religions and ancient weapons are  no  substitute  for  a  good
blaster at your side.                                      - Han Solo

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Jens Gehrlein]

Wolfgang Denk schrieb:
> In message <20080708093022.9272.4677.stgit@tq-sewsrv-4.tq-net.de> you wrote:
>> +/* Timer tick */
>> +#define CFG_HZ				32768
> 
> CFG_HZ is a constant and has to be 1000.

I know, we had a discussion earlier about that issue (see "i.MX31: 
question about CFG_HZ and CKIL" of 7th May). The situation is as follows:

The TQMA31, as well as the mx32ads use the General Purpose Timer 1, 
which is feeded by a 32768 clock (possibly imx31_litekit and 
imx31_phycore with 32000 Hz? I don't know.). The prescale divider can 
only be an integer. 32768/1000 = non-integer.

The counter is just read. There are no real interrupts (I mention it, 
because you wrote about this earlier).
The origin source code is from U-Boot V2, I suppose. Guennadi used it 
for the mx31ads.

Currently, I see only one way to solve this:
1. Patch the common file cpu/arm1136/mx31/interrupts.c, function 
interrupt_init(), so that the prescaler divides by 33.
Alternatively, also make the divider a board specific define.
2. Patch all mx31 board config header files with CFG_HZ 1000.
3. All mx31 boards have to be tested.

The following is impossible:
- changing the HW
- using an internal clock, because maximum is 1000 Hz * 4096 = 4096000 
Hz (the maximum divider is 4096). All internal clocks are much higher.
Please for correction if I'm wrong.

What do you suggest to do and who does it?

And while we are at the timers:
The udelay function is the next problem:
udelay cannot go below 1/(32768 Hz) = 30.5 micros
The current function inserts a theoretical nop if the requested usec 
value is below 1000. Therefore, IMHO, this timer is relatively 
imprecise, because the resulting delay is below 1 microsecond.
IMHO, this all because of that slow input clock.

Kind regards,
Jens

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Jean-Christophe PLAGNIOL-VILLARD]

> Thank you very much for catching all these silly mistakes.
>
> A last question:
> When I want to "reply all", your e-mail address doesn't appear in the  
> to-field. I have to add the address manually. Is this intended?

wierd, in the mail i'm not in the CC but in the FROM

Best Regards,
J.

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Guennadi Liakhovetski]

On Tue, 8 Jul 2008, Jens Gehrlein wrote:

> diff --git a/board/tqc/tqma31/Makefile b/board/tqc/tqma31/Makefile
> new file mode 100644
> index 0000000..f7e17c8
> --- /dev/null
> +++ b/board/tqc/tqma31/Makefile
> @@ -0,0 +1,48 @@
> +#
> +# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
> +# Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>

Thanks for the credit, but, although IANAL, I think, one does not _have_ 
to preserve the copyright of the original file when it gets copied to a 
new one. Otherwise most open-source files would have a veeeery long list 
of Copyrights:-) Am I right?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Wolfgang Denk]

In message <Pine.LNX.4.64.0807090048470.30894@axis700.grange> you wrote:
>
> > +# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
> > +# Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
> 
> Thanks for the credit, but, although IANAL, I think, one does not _have_ 
> to preserve the copyright of the original file when it gets copied to a 

Yes, of course you do. If you copy code, you *must* honour existing
copyrights and have not any right to remove these.

> new one. Otherwise most open-source files would have a veeeery long list 
> of Copyrights:-) Am I right?

No, you are fundamentally wrong.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Brain off-line, please wait.

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Guennadi Liakhovetski]

On Wed, 9 Jul 2008, Wolfgang Denk wrote:

> In message <Pine.LNX.4.64.0807090048470.30894@axis700.grange> you wrote:
> >
> > > +# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
> > > +# Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
> > 
> > Thanks for the credit, but, although IANAL, I think, one does not _have_ 
> > to preserve the copyright of the original file when it gets copied to a 
> 
> Yes, of course you do. If you copy code, you *must* honour existing
> copyrights and have not any right to remove these.

hm, starting from how many lines of code? Copy-paste is one of the main 
programming technics, as we all know:-) If you copy one line, you don't 
have to transfer all copyrights over, do you?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Jens Gehrlein]

Hi Guennadi,

Guennadi Liakhovetski schrieb:
> On Tue, 8 Jul 2008, Jens Gehrlein wrote:
> 
>> diff --git a/board/tqc/tqma31/Makefile b/board/tqc/tqma31/Makefile
>> new file mode 100644
>> index 0000000..f7e17c8
>> --- /dev/null
>> +++ b/board/tqc/tqma31/Makefile
>> @@ -0,0 +1,48 @@
>> +#
>> +# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
>> +# Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
> 
> Thanks for the credit, but, although IANAL, I think, one does not _have_ 
> to preserve the copyright of the original file when it gets copied to a 
> new one. Otherwise most open-source files would have a veeeery long list 
> of Copyrights:-) Am I right?

I didn't quite understand. So what should I remove:
- your name?
- my name?
- all?
- in all files (much work)?

Thanks.

Neither I'm a lawyer. I just had a look to other source files, were it's 
done similar.

Kind regards,
Jens

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Wolfgang Denk]

In message <Pine.LNX.4.64.0807090129450.30894@axis700.grange> you wrote:
> 
> > Yes, of course you do. If you copy code, you *must* honour existing
> > copyrights and have not any right to remove these.
> 
> hm, starting from how many lines of code? Copy-paste is one of the main 
> programming technics, as we all know:-) If you copy one line, you don't 
> have to transfer all copyrights over, do you?

I don't know of any "official" rules, but anything above the 5...10
lines limit should be properly attributed.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A morsel of genuine history is a  thing  so  rare  as  to  be  always
valuable.                                          - Thomas Jefferson

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Wolfgang Denk]

In message <48745B7C.3020400@tqs.de> you wrote:
> 
> I didn't quite understand. So what should I remove:

Nothing shall be removed. Guennadi was wrong.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Is truth not truth for all?
	-- Natira, "For the World is Hollow and I have Touched
		   the Sky", stardate 5476.4.

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Jerry Van Baren]

Guennadi Liakhovetski wrote:
> On Tue, 8 Jul 2008, Jens Gehrlein wrote:
> 
>> diff --git a/board/tqc/tqma31/Makefile b/board/tqc/tqma31/Makefile
>> new file mode 100644
>> index 0000000..f7e17c8
>> --- /dev/null
>> +++ b/board/tqc/tqma31/Makefile
>> @@ -0,0 +1,48 @@
>> +#
>> +# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
>> +# Copyright (C) 2008, Jens Gehrlein <sew_s@tqs.de>
> 
> Thanks for the credit, but, although IANAL, I think, one does not _have_ 
> to preserve the copyright of the original file when it gets copied to a 
> new one. Otherwise most open-source files would have a veeeery long list 
> of Copyrights:-) Am I right?
> 
> Thanks
> Guennadi

IANAL, but I play one on Groklaw sometimes, much to PJ's chagrin. ;-)

This is a squishy area.  It is dependent on what of the original work 
survives the modification and whether the surviving pieces are 
copyrightable.  It also depends on what country you are contemplating 
suing in.

<http://en.wikipedia.org/wiki/Limitations_and_exceptions_to_copyright>

Things that must be done in certain ways are not copyrightable, so 
Makefiles are pretty marginal to start with IMHO.

<http://en.wikipedia.org/wiki/Threshold_of_originality>

My opinion is to leave the original copyright notice in there and err on 
the side of preserving reasonable copyright notices.  The lawyers will 
be happy to tell us that we did it wrong if it ever came to a lawsuit, 
and I would prefer that they tell us that we had a useless copyright 
notice in the file rather than tell us that we should have had a notice 
but didn't...

Best regards,
gvb

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Wolfgang Denk]

In message <4873845B.3020808@tqs.de> you wrote:
>
> The TQMA31, as well as the mx32ads use the General Purpose Timer 1, 
> which is feeded by a 32768 clock (possibly imx31_litekit and 
> imx31_phycore with 32000 Hz? I don't know.). The prescale divider can 
> only be an integer. 32768/1000 = non-integer.

I think other architectures hav / had similar issues. See for example
the MIPS fixes that were added some time ago.

> Currently, I see only one way to solve this:
> 1. Patch the common file cpu/arm1136/mx31/interrupts.c, function 
> interrupt_init(), so that the prescaler divides by 33.
> Alternatively, also make the divider a board specific define.
> 2. Patch all mx31 board config header files with CFG_HZ 1000.
> 3. All mx31 boards have to be tested.

Sounds like a plan.

> And while we are at the timers:
> The udelay function is the next problem:
> udelay cannot go below 1/(32768 Hz) = 30.5 micros
> The current function inserts a theoretical nop if the requested usec 
> value is below 1000. Therefore, IMHO, this timer is relatively 
> imprecise, because the resulting delay is below 1 microsecond.
> IMHO, this all because of that slow input clock.

How is this handled in Linux? I don't think they would let this go
through?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Speed of a tortoise breaking the sound barrier         = 1 Machturtle

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Jens Gehrlein]

Wolfgang Denk schrieb:
> In message <4873845B.3020808@tqs.de> you wrote:
>> The TQMA31, as well as the mx32ads use the General Purpose Timer 1, 
>> which is feeded by a 32768 clock (possibly imx31_litekit and 
>> imx31_phycore with 32000 Hz? I don't know.). The prescale divider can 
>> only be an integer. 32768/1000 = non-integer.
> 
> I think other architectures hav / had similar issues. See for example
> the MIPS fixes that were added some time ago.

I'll take a look.


>> Currently, I see only one way to solve this:
>> 1. Patch the common file cpu/arm1136/mx31/interrupts.c, function 
>> interrupt_init(), so that the prescaler divides by 33.
>> Alternatively, also make the divider a board specific define.
>> 2. Patch all mx31 board config header files with CFG_HZ 1000.
>> 3. All mx31 boards have to be tested.
> 
> Sounds like a plan.

What do you mean?
It's just a proposal and I like to read comments from others, especially 
those, who wrote this code.


>> And while we are at the timers:
>> The udelay function is the next problem:
>> udelay cannot go below 1/(32768 Hz) = 30.5 micros
>> The current function inserts a theoretical nop if the requested usec 
>> value is below 1000. Therefore, IMHO, this timer is relatively 
>> imprecise, because the resulting delay is below 1 microsecond.
>> IMHO, this all because of that slow input clock.
> 
> How is this handled in Linux? I don't think they would let this go
> through?

I don't no. Where can I start to have a look on? According to 
experience, timer handling in Linux is much more complex.


Question: Why did you accept all the initial patches for 
cpu/arm1136/mx31/interrupts.c and for the boards mx31ads, imx31_litekit, 
imx31_phycore?

Kind regards,
Jens

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Wolfgang Denk]

In message <4875AAA3.2040501@tqs.de> you wrote:
>
> Question: Why did you accept all the initial patches for 
> cpu/arm1136/mx31/interrupts.c and for the boards mx31ads, imx31_litekit, 
> imx31_phycore?

Nobody raised concerns, and I did not notice problems  either.  I  do
not  claim  to catch 100% of all issues (I don't even claim to review
all postings).

But when I see a problem, I say so.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The following statement is not true.  The previous statement is true.

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new boardwith i.MX31 processor

[Martin Krause]

u-boot-users-bounces at lists.sourceforge.net wrote on :
> In message <4875AAA3.2040501@tqs.de> you wrote:
> > 
> > Question: Why did you accept all the initial patches for
> > cpu/arm1136/mx31/interrupts.c and for the boards mx31ads,
> > imx31_litekit, imx31_phycore?
> 
> Nobody raised concerns, and I did not notice problems  either.  I  do
> not  claim  to catch 100% of all issues (I don't even claim to review
> all postings).

If I could remember correctly, we (TQS) paid DENX for the U-Boot porting
of the mx31ads board. It is a little bit surprising that now the patch
for our own i.mx31 based board is not accepted, although we used the 
mx31ads port as basis. The reason for paying the mx31ads port was to get
an accepted basis for a common i.mx31 board into the official U-Boot
tree, to have a stable basis for further portings of i.mx31 boards (and
to give something back to the great U-Boot community which is hopefully
useful for many other users).

Best Regards,
Martin Krause

--
TQ-Systems GmbH
Muehlstrasse 2, Gut Delling, D-82229 Seefeld
Amtsgericht Muenchen, HRB 105 018, UST-IdNr. DE 811 607 913
Geschaeftsfuehrer: Dipl.-Ing. (FH) Detlef Schneider, Dipl.-Ing. (FH) Ruediger Stahl
http://www.tq-group.com

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Sascha Hauer]

Hi,

On Tue, Jul 08, 2008 at 05:14:35PM +0200, Jens Gehrlein wrote:
> Wolfgang Denk schrieb:
>> In message <20080708093022.9272.4677.stgit@tq-sewsrv-4.tq-net.de> you wrote:
>>> +/* Timer tick */
>>> +#define CFG_HZ				32768
>>
>> CFG_HZ is a constant and has to be 1000.

Why is it a board specific define then?

>
> I know, we had a discussion earlier about that issue (see "i.MX31:  
> question about CFG_HZ and CKIL" of 7th May). The situation is as follows:
>
> The TQMA31, as well as the mx32ads use the General Purpose Timer 1,  
> which is feeded by a 32768 clock (possibly imx31_litekit and  
> imx31_phycore with 32000 Hz? I don't know.). The prescale divider can  
> only be an integer. 32768/1000 = non-integer.
>
> The counter is just read. There are no real interrupts (I mention it,  
> because you wrote about this earlier).
> The origin source code is from U-Boot V2, I suppose. Guennadi used it  
> for the mx31ads.

Not quite correct, I wrote the original mx31 code for U-Boot V1 and then
ported it to V2. I think Guennadis work is based on the V1 work.

>
> Currently, I see only one way to solve this:
> 1. Patch the common file cpu/arm1136/mx31/interrupts.c, function  
> interrupt_init(), so that the prescaler divides by 33.
> Alternatively, also make the divider a board specific define.
> 2. Patch all mx31 board config header files with CFG_HZ 1000.
> 3. All mx31 boards have to be tested.
>
> The following is impossible:
> - changing the HW
> - using an internal clock, because maximum is 1000 Hz * 4096 = 4096000  
> Hz (the maximum divider is 4096). All internal clocks are much higher.
> Please for correction if I'm wrong.

You could add a software divider in get_timer(). But I think it's better
to define CFG_HZ to whatever the timer frequency is. At least 49 boards
do it.

Regards
  Sascha

-- 
Pengutronix e.K. - Linux Solutions for Science and Industry
-----------------------------------------------------------
Kontakt-Informationen finden Sie im Header dieser Mail oder
auf der Webseite -> http://www.pengutronix.de/impressum/ <-

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Sascha Hauer]

On Thu, Jul 10, 2008 at 12:46:42AM +0200, Wolfgang Denk wrote:
> In message <4873845B.3020808@tqs.de> you wrote:
> >
> > The TQMA31, as well as the mx32ads use the General Purpose Timer 1, 
> > which is feeded by a 32768 clock (possibly imx31_litekit and 
> > imx31_phycore with 32000 Hz? I don't know.). The prescale divider can 
> > only be an integer. 32768/1000 = non-integer.
> 
> I think other architectures hav / had similar issues. See for example
> the MIPS fixes that were added some time ago.
> 
> > Currently, I see only one way to solve this:
> > 1. Patch the common file cpu/arm1136/mx31/interrupts.c, function 
> > interrupt_init(), so that the prescaler divides by 33.
> > Alternatively, also make the divider a board specific define.
> > 2. Patch all mx31 board config header files with CFG_HZ 1000.
> > 3. All mx31 boards have to be tested.
> 
> Sounds like a plan.
> 
> > And while we are at the timers:
> > The udelay function is the next problem:
> > udelay cannot go below 1/(32768 Hz) = 30.5 micros
> > The current function inserts a theoretical nop if the requested usec 
> > value is below 1000. Therefore, IMHO, this timer is relatively 
> > imprecise, because the resulting delay is below 1 microsecond.
> > IMHO, this all because of that slow input clock.
> 
> How is this handled in Linux? I don't think they would let this go
> through?

Linux uses the high frequency timer, or better said, the same timer with
a high frequency input source.

Regards,
  Sascha

-- 
Pengutronix e.K. - Linux Solutions for Science and Industry
-----------------------------------------------------------
Kontakt-Informationen finden Sie im Header dieser Mail oder
auf der Webseite -> http://www.pengutronix.de/impressum/ <-

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Wolfgang Denk]

In message <20080710081725.GP4595@pengutronix.de> you wrote:
> 
> >> CFG_HZ is a constant and has to be 1000.
> 
> Why is it a board specific define then?

Historical reasons only. When PPCBoot was created, I played with that
parameter to get a feeling  for  the  involved  overhead,  etc.  This
should  really  be removed, but as you know too many boards depend on
this.

> You could add a software divider in get_timer(). But I think it's better
> to define CFG_HZ to whatever the timer frequency is. At least 49 boards
> do it.

That's what I mean: many boards need fixing.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A man either lives life as it happens to him, meets  it  head-on  and
licks it, or he turns his back on it and starts to wither away.
	-- Dr. Boyce, "The Menagerie" ("The Cage"), stardate unknown

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Sascha Hauer]

On Thu, Jul 10, 2008 at 10:49:09AM +0200, Wolfgang Denk wrote:
> In message <20080710081725.GP4595@pengutronix.de> you wrote:
> > 
> > >> CFG_HZ is a constant and has to be 1000.
> > 
> > Why is it a board specific define then?
> 
> Historical reasons only. When PPCBoot was created, I played with that
> parameter to get a feeling  for  the  involved  overhead,  etc.  This
> should  really  be removed, but as you know too many boards depend on
> this.
> 
> > You could add a software divider in get_timer(). But I think it's better
> > to define CFG_HZ to whatever the timer frequency is. At least 49 boards
> > do it.
> 
> That's what I mean: many boards need fixing.

How about using the Linux clocksource framework for U-Boot? I did this
for V2 and it works like a charm. The timer implementation is straight
forward. You only have to setup a free running timer and return its
value, so there's not much to do wrong when implementing new timers.
Currently U-Boot has many timing functions like get_timer,
get_timer_masked, reset_timer, reset_timer_masked, udelay and I suppose
most people do not understand the meaning of those functions, as the
differing implementations show.
Not that I volunteer to do this job though :(

Regards,
  Sascha

-- 
 Pengutronix - Linux Solutions for Science and Industry
   Handelsregister:  Amtsgericht Hildesheim, HRA 2686
     Hannoversche Str. 2, 31134 Hildesheim, Germany
   Phone: +49-5121-206917-0 |  Fax: +49-5121-206917-9

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Wolfgang Denk]

In message <20080710093001.GR4595@pengutronix.de> you wrote:
>
> How about using the Linux clocksource framework for U-Boot? I did this

I have to admit that I don't know how big that code is?

> Currently U-Boot has many timing functions like get_timer,
> get_timer_masked, reset_timer, reset_timer_masked, udelay and I suppose
> most people do not understand the meaning of those functions, as the
> differing implementations show.

I have to admit that I don't have  a  clue  why  get_timer_masked  or
reset_timer_masked   would   be   needed.  Originally  (see  the  PPC
implementation), there was only get_timer,  reset_timer,  and  udelay
(and IIRC reset_timer was not even necessary).

> Not that I volunteer to do this job though :(

What a pity :-)

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Ever try. Ever fail. No matter. Try again. Fail again.  Fail  better.
                                                        -- S. Beckett

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Sascha Hauer]

On Thu, Jul 10, 2008 at 11:46:45AM +0200, Wolfgang Denk wrote:
> In message <20080710093001.GR4595@pengutronix.de> you wrote:
> >
> > How about using the Linux clocksource framework for U-Boot? I did this
> 
> I have to admit that I don't know how big that code is?

Somewhere next to nothing:

/*
 * clock.c - generic clocksource implementation
 *
 * This file contains the clocksource implementation from the Linux
 * kernel originally by John Stultz
 *
 * Copyright (C) 2004, 2005 IBM, John Stultz (johnstul at us.ibm.com)
 * Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <common.h>
#include <asm-generic/div64.h>
#include <clock.h>

static struct clocksource *current_clock;
static uint64_t time_ns;

/**
 * get_time_ns - get current timestamp in nanoseconds
 */
uint64_t get_time_ns(void)
{
	struct clocksource *cs = current_clock;
        uint64_t cycle_now, cycle_delta;
        uint64_t ns_offset;

        /* read clocksource: */
        cycle_now = cs->read();

        /* calculate the delta since the last call: */
        cycle_delta = (cycle_now - cs->cycle_last) & cs->mask;

        /* convert to nanoseconds: */
        ns_offset = cyc2ns(cs, cycle_delta);

	cs->cycle_last = cycle_now;

	time_ns += ns_offset;
        return time_ns;
}
EXPORT_SYMBOL(get_time_ns);

/**
 * clocksource_hz2mult - calculates mult from hz and shift
 * @hz:                 Clocksource frequency in Hz
 * @shift_constant:     Clocksource shift factor
 *
 * Helper functions that converts a hz counter
 * frequency to a timsource multiplier, given the
 * clocksource shift value
 */
uint32_t clocksource_hz2mult(uint32_t hz, uint32_t shift_constant)
{
        /*  hz = cyc/(Billion ns)
         *  mult/2^shift  = ns/cyc
         *  mult = ns/cyc * 2^shift
         *  mult = 1Billion/hz * 2^shift
         *  mult = 1000000000 * 2^shift / hz
         *  mult = (1000000000<<shift) / hz
         */
        uint64_t tmp = ((uint64_t)1000000000) << shift_constant;

        tmp += hz/2; /* round for do_div */
        do_div(tmp, hz);

        return (uint32_t)tmp;
}

int is_timeout(uint64_t start_ns, uint64_t time_offset_ns)
{

	if (start_ns + time_offset_ns < get_time_ns())
		return 1;
	else
		return 0;
}
EXPORT_SYMBOL(is_timeout);

void udelay(unsigned long usecs)
{
	uint64_t start = get_time_ns();

	while(!is_timeout(start, usecs * 1000));
}
EXPORT_SYMBOL(udelay);

void mdelay(unsigned long msecs)
{
	uint64_t start = get_time_ns();

	while(!is_timeout(start, msecs * 1000000));
}
EXPORT_SYMBOL(mdelay);

int init_clock(struct clocksource *cs)
{
	current_clock = cs;
	return 0;
}

The clocksource driver itself adds another 100 lines of code (for mx31).
The implementation of udelay shows how to implement timeouts, the main
usage of timing functions.

Regards,
  Sascha



-- 
-- 
 Pengutronix - Linux Solutions for Science and Industry
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   Phone: +49-5121-206917-0 |  Fax: +49-5121-206917-9

[U-Boot-Users] [PATCH 04/10 v2] [ARM] TQMA31: add new board with i.MX31 processor

[Guennadi Liakhovetski]

On Thu, 10 Jul 2008, Jens Gehrlein wrote:

> Wolfgang Denk schrieb:
> > In message <4873845B.3020808@tqs.de> you wrote:
> >> The TQMA31, as well as the mx32ads use the General Purpose Timer 1, 
> >> which is feeded by a 32768 clock (possibly imx31_litekit and 
> >> imx31_phycore with 32000 Hz? I don't know.). The prescale divider can 
> >> only be an integer. 32768/1000 = non-integer.
> > 
> > I think other architectures hav / had similar issues. See for example
> > the MIPS fixes that were added some time ago.
> 
> I'll take a look.
> 
> 
> >> Currently, I see only one way to solve this:
> >> 1. Patch the common file cpu/arm1136/mx31/interrupts.c, function 
> >> interrupt_init(), so that the prescaler divides by 33.
> >> Alternatively, also make the divider a board specific define.
> >> 2. Patch all mx31 board config header files with CFG_HZ 1000.
> >> 3. All mx31 boards have to be tested.
> > 
> > Sounds like a plan.
> 
> What do you mean?
> It's just a proposal and I like to read comments from others, especially 
> those, who wrote this code.

Ok, let's fix it then. Unfortunately, I don't think I will have time for 
this _soon_, but I definitely will try to convret all i.MX31 platforms to 
CFG_HZ == 1000 ASAP. Jean-Christophe, what would you prefer, first accept 
patches as they are (i.e., with CFG_HZ ~= 1000) and then fix all i.MX31 
platforms or first fix the existing boards and then commit an updated 
patch with CFG_HZ == 1000?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de