[U-Boot] [patch] i.MX revise code in speed.c

Andrew Dyer
2008-08-26T22:35:56Z

This patch is for testing/comment - I have run it on our i.MX system,
but don't have an mx1ads, scb9328, or mx1fs2 board to play with.

1) pull common code for PLL calculations out of each function

2) add get_coreclk() to fetch the arm core frequency (we use for
printing core clock speed in checkboard() ), not currently used in
targets supported in git

3) use the frequencies of the board oscillators and register settings
to determine internal clocks rather than a #define

---
cpu/arm920t/cpu.c | 2 +-
cpu/arm920t/imx/speed.c | 77 +++++++++++++++++++++++++++++++++------------
include/common.h | 4 ++
include/configs/mx1ads.h | 4 +-
include/configs/mx1fs2.h | 7 ++--
include/configs/scb9328.h | 11 +-----
6 files changed, 69 insertions(+), 36 deletions(-)

diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index f93bf57..821685f 100644
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
#endif

/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
+unsigned long read_p15_c1 (void)
{
unsigned long value;

diff --git a/cpu/arm920t/imx/speed.c b/cpu/arm920t/imx/speed.c
index 1e29698..e2b7661 100644
--- a/cpu/arm920t/imx/speed.c
+++ b/cpu/arm920t/imx/speed.c
@@ -30,51 +30,72 @@
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- * SH FIXME: 16780000 in our case
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
*/
/* ------------------------------------------------------------------------- */

+static ulong calc_pll(u32 clkfreq, u32 ctlval)
+{
+ u32 pd = (ctlval >> 26) & 0xf;
+ u32 mfd = (ctlval >> 16) & 0x3ff;
+ u32 mfi = (ctlval >> 10) & 0xf;
+ u32 mfn = ctlval & 0x3ff;
+ long long tmp;
+
+ mfi = mfi<=5 ? 5 : mfi;
+
+ if (mfd == 0)
+ printf("ERROR: %s mfd==0\n", __FUNCTION__);
+ if (mfn == 0x3ff)
+ printf("ERROR: %s mfn==0x3ff\n", __FUNCTION__);
+
+ /* tmp is the pll multiplier factor scaled by 2^16 */
+ tmp = (long long)mfi << 16;
+ tmp += ((long long)mfn << 16)/((long long)mfd + 1);
+ tmp = tmp / ((long long)pd + 1);
+
+ tmp = 2 * (long long)clkfreq * tmp;
+ tmp = tmp >> 16;
+
+ return (ulong)tmp;
+}
+
ulong get_systemPLLCLK(void)
{
- /* FIXME: We assume System_SEL = 0 here */
u32 spctl0 = SPCTL0;
- u32 mfi = (spctl0 >> 10) & 0xf;
- u32 mfn = spctl0 & 0x3f;
- u32 mfd = (spctl0 >> 16) & 0x3f;
- u32 pd = (spctl0 >> 26) & 0xf;
+ u32 premclk;

- mfi = mfi<=5 ? 5 : mfi;
+ if (CSCR & CSCR_SYSTEM_SEL)
+ premclk = CONFIG_OSC16_FREQ;
+ else
+ premclk = (CONFIG_OSC32_FREQ * 512);

- return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+ return (calc_pll(premclk, spctl0));
}

-ulong get_mcuPLLCLK(void)
+static ulong get_mcuPLLCLK(void)
{
- /* FIXME: We assume System_SEL = 0 here */
u32 mpctl0 = MPCTL0;
- u32 mfi = (mpctl0 >> 10) & 0xf;
- u32 mfn = mpctl0 & 0x3f;
- u32 mfd = (mpctl0 >> 16) & 0x3f;
- u32 pd = (mpctl0 >> 26) & 0xf;
-
- mfi = mfi<=5 ? 5 : mfi;
+ u32 mcupll_clk = (CONFIG_OSC32_FREQ * 512);

- return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+ return (calc_pll(mcupll_clk, mpctl0));
}

ulong get_FCLK(void)
{
- return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
+ u32 mcupllclk = get_mcuPLLCLK();
+
+ if (CSCR & CSCR_MPU_PRESC)
+ mcupllclk >>= 1;
+
+ return mcupllclk;
}

/* return HCLK frequency */
ulong get_HCLK(void)
{
u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
- printf("bclkdiv: %d\n", bclkdiv);
return get_systemPLLCLK() / bclkdiv;
}

@@ -99,4 +120,20 @@ ulong get_PERCLK3(void)
return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
}

+ulong get_coreclk(void)
+{
+ u32 cp15_r1 = read_p15_c1();
+
+ switch (cp15_r1>>30) {
+ case 0:
+ case 1: return get_BCLK();
+ case 2: {
+ printf("Error - invalid clock mode 2 setting arm core cp15 r1!\n");
+ break;
+ }
+ case 3: return get_FCLK();
+ }
+
+ return 0;
+}
#endif /* defined (CONFIG_IMX) */
diff --git a/include/common.h b/include/common.h
index de3d595..a2a25d1 100644
--- a/include/common.h
+++ b/include/common.h
@@ -451,6 +451,9 @@ void ft_cpu_setup(void *blob, bd_t *bd);
void ft_pci_setup(void *blob, bd_t *bd);
#endif
#endif
+#ifdef CONFIG_IMX
+unsigned long read_p15_c1(void);
+#endif

/* $(CPU)/serial.c */
@@ -512,6 +515,7 @@ ulong get_BCLK(void);
ulong get_PERCLK1(void);
ulong get_PERCLK2(void);
ulong get_PERCLK3(void);
+ulong get_coreclk(void);
#endif
ulong get_bus_freq (ulong);

diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h
index 5125b21..84fc5ae 100644
--- a/include/configs/mx1ads.h
+++ b/include/configs/mx1ads.h
@@ -185,7 +185,7 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1

-#define CONFIG_SYS_CLK_FREQ 16780000
-#define CONFIG_SYSPLL_CLK_FREQ 16000000
+#define CONFIG_OSC32_FREQ 32768
+#define CONFIG_OSC16_FREQ 16000000

#endif /* __CONFIG_H */
diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h
index d527d09..5e8f7f5 100644
--- a/include/configs/mx1fs2.h
+++ b/include/configs/mx1fs2.h
@@ -257,6 +257,9 @@
#define CFG_PCDR_VAL 0x00010005
#define CFG_GPCR_VAL 0x00000FFB

+#define CONFIG_OSC32_FREQ 32768
+#define CONFIG_OSC16_FREQ 16000000
+
#define USE_16M_OSZI /* If you have one, you want to use it
The internal 32kHz oszillator jitters */
#ifdef USE_16M_OSZI
@@ -264,15 +267,11 @@
#define CFG_SPCTL0_VAL 0x04001401
#define CFG_SPCTL1_VAL 0x0C000040
#define CFG_CSCR_VAL 0x07030003
-#define CONFIG_SYS_CLK_FREQ 16780000
-#define CONFIG_SYSPLL_CLK_FREQ 16000000

#else

#define CFG_SPCTL0_VAL 0x07E716D1
#define CFG_CSCR_VAL 0x06000003
-#define CONFIG_SYS_CLK_FREQ 16780000
-#define CONFIG_SYSPLL_CLK_FREQ 16780000

#endif

diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
index 4ae25ad..206d9e8 100644
--- a/include/configs/scb9328.h
+++ b/include/configs/scb9328.h
@@ -326,15 +326,8 @@
*/
#define CFG_LOAD_ADDR 0x08400000

-#define MHZ16QUARZINUSE
-
-#ifdef MHZ16QUARZINUSE
-#define CONFIG_SYSPLL_CLK_FREQ 16000000
-#else
-#define CONFIG_SYSPLL_CLK_FREQ 16780000
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 16780000
+#define CONFIG_OSC32_FREQ 32000
+#define CONFIG_OSC16_FREQ 16000000

/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
#define CFG_FMCR_VAL 0x00000001
--
1.5.4.3