[U-Boot] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[U-Boot] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Heiko Schocher]

Hello,

[POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

tqm8272.c: In function 'upmnand_hwcontrol':
tqm8272.c:1086: warning: implicit declaration of function 'writeb'
tqm8272.c: In function 'board_nand_init':
tqm8272.c:1193: error: 'struct nand_chip' has no member named 'write_byte'
make[1]: *** [tqm8272.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [board/tqc/tqm8272/libtqm8272.a] Error 2

introduced from commit:

Update MTD to that of Linux 2.6.22.1

author  William Juul <william.juul@datarespons.no>
         Wed, 31 Oct 2007 12:53:06 +0000 (13:53 +0100)
committer       Scott Wood <scottwood@freescale.com>
         Tue, 12 Aug 2008 16:31:15 +0000 (11:31 -0500)
commit  cfa460adfdefcc30d104e1a9ee44994ee349bb7b

Couldnt try this patch, because I have no longer the Hardware :-(

Signed-off-by: Heiko Schocher <hs@denx.de>
---
 board/tqc/tqm8272/tqm8272.c |   35 ++++++++++-------------------------
 1 files changed, 10 insertions(+), 25 deletions(-)

diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c
index a0ec254..8b95143 100644
--- a/board/tqc/tqm8272/tqm8272.c
+++ b/board/tqc/tqm8272/tqm8272.c
@@ -1066,38 +1066,24 @@ int update_flash_size (int flash_size)
 #include <nand.h>
 #include <linux/mtd/mtd.h>

-static u8 hwctl = 0;
-
 static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	unsigned char byte = (unsigned char) cmd;

 	if (ctrl & NAND_CTRL_CHANGE) {
-		if ( ctrl & NAND_CLE )
-			hwctl |= 0x1;
-		else
-			hwctl &= ~0x1;
-		if ( ctrl & NAND_ALE )
-			hwctl |= 0x2;
-		else
-			hwctl &= ~0x2;
+		if ( ctrl & NAND_CLE ) {
+			WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
+			return ;
+		} else
+		if ( ctrl & NAND_ALE ) {
+			WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
+			return ;
+		}
 	}
 	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-
-	if (hwctl & 0x1) {
-		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
-	} else if (hwctl & 0x2) {
-		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
-	} else {
 		WRITE_NAND(byte, base);
-	}
 }

 static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
@@ -1190,7 +1176,6 @@ int board_nand_init(struct nand_chip *nand)

 	nand->cmd_ctrl	 = upmnand_hwcontrol;
 	nand->read_byte	 = upmnand_read_byte;
-	nand->write_byte = upmnand_write_byte;
 	nand->dev_ready	 = tqm8272_dev_ready;

 #ifndef CONFIG_NAND_SPL
-- 
1.5.6.1

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Stefan Roese]

Hi Heiko,

On Wednesday 27 August 2008, Heiko Schocher wrote:

<snip>

> +++ b/board/tqc/tqm8272/tqm8272.c
> @@ -1066,38 +1066,24 @@ int update_flash_size (int flash_size)
>  #include <nand.h>
>  #include <linux/mtd/mtd.h>
>
> -static u8 hwctl = 0;
> -
>  static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int
> ctrl) {
>  	struct nand_chip *this = mtd->priv;
> +	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
> +	unsigned char byte = (unsigned char) cmd;

You have integrated this NAND driver into the tqm8272.c source file. I suggest 
you move this at some time into the drivers/mtd/nand directory. Is it a 
TQM8272 specific driver? Or is this MPC8xxx specific? From the name of the 
functions (upm_xxx) this seems to match the already available driver under:

drivers/mtd/nand/fsl_upm.c

Is it possible that you can use this common FSL-UPM version?

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Heiko Schocher]

Hello Stefan,

Stefan Roese wrote:
> On Wednesday 27 August 2008, Heiko Schocher wrote:
> 
> <snip>
> 
>> +++ b/board/tqc/tqm8272/tqm8272.c
>> @@ -1066,38 +1066,24 @@ int update_flash_size (int flash_size)
>>  #include <nand.h>
>>  #include <linux/mtd/mtd.h>
>>
>> -static u8 hwctl = 0;
>> -
>>  static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int
>> ctrl) {
>>  	struct nand_chip *this = mtd->priv;
>> +	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
>> +	unsigned char byte = (unsigned char) cmd;
> 
> You have integrated this NAND driver into the tqm8272.c source file. I suggest 
> you move this at some time into the drivers/mtd/nand directory. Is it a 

Why? That are just the boardspecific routines, not a complete NAND driver!

> TQM8272 specific driver? Or is this MPC8xxx specific? From the name of the 
> functions (upm_xxx) this seems to match the already available driver under:
> 
> drivers/mtd/nand/fsl_upm.c
> 
> Is it possible that you can use this common FSL-UPM version?

Maybe this is posible, but without the Hardware to try this new
version, I dont like to make such a "big" change ...

bye
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Stefan Roese]

On Wednesday 27 August 2008, Heiko Schocher wrote:
> > You have integrated this NAND driver into the tqm8272.c source file. I
> > suggest you move this at some time into the drivers/mtd/nand directory.
> > Is it a
>
> Why? That are just the boardspecific routines, not a complete NAND driver!

It looks like a complete NAND driver to me. I'm referring to the CPU- / 
board-specific part of it. The part in:

#if defined(CONFIG_CMD_NAND)

#include <nand.h>
#include <linux/mtd/mtd.h>

static u8 hwctl = 0;
...

is what I'm talking about.

> > TQM8272 specific driver? Or is this MPC8xxx specific? From the name of
> > the functions (upm_xxx) this seems to match the already available driver
> > under:
> >
> > drivers/mtd/nand/fsl_upm.c
> >
> > Is it possible that you can use this common FSL-UPM version?
>
> Maybe this is posible, but without the Hardware to try this new
> version, I dont like to make such a "big" change ...

Understood. But at least extracting this driver into a separate file would 
help to identify this code as NAND driver. Just my 0.02 $.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH v2] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Heiko Schocher]

Hello,

[POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

tqm8272.c: In function 'upmnand_hwcontrol':
tqm8272.c:1086: warning: implicit declaration of function 'writeb'
tqm8272.c: In function 'board_nand_init':
tqm8272.c:1193: error: 'struct nand_chip' has no member named 'write_byte'
make[1]: *** [tqm8272.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [board/tqc/tqm8272/libtqm8272.a] Error 2

introduced from commit:

Update MTD to that of Linux 2.6.22.1

author  William Juul <william.juul@datarespons.no>
         Wed, 31 Oct 2007 12:53:06 +0000 (13:53 +0100)
committer       Scott Wood <scottwood@freescale.com>
         Tue, 12 Aug 2008 16:31:15 +0000 (11:31 -0500)
commit  cfa460adfdefcc30d104e1a9ee44994ee349bb7b

Also moved the NAND Code in a seperate File.

Couldnt try this patch, because I have no longer the Hardware  :-(

Signed-off-by: Heiko Schocher <hs@denx.de>
---

Update since last Patch:

- move NAND functions from tqm8272.c in seperate nand.c File

 board/tqc/tqm8272/Makefile  |    2 +-
 board/tqc/tqm8272/nand.c    |  266 +++++++++++++++++++++++++++++++++++++++++
 board/tqc/tqm8272/tqm8272.c |  277 +------------------------------------------
 board/tqc/tqm8272/tqm8272.h |   51 ++++++++
 4 files changed, 319 insertions(+), 277 deletions(-)
 create mode 100644 board/tqc/tqm8272/nand.c
 create mode 100644 board/tqc/tqm8272/tqm8272.h

diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile
index 6730263..c97fe14 100644
--- a/board/tqc/tqm8272/Makefile
+++ b/board/tqc/tqm8272/Makefile
@@ -28,7 +28,7 @@ endif

 LIB	= $(obj)lib$(BOARD).a

-COBJS	= $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
+COBJS	= $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o nand.o

 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c
new file mode 100644
index 0000000..21cb445
--- /dev/null
+++ b/board/tqc/tqm8272/nand.c
@@ -0,0 +1,266 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <command.h>
+#include "tqm8272.h"
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+#define _NOT_USED_	0xFFFFFFFF
+
+static int	chipsel = 0;
+
+/* UPM pattern for bus clock = 66.7 MHz */
+static const uint upmTable67[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
+    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
+    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 100 MHz */
+static const uint upmTable100[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
+    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
+    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 133.3 MHz */
+static const uint upmTable133[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
+    /* 0x04 */	0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
+    /* 0x1C */	0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+static void upmnand_hwcontrol (struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	unsigned char byte = (unsigned char) cmd;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE ) {
+			WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
+			return ;
+		} else
+		if ( ctrl & NAND_ALE ) {
+			WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
+			return ;
+		}
+	}
+	if (cmd != NAND_CMD_NONE)
+		WRITE_NAND(byte, base);
+}
+
+static u_char upmnand_read_byte (struct mtd_info *mtdinfo)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+
+	return READ_NAND(base);
+}
+
+static int tqm8272_dev_ready (struct mtd_info *mtdinfo)
+{
+	/* constant delay (see also tR in the datasheet) */
+	udelay (12);
+	return 1;
+}
+
+#ifndef CONFIG_NAND_SPL
+static void tqm8272_read_buf (struct mtd_info *mtdinfo, uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i< len; i++)
+		buf[i] = *base;
+}
+
+static void tqm8272_write_buf (struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i< len; i++)
+		*base = buf[i];
+}
+
+static int tqm8272_verify_buf (struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i < len; i++)
+		if (buf[i] != *base)
+			return -1;
+	return 0;
+}
+#endif /* #ifndef CONFIG_NAND_SPL */
+
+void board_nand_select_device (struct nand_chip *nand, int chip)
+{
+	chipsel = chip;
+}
+
+int board_nand_init (struct nand_chip *nand)
+{
+	static	int	UpmInit = 0;
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+
+	if (hwinf.nand == 0) return -1;
+
+	/* Setup the UPM */
+	if (UpmInit == 0) {
+		switch (hwinf.busclk_real) {
+		case 100000000:
+			upmconfig (UPMB, (uint *) upmTable100,
+			   sizeof (upmTable100) / sizeof (uint));
+			break;
+		case 133333333:
+			upmconfig (UPMB, (uint *) upmTable133,
+			   sizeof (upmTable133) / sizeof (uint));
+			break;
+		default:
+			upmconfig (UPMB, (uint *) upmTable67,
+			   sizeof (upmTable67) / sizeof (uint));
+			break;
+		}
+		UpmInit = 1;
+	}
+
+	/* Setup the memctrl */
+	memctl->memc_or3 = CFG_NAND_OR;
+	memctl->memc_br3 = CFG_NAND_BR;
+	memctl->memc_mbmr = (MxMR_OP_NORM);
+
+	nand->ecc.mode = NAND_ECC_SOFT;
+
+	nand->cmd_ctrl	 = upmnand_hwcontrol;
+	nand->read_byte	 = upmnand_read_byte;
+	nand->dev_ready	 = tqm8272_dev_ready;
+
+#ifndef CONFIG_NAND_SPL
+	nand->write_buf	 = tqm8272_write_buf;
+	nand->read_buf	 = tqm8272_read_buf;
+	nand->verify_buf = tqm8272_verify_buf;
+#endif
+
+	/*
+	 * Select required NAND chip
+	 */
+	board_nand_select_device (nand, 0);
+	return 0;
+}
+
+#endif
diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c
index a0ec254..76260c1 100644
--- a/board/tqc/tqm8272/tqm8272.c
+++ b/board/tqc/tqm8272/tqm8272.c
@@ -30,6 +30,7 @@
 #include <pci.h>
 #include <asm/m8260_pci.h>
 #endif
+#include "tqm8272.h"

 #if 0
 #define deb_printf(fmt,arg...) \
@@ -209,110 +210,6 @@ const iop_conf_t iop_conf_tab[4][32] = {

 #define _NOT_USED_	0xFFFFFFFF

-/* UPM pattern for bus clock = 66.7 MHz */
-static const uint upmTable67[] =
-{
-    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
-    /* 0x00 */	0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
-    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
-    /* 0x18 */	0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
-    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unsused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 100 MHz */
-static const uint upmTable100[] =
-{
-    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
-    /* 0x00 */	0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
-    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
-    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
-    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unsused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 133.3 MHz */
-static const uint upmTable133[] =
-{
-    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
-    /* 0x00 */	0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
-    /* 0x04 */	0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
-    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
-    /* 0x1C */	0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unsused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-static int	chipsel = 0;
-
 /* UPM pattern for slow init */
 static const uint upmTableSlow[] =
 {
@@ -615,31 +512,6 @@ static inline int scanChar (char *p, int len, unsigned long *number)
 	return akt;
 }

-typedef struct{
-	int	Bus;
-	int	flash;
-	int	flash_nr;
-	int	ram;
-	int	ram_cs;
-	int	nand;
-	int	nand_cs;
-	int	eeprom;
-	int	can;
-	unsigned long	cpunr;
-	unsigned long	option;
-	int	SecEng;
-	int	cpucl;
-	int	cpmcl;
-	int	buscl;
-	int	busclk_real_ok;
-	int	busclk_real;
-	unsigned char	OK;
-	unsigned char  ethaddr[20];
-} HWIB_INFO;
-
-HWIB_INFO	hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
-			 0, 0, 0, 0, 0, 0};
-
 static int dump_hwib(void)
 {
 	HWIB_INFO	*hw = &hwinf;
@@ -1061,153 +933,6 @@ int update_flash_size (int flash_size)
 }
 #endif

-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-#include <linux/mtd/mtd.h>
-
-static u8 hwctl = 0;
-
-static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd->priv;
-
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if ( ctrl & NAND_CLE )
-			hwctl |= 0x1;
-		else
-			hwctl &= ~0x1;
-		if ( ctrl & NAND_ALE )
-			hwctl |= 0x2;
-		else
-			hwctl &= ~0x2;
-	}
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-
-	if (hwctl & 0x1) {
-		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
-	} else if (hwctl & 0x2) {
-		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
-	} else {
-		WRITE_NAND(byte, base);
-	}
-}
-
-static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-
-	return READ_NAND(base);
-}
-
-static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
-{
-	/* constant delay (see also tR in the datasheet) */
-	udelay(12); \
-	return 1;
-}
-
-#ifndef CONFIG_NAND_SPL
-static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-	int	i;
-
-	for (i = 0; i< len; i++)
-		buf[i] = *base;
-}
-
-static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-	int	i;
-
-	for (i = 0; i< len; i++)
-		*base = buf[i];
-}
-
-static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-	int	i;
-
-	for (i = 0; i < len; i++)
-		if (buf[i] != *base)
-			return -1;
-	return 0;
-}
-#endif /* #ifndef CONFIG_NAND_SPL */
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
-	chipsel = chip;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	static	int	UpmInit = 0;
-	volatile immap_t * immr = (immap_t *)CFG_IMMR;
-	volatile memctl8260_t *memctl = &immr->im_memctl;
-
-	if (hwinf.nand == 0) return -1;
-
-	/* Setup the UPM */
-	if (UpmInit == 0) {
-		switch (hwinf.busclk_real) {
-		case 100000000:
-			upmconfig (UPMB, (uint *) upmTable100,
-			   sizeof (upmTable100) / sizeof (uint));
-			break;
-		case 133333333:
-			upmconfig (UPMB, (uint *) upmTable133,
-			   sizeof (upmTable133) / sizeof (uint));
-			break;
-		default:
-			upmconfig (UPMB, (uint *) upmTable67,
-			   sizeof (upmTable67) / sizeof (uint));
-			break;
-		}
-		UpmInit = 1;
-	}
-
-	/* Setup the memctrl */
-	memctl->memc_or3 = CFG_NAND_OR;
-	memctl->memc_br3 = CFG_NAND_BR;
-	memctl->memc_mbmr = (MxMR_OP_NORM);
-
-	nand->ecc.mode = NAND_ECC_SOFT;
-
-	nand->cmd_ctrl	 = upmnand_hwcontrol;
-	nand->read_byte	 = upmnand_read_byte;
-	nand->write_byte = upmnand_write_byte;
-	nand->dev_ready	 = tqm8272_dev_ready;
-
-#ifndef CONFIG_NAND_SPL
-	nand->write_buf	 = tqm8272_write_buf;
-	nand->read_buf	 = tqm8272_read_buf;
-	nand->verify_buf = tqm8272_verify_buf;
-#endif
-
-	/*
-	 * Select required NAND chip
-	 */
-	board_nand_select_device(nand, 0);
-	return 0;
-}
-
-#endif
-
 #ifdef CONFIG_PCI
 struct pci_controller hose;

diff --git a/board/tqc/tqm8272/tqm8272.h b/board/tqc/tqm8272/tqm8272.h
new file mode 100644
index 0000000..e2f47db
--- /dev/null
+++ b/board/tqc/tqm8272/tqm8272.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	_TQM8272_HEADER_H
+#define _TQM8272_HEADER_H
+
+typedef struct{
+	int	Bus;
+	int	flash;
+	int	flash_nr;
+	int	ram;
+	int	ram_cs;
+	int	nand;
+	int	nand_cs;
+	int	eeprom;
+	int	can;
+	unsigned long	cpunr;
+	unsigned long	option;
+	int	SecEng;
+	int	cpucl;
+	int	cpmcl;
+	int	buscl;
+	int	busclk_real_ok;
+	int	busclk_real;
+	unsigned char	OK;
+	unsigned char  ethaddr[20];
+} HWIB_INFO;
+
+static HWIB_INFO	hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
+			 0, 0, 0, 0, 0, 0};
+#endif
-- 
1.5.6.1

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Scott Wood]

On Wed, Aug 27, 2008 at 01:08:14PM +0200, Heiko Schocher wrote:
>  static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
>  {
>  	struct nand_chip *this = mtd->priv;
> +	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
> +	unsigned char byte = (unsigned char) cmd;
> 
>  	if (ctrl & NAND_CTRL_CHANGE) {
> -		if ( ctrl & NAND_CLE )
> -			hwctl |= 0x1;
> -		else
> -			hwctl &= ~0x1;
> -		if ( ctrl & NAND_ALE )
> -			hwctl |= 0x2;
> -		else
> -			hwctl &= ~0x2;
> +		if ( ctrl & NAND_CLE ) {
> +			WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
> +			return ;
> +		} else
> +		if ( ctrl & NAND_ALE ) {
> +			WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
> +			return ;

You shouldn't be writing any bytes unless cmd != NAND_CMD_NONE.

As Stefan pointed out, is there any reason you can't use
drivers/mtd/nand/fsl_upm.c?

-Scott

[U-Boot] [PATCH v2] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Scott Wood]

On Wed, Aug 27, 2008 at 08:37:22PM +0200, Heiko Schocher wrote:
> [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.
> 
> tqm8272.c: In function 'upmnand_hwcontrol':
> tqm8272.c:1086: warning: implicit declaration of function 'writeb'
> tqm8272.c: In function 'board_nand_init':
> tqm8272.c:1193: error: 'struct nand_chip' has no member named 'write_byte'
> make[1]: *** [tqm8272.o] Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [board/tqc/tqm8272/libtqm8272.a] Error 2
> 
> introduced from commit:
> 
> Update MTD to that of Linux 2.6.22.1
> 
> author  William Juul <william.juul@datarespons.no>
>          Wed, 31 Oct 2007 12:53:06 +0000 (13:53 +0100)
> committer       Scott Wood <scottwood@freescale.com>
>          Tue, 12 Aug 2008 16:31:15 +0000 (11:31 -0500)
> commit  cfa460adfdefcc30d104e1a9ee44994ee349bb7b
> 
> Also moved the NAND Code in a seperate File.

Please don't do these in the same patch -- especially if you do not use
the -M flag with git-format-patch.  It makes it difficult to see what was
changed.

-Scott

[U-Boot] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Heiko Schocher]

Hello Scott,

Scott Wood wrote:
> On Wed, Aug 27, 2008 at 01:08:14PM +0200, Heiko Schocher wrote:
>>  static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
>>  {
>>  	struct nand_chip *this = mtd->priv;
>> +	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
>> +	unsigned char byte = (unsigned char) cmd;
>>
>>  	if (ctrl & NAND_CTRL_CHANGE) {
>> -		if ( ctrl & NAND_CLE )
>> -			hwctl |= 0x1;
>> -		else
>> -			hwctl &= ~0x1;
>> -		if ( ctrl & NAND_ALE )
>> -			hwctl |= 0x2;
>> -		else
>> -			hwctl &= ~0x2;
>> +		if ( ctrl & NAND_CLE ) {
>> +			WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
>> +			return ;
>> +		} else
>> +		if ( ctrl & NAND_ALE ) {
>> +			WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
>> +			return ;
> 
> You shouldn't be writing any bytes unless cmd != NAND_CMD_NONE.

Ah, okay ...

> As Stefan pointed out, is there any reason you can't use
> drivers/mtd/nand/fsl_upm.c?

Yes, as I wrote to Stefan, I have no longer the Hardware and I fear
such a big change ...

bye
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH v3] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Heiko Schocher]

Hello,

[POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

tqm8272.c: In function 'upmnand_hwcontrol':
tqm8272.c:1086: warning: implicit declaration of function 'writeb'
tqm8272.c: In function 'board_nand_init':
tqm8272.c:1193: error: 'struct nand_chip' has no member named 'write_byte'
make[1]: *** [tqm8272.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [board/tqc/tqm8272/libtqm8272.a] Error 2

introduced from commit:

Update MTD to that of Linux 2.6.22.1

author  William Juul <william.juul@datarespons.no>
         Wed, 31 Oct 2007 12:53:06 +0000 (13:53 +0100)
committer       Scott Wood <scottwood@freescale.com>
         Tue, 12 Aug 2008 16:31:15 +0000 (11:31 -0500)
commit  cfa460adfdefcc30d104e1a9ee44994ee349bb7b

Signed-off-by: Heiko Schocher <hs@denx.de>
---
 board/tqc/tqm8272/tqm8272.c |   33 +++++++++++++++------------------
 1 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c
index a0ec254..a3d37f6 100644
--- a/board/tqc/tqm8272/tqm8272.c
+++ b/board/tqc/tqm8272/tqm8272.c
@@ -1068,10 +1068,22 @@ int update_flash_size (int flash_size)

 static u8 hwctl = 0;

-static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);

+	if (hwctl & 0x1) {
+		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
+	} else if (hwctl & 0x2) {
+		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
+	} else {
+		WRITE_NAND(byte, base);
+	}
+}
+
+static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
 	if (ctrl & NAND_CTRL_CHANGE) {
 		if ( ctrl & NAND_CLE )
 			hwctl |= 0x1;
@@ -1083,21 +1095,7 @@ static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 			hwctl &= ~0x2;
 	}
 	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-
-	if (hwctl & 0x1) {
-		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
-	} else if (hwctl & 0x2) {
-		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
-	} else {
-		WRITE_NAND(byte, base);
-	}
+		upmnand_write_byte (mtd, cmd);
 }

 static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
@@ -1190,7 +1188,6 @@ int board_nand_init(struct nand_chip *nand)

 	nand->cmd_ctrl	 = upmnand_hwcontrol;
 	nand->read_byte	 = upmnand_read_byte;
-	nand->write_byte = upmnand_write_byte;
 	nand->dev_ready	 = tqm8272_dev_ready;

 #ifndef CONFIG_NAND_SPL
-- 
1.5.6.1


-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH][POWERPC] TQM8272: move NAND part in seperate File

[Heiko Schocher]

Hello,

[POWERPC] TQM8272: move NAND part in seperate File

I didnt try to use drivers/mtd/nand/fsl_upm.c for the
NAND driver, because I have no longer the Hardware.

Signed-off-by: Heiko Schocher <hs@denx.de>
---
 board/tqc/tqm8272/Makefile  |    2 +-
 board/tqc/tqm8272/nand.c    |  276 +++++++++++++++++++++++++++++++++++++++++++
 board/tqc/tqm8272/tqm8272.c |  276 +------------------------------------------
 board/tqc/tqm8272/tqm8272.h |   53 ++++++++
 4 files changed, 331 insertions(+), 276 deletions(-)
 create mode 100644 board/tqc/tqm8272/nand.c
 create mode 100644 board/tqc/tqm8272/tqm8272.h

diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile
index 6730263..c97fe14 100644
--- a/board/tqc/tqm8272/Makefile
+++ b/board/tqc/tqm8272/Makefile
@@ -28,7 +28,7 @@ endif

 LIB	= $(obj)lib$(BOARD).a

-COBJS	= $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
+COBJS	= $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o nand.o

 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c
new file mode 100644
index 0000000..b988ffa
--- /dev/null
+++ b/board/tqc/tqm8272/nand.c
@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+#include "tqm8272.h"
+
+/* UPM pattern for bus clock = 66.7 MHz */
+static const uint upmTable67[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
+    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
+    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 100 MHz */
+static const uint upmTable100[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
+    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
+    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 133.3 MHz */
+static const uint upmTable133[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
+    /* 0x04 */	0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
+    /* 0x1C */	0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+static int	chipsel = 0;
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+static u8 hwctl = 0;
+
+static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+
+	if (hwctl & 0x1) {
+		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
+	} else if (hwctl & 0x2) {
+		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
+	} else {
+		WRITE_NAND(byte, base);
+	}
+}
+
+static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			hwctl |= 0x1;
+		else
+			hwctl &= ~0x1;
+		if ( ctrl & NAND_ALE )
+			hwctl |= 0x2;
+		else
+			hwctl &= ~0x2;
+	}
+	if (cmd != NAND_CMD_NONE)
+		upmnand_write_byte (mtd, cmd);
+}
+
+static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+
+	return READ_NAND(base);
+}
+
+static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
+{
+	/* constant delay (see also tR in the datasheet) */
+	udelay(12); \
+	return 1;
+}
+
+#ifndef CONFIG_NAND_SPL
+static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i< len; i++)
+		buf[i] = *base;
+}
+
+static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i< len; i++)
+		*base = buf[i];
+}
+
+static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i < len; i++)
+		if (buf[i] != *base)
+			return -1;
+	return 0;
+}
+#endif /* #ifndef CONFIG_NAND_SPL */
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+	chipsel = chip;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	static	int	UpmInit = 0;
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+
+	if (hwinf.nand == 0) return -1;
+
+	/* Setup the UPM */
+	if (UpmInit == 0) {
+		switch (hwinf.busclk_real) {
+		case 100000000:
+			upmconfig (UPMB, (uint *) upmTable100,
+			   sizeof (upmTable100) / sizeof (uint));
+			break;
+		case 133333333:
+			upmconfig (UPMB, (uint *) upmTable133,
+			   sizeof (upmTable133) / sizeof (uint));
+			break;
+		default:
+			upmconfig (UPMB, (uint *) upmTable67,
+			   sizeof (upmTable67) / sizeof (uint));
+			break;
+		}
+		UpmInit = 1;
+	}
+
+	/* Setup the memctrl */
+	memctl->memc_or3 = CFG_NAND_OR;
+	memctl->memc_br3 = CFG_NAND_BR;
+	memctl->memc_mbmr = (MxMR_OP_NORM);
+
+	nand->ecc.mode = NAND_ECC_SOFT;
+
+	nand->cmd_ctrl	 = upmnand_hwcontrol;
+	nand->read_byte	 = upmnand_read_byte;
+	nand->dev_ready	 = tqm8272_dev_ready;
+
+#ifndef CONFIG_NAND_SPL
+	nand->write_buf	 = tqm8272_write_buf;
+	nand->read_buf	 = tqm8272_read_buf;
+	nand->verify_buf = tqm8272_verify_buf;
+#endif
+
+	/*
+	 * Select required NAND chip
+	 */
+	board_nand_select_device(nand, 0);
+	return 0;
+}
+
+#endif
diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c
index a3d37f6..c7a1ff9 100644
--- a/board/tqc/tqm8272/tqm8272.c
+++ b/board/tqc/tqm8272/tqm8272.c
@@ -30,6 +30,7 @@
 #include <pci.h>
 #include <asm/m8260_pci.h>
 #endif
+#include "tqm8272.h"

 #if 0
 #define deb_printf(fmt,arg...) \
@@ -207,112 +208,6 @@ const iop_conf_t iop_conf_tab[4][32] = {
     }
 };

-#define _NOT_USED_	0xFFFFFFFF
-
-/* UPM pattern for bus clock = 66.7 MHz */
-static const uint upmTable67[] =
-{
-    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
-    /* 0x00 */	0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
-    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
-    /* 0x18 */	0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
-    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unsused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 100 MHz */
-static const uint upmTable100[] =
-{
-    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
-    /* 0x00 */	0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
-    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
-    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
-    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unsused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 133.3 MHz */
-static const uint upmTable133[] =
-{
-    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
-    /* 0x00 */	0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
-    /* 0x04 */	0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Read Burst RAM array entry -> unused */
-    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
-    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
-    /* 0x1C */	0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
-
-		/* UPM Write Burst RAM array entry -> unused */
-    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Refresh Timer RAM array entry -> unused */
-    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-		/* UPM Exception RAM array entry -> unsused */
-    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-static int	chipsel = 0;
-
 /* UPM pattern for slow init */
 static const uint upmTableSlow[] =
 {
@@ -615,31 +510,6 @@ static inline int scanChar (char *p, int len, unsigned long *number)
 	return akt;
 }

-typedef struct{
-	int	Bus;
-	int	flash;
-	int	flash_nr;
-	int	ram;
-	int	ram_cs;
-	int	nand;
-	int	nand_cs;
-	int	eeprom;
-	int	can;
-	unsigned long	cpunr;
-	unsigned long	option;
-	int	SecEng;
-	int	cpucl;
-	int	cpmcl;
-	int	buscl;
-	int	busclk_real_ok;
-	int	busclk_real;
-	unsigned char	OK;
-	unsigned char  ethaddr[20];
-} HWIB_INFO;
-
-HWIB_INFO	hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
-			 0, 0, 0, 0, 0, 0};
-
 static int dump_hwib(void)
 {
 	HWIB_INFO	*hw = &hwinf;
@@ -1061,150 +931,6 @@ int update_flash_size (int flash_size)
 }
 #endif

-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-#include <linux/mtd/mtd.h>
-
-static u8 hwctl = 0;
-
-static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-
-	if (hwctl & 0x1) {
-		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
-	} else if (hwctl & 0x2) {
-		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
-	} else {
-		WRITE_NAND(byte, base);
-	}
-}
-
-static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if ( ctrl & NAND_CLE )
-			hwctl |= 0x1;
-		else
-			hwctl &= ~0x1;
-		if ( ctrl & NAND_ALE )
-			hwctl |= 0x2;
-		else
-			hwctl &= ~0x2;
-	}
-	if (cmd != NAND_CMD_NONE)
-		upmnand_write_byte (mtd, cmd);
-}
-
-static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-
-	return READ_NAND(base);
-}
-
-static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
-{
-	/* constant delay (see also tR in the datasheet) */
-	udelay(12); \
-	return 1;
-}
-
-#ifndef CONFIG_NAND_SPL
-static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-	int	i;
-
-	for (i = 0; i< len; i++)
-		buf[i] = *base;
-}
-
-static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-	int	i;
-
-	for (i = 0; i< len; i++)
-		*base = buf[i];
-}
-
-static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
-	int	i;
-
-	for (i = 0; i < len; i++)
-		if (buf[i] != *base)
-			return -1;
-	return 0;
-}
-#endif /* #ifndef CONFIG_NAND_SPL */
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
-	chipsel = chip;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	static	int	UpmInit = 0;
-	volatile immap_t * immr = (immap_t *)CFG_IMMR;
-	volatile memctl8260_t *memctl = &immr->im_memctl;
-
-	if (hwinf.nand == 0) return -1;
-
-	/* Setup the UPM */
-	if (UpmInit == 0) {
-		switch (hwinf.busclk_real) {
-		case 100000000:
-			upmconfig (UPMB, (uint *) upmTable100,
-			   sizeof (upmTable100) / sizeof (uint));
-			break;
-		case 133333333:
-			upmconfig (UPMB, (uint *) upmTable133,
-			   sizeof (upmTable133) / sizeof (uint));
-			break;
-		default:
-			upmconfig (UPMB, (uint *) upmTable67,
-			   sizeof (upmTable67) / sizeof (uint));
-			break;
-		}
-		UpmInit = 1;
-	}
-
-	/* Setup the memctrl */
-	memctl->memc_or3 = CFG_NAND_OR;
-	memctl->memc_br3 = CFG_NAND_BR;
-	memctl->memc_mbmr = (MxMR_OP_NORM);
-
-	nand->ecc.mode = NAND_ECC_SOFT;
-
-	nand->cmd_ctrl	 = upmnand_hwcontrol;
-	nand->read_byte	 = upmnand_read_byte;
-	nand->dev_ready	 = tqm8272_dev_ready;
-
-#ifndef CONFIG_NAND_SPL
-	nand->write_buf	 = tqm8272_write_buf;
-	nand->read_buf	 = tqm8272_read_buf;
-	nand->verify_buf = tqm8272_verify_buf;
-#endif
-
-	/*
-	 * Select required NAND chip
-	 */
-	board_nand_select_device(nand, 0);
-	return 0;
-}
-
-#endif
-
 #ifdef CONFIG_PCI
 struct pci_controller hose;

diff --git a/board/tqc/tqm8272/tqm8272.h b/board/tqc/tqm8272/tqm8272.h
new file mode 100644
index 0000000..6d558ec
--- /dev/null
+++ b/board/tqc/tqm8272/tqm8272.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	_TQM8272_HEADER_H
+#define	_TQM8272_HEADER_H
+
+#define _NOT_USED_	0xFFFFFFFF
+
+typedef struct{
+	int	Bus;
+	int	flash;
+	int	flash_nr;
+	int	ram;
+	int	ram_cs;
+	int	nand;
+	int	nand_cs;
+	int	eeprom;
+	int	can;
+	unsigned long	cpunr;
+	unsigned long	option;
+	int	SecEng;
+	int	cpucl;
+	int	cpmcl;
+	int	buscl;
+	int	busclk_real_ok;
+	int	busclk_real;
+	unsigned char	OK;
+	unsigned char  ethaddr[20];
+} HWIB_INFO;
+
+static HWIB_INFO	hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
+			 0, 0, 0, 0, 0, 0};
+#endif
-- 
1.5.6.1

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH v2] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Wolfgang Denk]

Dear Heiko Schocher,

In message <48B59EE2.8090504@denx.de> you wrote:
> Hello,
> 
> [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.
> 
> tqm8272.c: In function 'upmnand_hwcontrol':
> tqm8272.c:1086: warning: implicit declaration of function 'writeb'
> tqm8272.c: In function 'board_nand_init':
> tqm8272.c:1193: error: 'struct nand_chip' has no member named 'write_byte'
> make[1]: *** [tqm8272.o] Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [board/tqc/tqm8272/libtqm8272.a] Error 2
> 
> introduced from commit:
> 
> Update MTD to that of Linux 2.6.22.1
> 
> author  William Juul <william.juul@datarespons.no>
>          Wed, 31 Oct 2007 12:53:06 +0000 (13:53 +0100)
> committer       Scott Wood <scottwood@freescale.com>
>          Tue, 12 Aug 2008 16:31:15 +0000 (11:31 -0500)
> commit  cfa460adfdefcc30d104e1a9ee44994ee349bb7b
> 
> Also moved the NAND Code in a seperate File.
> 
> Couldnt try this patch, because I have no longer the Hardware  :-(
> 
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---

Applied (with slightly edited commit messages).

Please keep in mind that all commets should go *below* the '---' line.

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Faith: not *wanting* to know what is true."    - Friedrich Nietzsche

[U-Boot] [PATCH v3] [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.

[Wolfgang Denk]

Dear Heiko Schocher,

In message <48B69094.3030103@denx.de> you wrote:
> Hello,
> 
> [POWERPC] TQM8272: Fix compiling error for the TQM8272 board.
> 
> tqm8272.c: In function 'upmnand_hwcontrol':
> tqm8272.c:1086: warning: implicit declaration of function 'writeb'
> tqm8272.c: In function 'board_nand_init':
> tqm8272.c:1193: error: 'struct nand_chip' has no member named 'write_byte'
> make[1]: *** [tqm8272.o] Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [board/tqc/tqm8272/libtqm8272.a] Error 2
> 
> introduced from commit:
> 
> Update MTD to that of Linux 2.6.22.1
> 
> author  William Juul <william.juul@datarespons.no>
>          Wed, 31 Oct 2007 12:53:06 +0000 (13:53 +0100)
> committer       Scott Wood <scottwood@freescale.com>
>          Tue, 12 Aug 2008 16:31:15 +0000 (11:31 -0500)
> commit  cfa460adfdefcc30d104e1a9ee44994ee349bb7b
> 
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
>  board/tqc/tqm8272/tqm8272.c |   33 +++++++++++++++------------------
>  1 files changed, 15 insertions(+), 18 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
ATTENTION: Despite Any Other Listing of Product Contents Found  Here-
on, the Consumer is Advised That, in Actuality, This Product Consists
Of 99.9999999999% Empty Space.

[U-Boot] [PATCH][POWERPC] TQM8272: move NAND part in seperate File

[Wolfgang Denk]

Dear Heiko Schocher,

In message <48B69112.3030903@denx.de> you wrote:
> Hello,
> 
> [POWERPC] TQM8272: move NAND part in seperate File
> 
> I didnt try to use drivers/mtd/nand/fsl_upm.c for the
> NAND driver, because I have no longer the Hardware.
> 
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
>  board/tqc/tqm8272/Makefile  |    2 +-
>  board/tqc/tqm8272/nand.c    |  276 +++++++++++++++++++++++++++++++++++++++++++
>  board/tqc/tqm8272/tqm8272.c |  276 +------------------------------------------
>  board/tqc/tqm8272/tqm8272.h |   53 ++++++++
>  4 files changed, 331 insertions(+), 276 deletions(-)
>  create mode 100644 board/tqc/tqm8272/nand.c
>  create mode 100644 board/tqc/tqm8272/tqm8272.h

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Premature optimization is the root of all evil.         -- D.E. Knuth