* [U-Boot-Users] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
@ 2008-08-07 11:03 thaoth
2008-08-08 1:35 ` Nobuhiro Iwamatsu
0 siblings, 1 reply; 20+ messages in thread
From: thaoth @ 2008-08-07 11:03 UTC (permalink / raw)
To: u-boot
Dear All,
I would like to port a Uboot loader on T-Engine/SH7727 MS7727CP02 DevKit.
Here is the configuration of this board
Renesas Technology SH7727(SH3-DSP, internal clock 96MHz / external clock
48MHz)
Flash Memory: 8MB
SDRAM: 32MB
Memory map of overall system is shown as below.
0x00000000 +-------------------------------+--------
| User area (P0)|
0x10000000 +-------------------------------+
| (Unused) (P0)| Enabled as a virtual
memory
0x40000000 +-------------------------------+
| System / Common area(1) (P0)|
0x80000000 +-------------------------------+--------
| Physical memory area (P1) |
| (Cache On) |
0xa0000000 +-------------------------------+
| Physical memory area (P2) |
| (Cache Off) |
0xc0000000 +-------------------------------+--------
| System/Common area(2) (P3) | Enabled as a virtual
memory
0xe0000000 +-------------------------------+--------
| I/O area (P4) |
0xffffffff +-------------------------------+
Physical memory area (P1 area) memory map is shown as below.
0x80000000 +-------------------------------+--------
| ROM area(8MB) | Area 0
| (Unused area included) |
0x84000000 +-------------------------------+--------
| I/O area | Area 1-2
| (Not used as a general rule)|
0x8c000000 +-------------------------------+--------
| RAM area(64MB) | Area 3
0x90000000 +-------------------------------+--------
| I/O area | Area 4-7
| (Not used as a general rule)|
0xa0000000 +-------------------------------+--------
Here is configuration of UBoot
\board\ms7727se\config.mk : TEXT_BASE = 0x8DFC0000
\board\ms7727se\u-boot.lds
OUTPUT_FORMAT("elf32-sh-tkernel", "elf32-sh-tkernel", "elf32-sh-tkernel")
SECTIONS
{
. = 0x8C000000 + (32*1024*1024) - (256*1024);
\include\configs\ms7727se.h
/* MEMORY */
#define MS7720SE_SDRAM_BASE 0x8C000000
#define MS7720SE_FLASH_BASE_1 0x80000000 //0xA0000000
#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
#define CFG_MEMTEST_START MS7720SE_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
#define CFG_SDRAM_BASE MS7720SE_SDRAM_BASE
#define CFG_SDRAM_SIZE (32 * 1024 * 1024)
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
#define CFG_MONITOR_BASE MS7720SE_FLASH_BASE_1
#define CFG_MONITOR_LEN (128 * 1024)
#define CFG_MALLOC_LEN (256 * 1024)
#define CFG_GBL_DATA_SIZE 256
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#undef CFG_FLASH_QUIET_TEST
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_BASE MS7720SE_FLASH_BASE_1
Would you please help me have a look this setting?
1. Is this setting correct ? I am confusing about TEXT_BASE with
CFG_LOAD_ADDR. Here is definition
- CFG_FLASH_BASE:
Physical start address of Flash memory.
- CFG_MONITOR_BASE:
Physical start address of boot monitor code (set by
make config files to be same as the text base address
(TEXT_BASE) used when linking) - same as
CFG_FLASH_BASE when booting from flash.
If I am wrong, please tell me how to correct these setting.
2. "ld" T-Engine toolchain only supports elf32-sh-tkernel target, but
reference implementation (example) tell "elf32-sh-linux" is expected target.
Is the setting correct?
\board\ms7727se\u-boot.lds
Original :
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-> My changes
OUTPUT_FORMAT("elf32-sh-tkernel", "elf32-sh-tkernel", "elf32-sh-tkernel")
I am newbie in embedded system. I am appreciating your helping.
Thank you a lot.
--
View this message in context: http://www.nabble.com/-T-Engine--UBoot-configuration-for-T-Engine-SH7727-MS7727CP02-DevKit-tp18868090p18868090.html
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot-Users] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-08-07 11:03 [U-Boot-Users] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit thaoth
@ 2008-08-08 1:35 ` Nobuhiro Iwamatsu
2008-08-08 7:51 ` thaoth
0 siblings, 1 reply; 20+ messages in thread
From: Nobuhiro Iwamatsu @ 2008-08-08 1:35 UTC (permalink / raw)
To: u-boot
Hi, thaoth .
2008/8/7 thaoth <thaoth@cybersoft-vn.com>:
> Here is configuration of UBoot
> \board\ms7727se\config.mk : TEXT_BASE = 0x8DFC0000
> \board\ms7727se\u-boot.lds
>
> OUTPUT_FORMAT("elf32-sh-tkernel", "elf32-sh-tkernel", "elf32-sh-tkernel")
> SECTIONS
> {
> . = 0x8C000000 + (32*1024*1024) - (256*1024);
>
> \include\configs\ms7727se.h
> /* MEMORY */
> #define MS7720SE_SDRAM_BASE 0x8C000000
> #define MS7720SE_FLASH_BASE_1 0x80000000 //0xA0000000
> #define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
>
> #define CFG_MEMTEST_START MS7720SE_SDRAM_BASE
> #define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
>
> #define CFG_SDRAM_BASE MS7720SE_SDRAM_BASE
> #define CFG_SDRAM_SIZE (32 * 1024 * 1024)
>
> #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
> #define CFG_MONITOR_BASE MS7720SE_FLASH_BASE_1
> #define CFG_MONITOR_LEN (128 * 1024)
> #define CFG_MALLOC_LEN (256 * 1024)
> #define CFG_GBL_DATA_SIZE 256
> #define CFG_BOOTMAPSZ (8 * 1024 * 1024)
>
>
> /* FLASH */
> #define CFG_FLASH_CFI
> #define CFG_FLASH_CFI_DRIVER
> #undef CFG_FLASH_QUIET_TEST
> #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
>
> #define CFG_FLASH_BASE MS7720SE_FLASH_BASE_1
>
>
>
> Would you please help me have a look this setting?
> 1. Is this setting correct ? I am confusing about TEXT_BASE with
> CFG_LOAD_ADDR. Here is definition
> - CFG_FLASH_BASE:
> Physical start address of Flash memory.
>
> - CFG_MONITOR_BASE:
> Physical start address of boot monitor code (set by
> make config files to be same as the text base address
> (TEXT_BASE) used when linking) - same as
> CFG_FLASH_BASE when booting from flash.
Yes, you are right.
If you use *make config_xx ; make* , you can make an u-boot.srec file starting
from the memory (May be address is 0x8DFC000).
I think that you know it, T-engine has a monitor program.
The T-engine user uses this monitor program and writes in it at a flash bulb.
However, as for this program, only a SREC file is usable.
If you want make SREC file to Flash, you need to use objcopy command.
shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec
Please check doc/README.sh.
>
> If I am wrong, please tell me how to correct these setting.
>
> 2. "ld" T-Engine toolchain only supports elf32-sh-tkernel target, but
> reference implementation (example) tell "elf32-sh-linux" is expected target.
> Is the setting correct?
>
> \board\ms7727se\u-boot.lds
> Original :
> OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
> -> My changes
> OUTPUT_FORMAT("elf32-sh-tkernel", "elf32-sh-tkernel", "elf32-sh-tkernel")
Hmmm, I have not used the tool-chain for t-kernel.
However, as for me, there is an acquaintance using t-kernel.
I can ask him. And, I will reply about this matter.
>
>
> I am newbie in embedded system. I am appreciating your helping.
> Thank you a lot.
I think that I want to support t-kernel and other OS to U-boot-sh.
I cooperate with you.
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot-Users] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-08-08 1:35 ` Nobuhiro Iwamatsu
@ 2008-08-08 7:51 ` thaoth
2008-08-08 8:59 ` Nobuhiro Iwamatsu
0 siblings, 1 reply; 20+ messages in thread
From: thaoth @ 2008-08-08 7:51 UTC (permalink / raw)
To: u-boot
> If you want make SREC file to Flash, you need to use objcopy command.
> shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec
This is a good instruction, now I could flash the srec image to Flash Memory
by this command.
srec file was created by below command cannot flash into board.
# sh3-linux-objcopy --gap-fill=0xff -O srec u-boot u-boot.srec
# sh3-linux-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin
Here are file sizes
u-boot.flash.srec 213040
u-boot.srec 222322
u-boot.bin 74080
> Please check doc/README.sh.
I didn't see it. there is only doc/README.sha1
> I think that you know it, T-engine has a monitor program.
> The T-engine user uses this monitor program and writes in it at a flash
> bulb.
> However, as for this program, only a SREC file is usable.
This is a T-Monitor program can work as boot loader application. But I
didn't use it for flashing memory ROM. I would like to use UBoot as a boot
loader replacing this application (T-Monitor).
I worked with Downloader utility of Debug board (T-Engine/SH7727 DevKit)
====================================================
T-Engine(MS7727CP01) DownLoader Ver1.8L
----------------------------------------------------
SH7727 Flash Memory Change Value!
Flash Memory data copy to RAM
Please Send A S-format Record
Start Addrs = 00000000
End Addrs = 0001215F
Transfer complete
Flash chip erase: complete
Program :complete
Flash write complete
Ready>RESTART
I have questions about uboot below:
1. Reallocating address of u-boot in booting process.
At the booting process, the address 0x80000000 is executed. This is memory
mapping address of Flash memory. and executable code of T-Monitor will be
executed.
(1) ROM area memory map
In ROM, 8M byte(0x80000000-0x807FFFFF)of area is implemented.
Memory map of ROM area is shown as below.
0x80000000 +-------------------------------+
| T-Monitor code |
|- - - - - - - - - - - - - - - -|
| |
0x80010000 +-------------------------------+
| ROM Information |
0x80010080 +-------------------------------+
|System configuration info |
| (SYSCONF / DEVCONF) |
|- - - - - - - - - - - - - - - -|
| |
0x80020000 +-------------------------------+
| T-Kernel code |
| |
+-------------------------------+
| |
| User area |
| |
0x80800000 +-------------------------------+
UBoot code will reflash into Flash memory at 0x80000000 address. This is
Flash Memory just readonly. Will UBoot reallocating (loading) binary code
into SDRAM at TEXT_BASE address. In T-Engine/Sh7727, this address will be
0x8DFC0000 (Beginning address of SDRAM is 0x8C000000). Does UBoot
automatically reload this code into TEXT_BASE address?
Because Boot starting address will begin at Flash memory (0x80000000) and
T-Monitor (current boot loader) worked at this address. I don't know how
about UBoot. Does it reload Uboot into SDRAM (TEXT BASE) and run?
2. This is a great site for working SH with Linux.
http://www.superh-linux.org/platforms/index.html
Based on Reference board board/ms7720se, I changed the UBoot configuration
for T-Engine/SH7727 MS7727CP02 Kit.
Many thanks to authors for your efforts
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
I got a toolchain at
http://www.superh-linux.org/archive/bsp/sh7721_se/toolchain_sh3_gcc4.2.tar.gz
It supported "elf32-sh-linux" target.
And I also got toolchain from T-Engine forum and it support
"elf32-sh-tkernel" target.
I don't know UBoot built with toolchain from http://www.superh-linux.org can
work on T-Engine platform or not?
3. Debugging tool for U-Boot development.
Please tell me how to debug UBoot can work on board. Could you tell me
debugger tool for this purpose? Now I can reflash UBoot into Flash Memory
but I don't know how to check UBoot can work on it. Because porting have
others issues such as serial library, interrupt....
Could you recommend a tool can check it can work?
Sorry for stupid question.
4. Serial driver for UBoot on T-Engine/SH7727 board.
After make sure these configuration are correct setting (SDRAM adress, Flash
Memory). Next step is serial porting for UBoot.
I think serial is basic peripheral and It can work with a small changes. But
Maybe I am wrong. Could you recommend the steps I could work on for serial
porting of UBoot?
T-Engine has a serial library. I don't know how can reuse this library or
not? :(
> I think that I want to support t-kernel and other OS to U-boot-sh.
> I cooperate with you.
Nice for hearing that. I appreciated your help. Many thanks for your effort.
Best regards,
Thao
--
View this message in context: http://www.nabble.com/-T-Engine--UBoot-configuration-for-T-Engine-SH7727-MS7727CP02-DevKit-tp18868090p18887349.html
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot-Users] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-08-08 7:51 ` thaoth
@ 2008-08-08 8:59 ` Nobuhiro Iwamatsu
2008-08-20 4:02 ` [U-Boot] " thaoth
2008-09-10 11:51 ` thaoth
0 siblings, 2 replies; 20+ messages in thread
From: Nobuhiro Iwamatsu @ 2008-08-08 8:59 UTC (permalink / raw)
To: u-boot
Hello,
2008/8/8 thaoth <thaoth@cybersoft-vn.com>:
>
> I have questions about uboot below:
> 1. Reallocating address of u-boot in booting process.
> At the booting process, the address 0x80000000 is executed. This is memory
> mapping address of Flash memory. and executable code of T-Monitor will be
> executed.
>
> (1) ROM area memory map
> In ROM, 8M byte(0x80000000-0x807FFFFF)of area is implemented.
> Memory map of ROM area is shown as below.
>
> 0x80000000 +-------------------------------+
> | T-Monitor code |
> |- - - - - - - - - - - - - - - -|
> | |
> 0x80010000 +-------------------------------+
> | ROM Information |
> 0x80010080 +-------------------------------+
> |System configuration info |
> | (SYSCONF / DEVCONF) |
> |- - - - - - - - - - - - - - - -|
> | |
> 0x80020000 +-------------------------------+
> | T-Kernel code |
> | |
> +-------------------------------+
> | |
> | User area |
> | |
> 0x80800000 +-------------------------------+
>
> UBoot code will reflash into Flash memory at 0x80000000 address. This is
> Flash Memory just readonly. Will UBoot reallocating (loading) binary code
> into SDRAM at TEXT_BASE address. In T-Engine/Sh7727, this address will be
> 0x8DFC0000 (Beginning address of SDRAM is 0x8C000000). Does UBoot
> automatically reload this code into TEXT_BASE address?
Yes, U-Boot designed working on SDRAM.
In cpu/sh3/start.S, code of U-boot is copied from a flash bulb by memory and
jump in memory.
Because implementation of original U-boot comes to work as for this on memory,
I match the SuperH with this implementation.
>
> Because Boot starting address will begin at Flash memory (0x80000000) and
> T-Monitor (current boot loader) worked at this address. I don't know how
> about UBoot. Does it reload Uboot into SDRAM (TEXT BASE) and run?
>
> 2. This is a great site for working SH with Linux.
> http://www.superh-linux.org/platforms/index.html
> Based on Reference board board/ms7720se, I changed the UBoot configuration
> for T-Engine/SH7727 MS7727CP02 Kit.
>
> Many thanks to authors for your efforts
> # Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
> # Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
>
> I got a toolchain at
> http://www.superh-linux.org/archive/bsp/sh7721_se/toolchain_sh3_gcc4.2.tar.gz
> It supported "elf32-sh-linux" target.
> And I also got toolchain from T-Engine forum and it support
> "elf32-sh-tkernel" target.
>
> I don't know UBoot built with toolchain from http://www.superh-linux.org can
> work on T-Engine platform or not?
Sorry , I dont know it.
The tool chain of http://www.superh-linux.org tests only elf32-sh-linux.
>
> 3. Debugging tool for U-Boot development.
> Please tell me how to debug UBoot can work on board. Could you tell me
> debugger tool for this purpose? Now I can reflash UBoot into Flash Memory
> but I don't know how to check UBoot can work on it. Because porting have
> others issues such as serial library, interrupt....
>
> Could you recommend a tool can check it can work?
> Sorry for stupid question.
A developer has many cases to debug with ICE.
When there is not ICE, We write in it at SDRAM with monitor and debug
it on SDRAM.
>
> 4. Serial driver for UBoot on T-Engine/SH7727 board.
> After make sure these configuration are correct setting (SDRAM adress, Flash
> Memory). Next step is serial porting for UBoot.
>
> I think serial is basic peripheral and It can work with a small changes. But
> Maybe I am wrong. Could you recommend the steps I could work on for serial
> porting of UBoot?
>
> T-Engine has a serial library. I don't know how can reuse this library or
> not? :(
>
There is two approach.
1. You delete content of Flash, and it is the method that only U-Boot uses.
When you use this method, you come to need ICE.
But this is very simple.
2. You call U-boot like an application from T-monitor, and to use.
When you use this method, you will not need ICE.
But you need Implementation serial function used T-monitor's library.
I will ask a specialist in T-engine an opinion.
I will send e-mail it if there is some information.
Many Japanese companies become the long vacation from tomorrow.
Because I am a holiday, an answer is not possible for approximately 2
weeks.
Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-08-08 8:59 ` Nobuhiro Iwamatsu
@ 2008-08-20 4:02 ` thaoth
2008-08-20 7:40 ` Nobuhiro Iwamatsu
2008-09-10 11:51 ` thaoth
1 sibling, 1 reply; 20+ messages in thread
From: thaoth @ 2008-08-20 4:02 UTC (permalink / raw)
To: u-boot
Hi Nobuhiro Iwamatsu,
1. Clock frequency of board.
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
I don't understand how to set CONFIG_SYS_CLK_FREQ value. From T-Engine
support, they said clock frequency of board is 144MHz.
CPU: SH7727 144 MHz
Flash ROM: 80000000 - 807FFFFF : 8 MB (64 KB blk x 128)
80000000 - 8000FFFF : Monitor Area (64 KB)
80010000 - 8001007F : RomInfo Area (128 B)
SDRAM: 8C000000 - 8DFFFFFF : 32 MB
8C000000 - 8C001FFF : Monitor & System Area (8 KB)
Could I set CFG_HZ to 144?
#define CFG_HZ 144
2. Cross compiler tool chain : GCC vs T-Engine toolchain
There are two tool chains
-
http://www.superh-linux.org/archive/bsp/sh7721_se/toolchain_sh3_gcc4.2.tar.gz
support elf32-sh-linux target.
- Tool chain from T-Engine forum support elf32-sh-tkernel
Using both cross compilers, we could turn on LED on debug board by setting
correct value LED_A and LED_B value.
3. ICE or JTAG debugger and LED debugging.
I don't have these debug tools, and so hard for debugging. T-Engine/SH7727
DevKit has debug board with 8 LEDs. I could turn on/off these LEDs by
setting correct value to 0xA1600000 memory. But C function turn on/off LED
cannot work. For example
int cpu_init(void)
{
// Turn off LED 1 to notify cpu_init is called.
outw(0x00 & 0xFF, 0xa1600000);
return 0;
}
I don't know why it isn't called?
Would you please give me your ideas? Thank you a lot.
Regards,
--
View this message in context: http://www.nabble.com/-T-Engine--UBoot-configuration-for-T-Engine-SH7727-MS7727CP02-DevKit-tp18868090p19062634.html
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-08-20 4:02 ` [U-Boot] " thaoth
@ 2008-08-20 7:40 ` Nobuhiro Iwamatsu
2008-08-21 7:26 ` thaoth
2008-09-03 3:48 ` thaoth
0 siblings, 2 replies; 20+ messages in thread
From: Nobuhiro Iwamatsu @ 2008-08-20 7:40 UTC (permalink / raw)
To: u-boot
Hi,
2008/8/20 thaoth <thaoth@cybersoft-vn.com>:
>
> Hi Nobuhiro Iwamatsu,
>
> 1. Clock frequency of board.
>
> #define CONFIG_SYS_CLK_FREQ 33333333
> #define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
> #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
>
> I don't understand how to set CONFIG_SYS_CLK_FREQ value. From T-Engine
> support, they said clock frequency of board is 144MHz.
Please set outside clock to CONFIG_SYS_CLK_FREQ.
>
> 2. Cross compiler tool chain : GCC vs T-Engine toolchain
> There are two tool chains
> -
> http://www.superh-linux.org/archive/bsp/sh7721_se/toolchain_sh3_gcc4.2.tar.gz
> support elf32-sh-linux target.
> - Tool chain from T-Engine forum support elf32-sh-tkernel
> Using both cross compilers, we could turn on LED on debug board by setting
> correct value LED_A and LED_B value.
>
> 3. ICE or JTAG debugger and LED debugging.
> I don't have these debug tools, and so hard for debugging. T-Engine/SH7727
> DevKit has debug board with 8 LEDs. I could turn on/off these LEDs by
> setting correct value to 0xA1600000 memory. But C function turn on/off LED
> cannot work. For example
>
> int cpu_init(void)
> {
> // Turn off LED 1 to notify cpu_init is called.
> outw(0x00 & 0xFF, 0xa1600000);
> return 0;
> }
>
> I don't know why it isn't called?
I think that cpu_init is not carried out.
I think that u-boot stopped on lowlevel_init function.
>
> Would you please give me your ideas? Thank you a lot.
I will get T-Engine board ......
Please wait.
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-08-20 7:40 ` Nobuhiro Iwamatsu
@ 2008-08-21 7:26 ` thaoth
2008-08-21 9:54 ` thaoth
2008-09-03 3:48 ` thaoth
1 sibling, 1 reply; 20+ messages in thread
From: thaoth @ 2008-08-21 7:26 UTC (permalink / raw)
To: u-boot
Hi Nobuhiro Iwamatsu,
> Please set outside clock to CONFIG_SYS_CLK_FREQ.
Sorry I didn't see "outside clock" in T-Engine/SH7727 specification. Regard
to clock of board, there are 3 types
- Internal clock
- Peripheral clock
- Bus clock
And have a look initialization values of T-Monitor - a boot loader of
T-Engine/SH7727,
ICLK_VAL: .long 0x0060 // 96 Mhz
PCLK_VAL: .long 0x0018 // 24 Mhz
FRQCR_VAL: .long 0x0112 // PLL*2, IFC*1, PFC/4
RTCOR_VAL: .long 0xa50b // 48MHz /64 14.667us
FRQCR: frequency multipliers controller
RTCOR: reflash time constant counter
Does "outside clock" mean peripheral clock? It is 24 Mhz.
> I think that cpu_init is not carried out.
> I think that u-boot stopped on lowlevel_init function.
In lowlevel_init function, I put a LED debugging function which turn on LED
on debug board. It works.
mov.l LED_A, r1
mov.l LED_D, r0
mov.b r0, @r1
LED_A: .long 0xA1600000 /* LED_BASE address */
LED_D: .long 0xaa /* mh a1600000, 00 --> ALL LED ON */
But C function in sh_generic_init() cannot work. :(
> I will get T-Engine board ......
Thank you and hope hearing good news from you.
Best regards,
--
View this message in context: http://www.nabble.com/-T-Engine--UBoot-configuration-for-T-Engine-SH7727-MS7727CP02-DevKit-tp18868090p19083780.html
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-08-21 7:26 ` thaoth
@ 2008-08-21 9:54 ` thaoth
2008-08-21 11:27 ` thaoth
0 siblings, 1 reply; 20+ messages in thread
From: thaoth @ 2008-08-21 9:54 UTC (permalink / raw)
To: u-boot
Hi Nobuhiro Iwamatsu,
> I think that cpu_init is not carried out.
> I think that u-boot stopped on lowlevel_init function.
thaoth wrote:
>
> In lowlevel_init function, I put a LED debugging function which turn on
> LED on debug board. It works.
>
> mov.l LED_A, r1
> mov.l LED_D, r0
> mov.b r0, @r1
>
> LED_A: .long 0xA1600000 /* LED_BASE address */
> LED_D: .long 0xaa /* mh a1600000, 00 --> ALL LED ON */
>
> But C function in sh_generic_init() cannot work. :(
>
Here is lowlevel_init.S
> .global lowlevel_init
>
> .text
> .align 2
>
> lowlevel_init:
> mov.l WTCSR,r1 // WTCSR: 0xFFFFFF86 Watchdog Timer Control / Status
> Register)
> mov.l WTCSR_D,r0 // WTCSR_D: 0xA506
> mov.w r0, at r1
>
> mov.l WTCNT,r1 // WTCNT: 0xFFFFFF84 Watchdog Timer Counter
> mov.l WTCNT_D,r0 // WTCNT_D: 0x5A00
> mov.w r0, at r1
>
> ! mov.l UCLKCR,r1 // UCLKCR: USBH/USBF Clock control register
> ! mov.l UCLKCR_D,r0
> ! mov.w r0, at r1
>
> mov.l FRQCR, r1 // FRQCR_A: 0xFFFFFF80 Frequency control register
> Address
> mov.l FRQCR_VAL, r0
> mov.w r0, @r1
>
> mov.l BCR1, r1
> mov.l BCR1_VAL, r0
> mov.w r0, @r1 // base control register 1
>
> mov.l BCR2, r1
> mov.l BCR2_VAL, r0
> mov.w r0, @r1 // base control register 2
>
> mov.l WCR1, r1
> mov.l WCR1_VAL, r0
> mov.w r0, @r1 // wait state control register 1
>
> mov.l WCR2, r1
> mov.l WCR2_VAL, r0
> mov.w r0, @r1 // wait state control register 2
>
> mov.l MCR, r1
> mov.l MCR_VAL, r0
> mov.w r0, @r1 // memory control register
>
> mov.l PCR, r1
> mov.l PCR_VAL, r0
> mov.w r0, @r1 // PCMCIA control register
>
> mov.l RTCSR, r1
> mov.w RTCSR_DUMMY, r0
> mov.w r0, @r1 // reflash timer control / status register
>
> mov.l RTCNT, r1
> mov.w RTCNT_VAL, r0
> mov.w r0, @r1 // reflash timer counter
>
> mov.l RTCOR, r1
> mov.w RTCOR_VAL, r0
> mov.w r0, @r1 // reflash time constant counter
>
> mov.l RFCR, r1
> mov.w RFCR_VAL, r0
> mov.w r0, @r1 // reflash count register
>
> /* SDRAM initalization */
> // 100us dummy wait
>
> mov.l SDMR3_ADDR, r1
> mov.w SDMR3_VAL, r0
> mov.w r0, @r1 // reflash count register
>
> mov.l RTCSR, r1
> mov.w RTCSR_VAL, r0
> mov.w r0, @r1 // reflash timer control / status register
>
> // dummy reflash
> /***********************/
>
> // mov.l _PINTER, r1 // init PINTER
> // mov #0, r0
> // mov.w r0, @r1
>
> // mov.l _IPRA, r1 // init IPRA
> // mov.w IPRA_VAL, r0
> // mov.w r0, @r1
>
> // mov.l _IPRD, r1 // init IPRD
> // mov.w IPRD_VAL, r0
> // mov.w r0, @r1
>
> // mov.l _IPRG, r1 // init IPRG
> // mov.w IPRG_VAL, r0
> // mov.w r0, @r1
>
> // mov.l _ICR1, r1 // init ICR1
> // mov.w ICR1_VAL, r0
> // mov.w r0, @r1
>
> // mov.l _ICR2, r1 // init ICR2
> // mov.w ICR2_VAL, r0
> // mov.w r0, @r1
>
> // mov.l _PINTER, r1 // init PINTER
> // mov.w PINTER_VAL, r0
> // mov.w r0, @r1
>
> mov.l PCCR, r1 // init PCCR
> mov.w PCCR_VAL, r0
> mov.w r0, @r1
>
> mov.l PDCR, r1 // init PDCR
> mov.w PDCR_VAL, r0
> mov.w r0, @r1
>
> mov.l PECR, r1 // init PECR
> mov.w PECR_VAL, r0
> mov.w r0, @r1
>
> mov.l PHCR, r1 // init PHCR
> mov.w PHCR_VAL, r0
> mov.w r0, @r1
>
> mov.l PJCR, r1 // init PJCR
> mov.w PJCR_VAL, r0
> mov.w r0, @r1
>
> mov.l PKCR, r1 // init PKCR
> mov.w PKCR_VAL, r0
> mov.w r0, @r1
>
> mov.l PLCR, r1 // init PLCR
> mov.w PLCR_VAL, r0
> mov.w r0, @r1
>
> mov.l PMCR, r1 // init PMCR
> mov.w PMCR_VAL, r0
> mov.w r0, @r1
>
> mov.l SCPCR, r1 // init SCPCR
> mov.w SCPCR_VAL, r0
> mov.w r0, @r1
>
> ! mov.l ICLK, r1 // init internal clock 96 Mhz
> ! mov.l ICLK_VAL, r0
> ! mov.w r0, @r1
>
> ! mov.l PCLK, r1 // init peripheral clock 24 Mhz
> ! mov.l PCLK_VAL, r0
> ! mov.w r0, @r1
>
> mov.l LED_A, r1
> mov.l LED_D, r0
> mov.b r0, @r1
>
> rts
> nop
>
> .align 4
>
> !ICLK: .long 0x8c000274
> !PCLK: .long 0x8c000276
>
> WTCSR: .long 0xFFFFFF86 /* WTCSR: 0xFFFFFF86 Watchdog Timer Control /
> Status Register) */
> WTCNT: .long 0xFFFFFF84 /* WTCNT: 0xFFFFFF84 Watchdog Timer Counter */
> /*UCLKCR: .long 0xA40A0008*/ /* USBH/USBF: Clock control register ???*/
> FRQCR: .long 0xffffff80
> BCR1: .long 0xffffff60 /* Bus Control Register 1 */
> BCR2: .long 0xffffff62 /* Bus Control Register 2 */
> WCR1: .long 0xffffff64 /* Wait State Control Register 1 */
> WCR2: .long 0xffffff66 /* Wait State Control Register 2 */
> MCR: .long 0xffffff68 /* Individual Memory Control Register */
> PCR: .long 0xffffff6c /* PCMCIA control register */
> RTCSR: .long 0xffffff6e /* Refresh timer control/status register */
> RTCNT: .long 0xffffff70 /* Refresh timer counter */
> RTCOR: .long 0xffffff72 /* Refresh time contant register */
> RFCR: .long 0xffffff74 /* Refresh count register */
> SDMR3_ADDR: .long 0xFFFFE800 + 0x80 /* Synchorounos DRAM Mode register
> ??? */
>
> /* SH Internal Use - Area 1 */
> PCCR: .long 0xa4000104
> PDCR: .long 0xa4000106
> PECR: .long 0xa4000108
> PFCR: .long 0xa400010a
> PGCR: .long 0xa400010c
> PHCR: .long 0xa400010e
> PJCR: .long 0xa4000110
> PKCR: .long 0xa4000112
> PLCR: .long 0xa4000114
> PMCR: .long 0xa4000118
> SCPCR: .long 0x04000116
>
> /* Initialize data */
> ICLK_VAL: .long 0x0060 // 96 Mhz
> PCLK_VAL: .long 0x0018 // 24 Mhz
>
> WTCNT_D: .long 0x5A00 /* WTCNT_D: 0x5A00 set the upper byte to 5A and
> transfer data into lower byte */
> WTCSR_D: .long 0xA506 /* WTCSR_D: 0xA506 set the upper byte to A5 and
> transfer data into lower byte */
> /*UCLKCR_D: .long 0xA5C0*/
>
> FRQCR_VAL: .long 0x0112 // PLL*2, IFC*1, PFC/4
> BCR1_VAL: .long 0x0008 /* Bus Control Register 1 */
> BCR2_VAL: .long 0x2ae0 /* Bus Control Register 2 */
> #if USE_R0P7727TH003TRK == 1
> WCR1_VAL: .long 0xaaa2 /* Wait State Control Register 1 */
> #else // previous type T-Engine
> WCR1_VAL: .long 0xaa22
> #endif
> WCR2_VAL: .long 0xb6dd /* Wait State Control Register 2 */
>
> #if USE_R0P7727TH003TRK == 1
> MCR_VAL: .long 0x966c /* Individual Memory Control Register */
> #else // previous type T-Engine
> MCR_VAL: .long 0x012c
> #endif
> PCR_VAL: .long 0x0000 /* PCMCIA control register */
> RTCSR_DUMMY: .long 0xa500 //
> RTCSR_VAL: .long 0xa518 /* Refresh timer control/status register : CKIO
> 1/64 */
> RTCNT_VAL: .long 0xa500 /* Refresh timer counter */
>
> #if USE_R0P7727TH003TRK == 1
> RTCOR_VAL: .long 0xa505 /* Refresh time contant register */
> #else // previous type T-Engine
> RTCOR_VAL: .long 0xa50b // 48MHz /64 14.667us
> #endif
> RFCR_VAL: .long 0xa400 /* Refresh count register */
> SDMR3_VAL: .long 0x00 /* Synchorounos DRAM Mode register ??? */
>
> IPRA_VAL: .long 0x8000
> IPRD_VAL: .long 0xc000
> IPRG_VAL: .long 0xc000
> ICR1_VAL: .long 0x42aa
> ICR2_VAL: .long 0x000c
> PINTER_VAL: .long 0x000c
> PCCR_VAL: .long 0x0000
> PDCR_VAL: .long 0x0000
> PECR_VAL: .long 0x0500
> PFCR_VAL: .long 0x00AA
> PGCR_VAL: .long 0xA200
> PHCR_VAL: .long 0x0800
> PJCR_VAL: .long 0x0540
> PKCR_VAL: .long 0x0005
> PLCR_VAL: .long 0xaaaa
> PMCR_VAL: .long 0xaa00
> SCPCR_VAL: .long 0x0000
>
> SDCR_D1: .long 0x00000011
> SDCR_D2: .long 0x00000811
>
> LED_A: .long 0xA1600000 /* LED_BASE address */
> LED_D: .long 0xaa /* mh a1600000, 00 --> ALL LED ON */
>
void sh_generic_init (void)
{
...
outw(0x7e, LED_BASE);
}
Now sh_generic_init could be called with LEDs indicated true status. :-) But
I don't know what next issue? :-((
Best regards,
--
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-08-21 9:54 ` thaoth
@ 2008-08-21 11:27 ` thaoth
0 siblings, 0 replies; 20+ messages in thread
From: thaoth @ 2008-08-21 11:27 UTC (permalink / raw)
To: u-boot
Hi Nobuhiro Iwamatsu,
I have checked sequence initialization functions in sh_generic_init and the
problem is serial library cannot work correctly. The result is output to
console cannot display.
Regards.
--
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-08-20 7:40 ` Nobuhiro Iwamatsu
2008-08-21 7:26 ` thaoth
@ 2008-09-03 3:48 ` thaoth
1 sibling, 0 replies; 20+ messages in thread
From: thaoth @ 2008-09-03 3:48 UTC (permalink / raw)
To: u-boot
Hi Nobuhiro Iwamatsu,
Now I'm porting USB on board T-Engine(SH7727)
- My configure following :
#define CONFIG_CMD_USB
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_STORAGE 1
#define CFG_USB_OHCI_REGS_BASE 0x04000400
#define CFG_USB_OHCI_SLOT_NAME "s3c2400"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
- And in lowlevel_init.S, I change USB clock following:
UCLKCR_A: .long 0xA40A0008
UCLKCR_D: .long 0xA5C0
mov.l UCLKCR_A,r1
mov.l UCLKCR_D,r0
mov.w r0, at r1
- When I'm starting board with above configue, I see the led of USB device
is blinking. Then I run command "usb start", the led turn off and u-boot
don't find any USB device, with following logs:
DEBUG: OHCI controller usb-s3c2400 state
DEBUG: control: 0x0000008f HCFS=operational IE PLE CBSR=3
DEBUG: cmdstatus: 0x00000000 SOC=0
DEBUG: intrstatus: 0x00000004 SF
DEBUG: intrenable: 0x00000053 RHSC UE WDH SO
DEBUG: hcca frame #0019
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000100 PPS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
scanning bus for devices... New Device 0
usb_control_msg: request: 0x6, requesttype: 0x80
value 0x100 index 0x0 length 0x8
INFO: submit_control_msg
DEBUG: SUB URB:[ 42] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000
DEBUG: SUB(rh) URB:[ 45] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000
INFO: Root-Hub: adr: 0 cmd(8): 00000680 0001 0000 0800
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000100 PPS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ 56] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x2
usb_ohci.c: cmd(8): 80 06 01 00 00 00 00 08
usb_ohci.c: data(0/8):
USB device not responding, giving up (status=2)
0 USB Device(s) found scanning bus for storage devices... 0 Storage
Device
(s) found
- I don't know what is wrong in my configure, I think the
CONFIG_SYS_CLK_FREQ and CFG_HZ is incorrect and I can't start USB device,
and clock which I control in lowlevel_init.S following:
FRQCR_A: .long 0xA415FF80 /* FRQCR Address(Frequency Control Register) */
FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */
Can you help me about this problem and tell me about any other wrong things
in my configure? why the led turn off when I run command "usb start"?
thanks
Nobuhiro Iwamatsu wrote:
>
> Hi,
>
> 2008/8/20 thaoth <thaoth@cybersoft-vn.com>:
>>
>> Hi Nobuhiro Iwamatsu,
>>
>> 1. Clock frequency of board.
>>
>> #define CONFIG_SYS_CLK_FREQ 33333333
>> #define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or
>> 1024 */
>> #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
>>
>> I don't understand how to set CONFIG_SYS_CLK_FREQ value. From T-Engine
>> support, they said clock frequency of board is 144MHz.
>
>
> Please set outside clock to CONFIG_SYS_CLK_FREQ.
>
>>
>> 2. Cross compiler tool chain : GCC vs T-Engine toolchain
>> There are two tool chains
>> -
>> http://www.superh-linux.org/archive/bsp/sh7721_se/toolchain_sh3_gcc4.2.tar.gz
>> support elf32-sh-linux target.
>> - Tool chain from T-Engine forum support elf32-sh-tkernel
>> Using both cross compilers, we could turn on LED on debug board by
>> setting
>> correct value LED_A and LED_B value.
>>
>> 3. ICE or JTAG debugger and LED debugging.
>> I don't have these debug tools, and so hard for debugging.
>> T-Engine/SH7727
>> DevKit has debug board with 8 LEDs. I could turn on/off these LEDs by
>> setting correct value to 0xA1600000 memory. But C function turn on/off
>> LED
>> cannot work. For example
>>
>> int cpu_init(void)
>> {
>> // Turn off LED 1 to notify cpu_init is called.
>> outw(0x00 & 0xFF, 0xa1600000);
>> return 0;
>> }
>>
>> I don't know why it isn't called?
>
> I think that cpu_init is not carried out.
> I think that u-boot stopped on lowlevel_init function.
>
>>
>> Would you please give me your ideas? Thank you a lot.
>
> I will get T-Engine board ......
> Please wait.
>
> Best regards,
> Nobuhiro
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
>
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* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-08-08 8:59 ` Nobuhiro Iwamatsu
2008-08-20 4:02 ` [U-Boot] " thaoth
@ 2008-09-10 11:51 ` thaoth
2008-09-10 12:13 ` Nobuhiro Iwamatsu
1 sibling, 1 reply; 20+ messages in thread
From: thaoth @ 2008-09-10 11:51 UTC (permalink / raw)
To: u-boot
Hi,
I got USB issue and here is an error message:
ERROR: CTL:TIMEOUT
USB device not responding, giving up (status=20)
3 USB Device(s) found
scanning bus for storage devices...
0 Storage Device(s) found
For detail, TEngine/SH7727 has one USB host controller, when I plugged USB
Flash Memory there were 3 devices. And No unplugged USB device, they said 2
devices.
=> usb info
1: Hub, USB Revision 1.10
- OHCI Root Hub
- Class: Hub
- PacketSize: 8 Configurations: 1
- Vendor: 0x0000 Product 0x0000 Version 0.0
Configuration: 1
- Interfaces: 1 Self Powered 0mA
Interface: 0
- Alternate Setting 0, Endpoints: 1
- Class Hub
- Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms
Configuration: 0
- Interfaces: 0 Bus Powered 0mA
Configuration: 0
- Interfaces: 0 Bus Powered 0mA
The problem sounded USB host controller driver could work well but
submit_common_msg couldn't get description of USB flash memory device and it
said "No storage device".
Here is configuration of USB on UBoot
/* USB Mass Storage Support*/
#define CONFIG_CMD_USB
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_STORAGE 1
#define CFG_USB_OHCI_REGS_BASE 0xA4000400
#define CFG_USB_OHCI_SLOT_NAME "s3c2400"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
Could I have help? Please tell me if you have any idea. Thank you for your
helping. =)
Here is a log data
U-Boot 1.3.4-00404-gab00e7a-dirty (Sep 10 2008 - 16:30:38)
CPU: SH3
BOARD: Hitachi UL MS7727SE
DRAM: 32MB
FLASH: 8MB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
=> usb start
(Re)start USB...
USB: INFO: aligned ghcca 8e01ad00
DEBUG: hc_reset
DEBUG: USB HC reset_hc usb-s3c2400: ctrl = 0x0 ;
DEBUG: OHCI controller usb-s3c2400 state
DEBUG: control: 0x0000008f HCFS=operational IE PLE CBSR=3
DEBUG: cmdstatus: 0x00000000 SOC=0
DEBUG: intrstatus: 0x00000004 SF
DEBUG: intrenable: 0x00000053 RHSC UE WDH SO
DEBUG: hcca frame #000d
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000100 PPS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
scanning bus for devices... New Device 0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0
length 0
x8
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000
INFO: Root-Hub: adr: 0 cmd(8): 00000680 0100 0000 0008
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000100 PPS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x0
usb_ohci.c: cmd(8): 80 06 00 01 00 00 08 00
usb_ohci.c: data(0/8):
set address 1
usb_control_msg: request: 0x5, requesttype: 0x0, value 0x1 index 0x0 length
0x0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 00 05 01 00 00 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 00 05 01 00 00 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000500 0001 0000 0000
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 00 05 01 00 00 00 00 00
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0
length 0
x12
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/18 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/18 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 00000680 0100 0000 0012
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/18 stat:0x0
usb_ohci.c: cmd(8): 80 06 00 01 00 00 12 00
usb_ohci.c: data(0/18):
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0
length 0
x8
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 00000680 0200 0000 0008
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/8 stat:0x0
usb_ohci.c: cmd(8): 80 06 00 02 00 00 08 00
usb_ohci.c: data(0/8):
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0
length 0
x19
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/25 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/25 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 00000680 0200 0000 0019
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/25 stat:0x0
usb_ohci.c: cmd(8): 80 06 00 02 00 00 19 00
usb_ohci.c: data(0/25):
get_conf_no 0 Result 25, wLength 25
if 0, ep 0
##EP epmaxpacketin[1] = 2
set configuration 1
usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length
0x0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 00 09 01 00 00 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 00 09 01 00 00 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000900 0001 0000 0000
INFO: WR:status 0x10000
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 00 09 01 00 00 00 00 00
new device strings: Mfr=0, Product=1, SerialNumber=0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0
length 0
xFF
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 00000680 0300 0000 00ff
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x0
usb_ohci.c: cmd(8): 80 06 00 03 00 00 ff 00
usb_ohci.c: data(0/255):
USB device number 1 default language ID 0x409
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x409
length
0xFF
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 00000680 0301 0409 00ff
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x0
usb_ohci.c: cmd(8): 80 06 01 03 09 04 ff 00
usb_ohci.c: data(0/255):
Manufacturer
Product OHCI Root Hub
SerialNumber
USB hub found
usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0
length
0x4
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 000006a0 2900 0000 0004
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x0
usb_ohci.c: cmd(8): a0 06 00 29 00 00 04 00
usb_ohci.c: data(0/4):
usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0
length
0x9
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/9 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/9 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 000006a0 2900 0000 0009
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/9 stat:0x0
usb_ohci.c: cmd(8): a0 06 00 29 00 00 09 00
usb_ohci.c: data(0/9):
2 ports detected
ganged power switching
standalone hub
no over-current protection
power on to power good time: 4ms
hub controller current requirement: 0mA
port 1 is removable
port 2 is removable
usb_control_msg: request: 0x0, requesttype: 0xA0, value 0x0 index 0x0 length
0x4
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 000000a0 0000 0000 0004
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x0
usb_ohci.c: cmd(8): a0 00 00 00 00 00 04 00
usb_ohci.c: data(0/4):
get_hub_status returned status 0, change 0
local power source is good
no over-current condition exists
enabling power on all ports
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x1 length
0x0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 03 08 00 01 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 03 08 00 01 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000323 0008 0001 0000
INFO: WR:portstatus[0] 0x100
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 23 03 08 00 01 00 00 00
port 1 returns 0
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x2 length
0x0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 03 08 00 02 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 03 08 00 02 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000323 0008 0002 0000
INFO: WR:portstatus[1] 0x100
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 23 03 08 00 02 00 00 00
port 2 returns 0
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length
0x4
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x0
usb_ohci.c: cmd(8): a3 00 00 00 01 00 04 00
usb_ohci.c: data(0/4):
Port 1 Status 101 Change 1
port 1 connection change
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length
0x4
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x0
usb_ohci.c: cmd(8): a3 00 00 00 01 00 04 00
usb_ohci.c: data(0/4):
portstatus 101, change 1, High Speed
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x10 index 0x1
length 0x
0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 10 00 01 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 10 00 01 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000123 0010 0001 0000
INFO: WR:portstatus[0] 0x10000
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000101 PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 23 01 10 00 01 00 00 00
hub_port_reset: resetting port 0...
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length
0x0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 03 04 00 01 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 03 04 00 01 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000323 0004 0001 0000
INFO: WR:portstatus[0] 0x10
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000311 LSDA PPS PRS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 23 03 04 00 01 00 00 00
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length
0x4
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00100303 PRSC LSDA PPS PES CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x0
usb_ohci.c: cmd(8): a3 00 00 00 01 00 04 00
usb_ohci.c: data(0/4):
portstatus 303, change 10, Low Speed
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 1
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x1
length 0x
0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 14 00 01 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 14 00 01 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000123 0014 0001 0000
INFO: WR:portstatus[0] 0x100000
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000303 LSDA PPS PES CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 23 01 14 00 01 00 00 00
New Device 1
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0
length 0
x8
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000
DEBUG: SUB URB:[ d] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000
hc_interrupt regs->intrstatus=68;regs->intrenable=83;ints=64
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
hc_interrupt regs->intrstatus=6;regs->intrenable=83;ints=2
submit_common_msg hc_interrupt():stat = 0
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
ERROR: CTL:TIMEOUT
DEBUG: submit_common_msg: TO status ff
DEBUG: RET(ctlr) URB:[ d] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x20
USB device not responding, giving up (status=20)
hub: disabling port 1
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x1 index 0x1 length
0x0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 01 00 01 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 01 00 01 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000123 0001 0001 0000
INFO: WR:portstatus[0] 0x1
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000301 LSDA PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 23 01 01 00 01 00 00 00
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length
0x4
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0002 0004
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000301 LSDA PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x0
usb_ohci.c: cmd(8): a3 00 00 00 02 00 04 00
usb_ohci.c: data(0/4):
Port 2 Status 101 Change 1
port 2 connection change
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length
0x4
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0002 0004
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000301 LSDA PPS CCS
DEBUG: roothub.portstatus [1] = 0x00010101 CSC PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x0
usb_ohci.c: cmd(8): a3 00 00 00 02 00 04 00
usb_ohci.c: data(0/4):
portstatus 101, change 1, High Speed
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x10 index 0x2
length 0x
0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 10 00 02 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 10 00 02 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000123 0010 0002 0000
INFO: WR:portstatus[1] 0x10000
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000301 LSDA PPS CCS
DEBUG: roothub.portstatus [1] = 0x00000101 PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 23 01 10 00 02 00 00 00
hub_port_reset: resetting port 1...
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x2 length
0x0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 03 04 00 02 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 03 04 00 02 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000323 0004 0002 0000
INFO: WR:portstatus[1] 0x10
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000301 LSDA PPS CCS
DEBUG: roothub.portstatus [1] = 0x00000111 PPS PRS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 23 03 04 00 02 00 00 00
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length
0x4
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000
INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0002 0004
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000301 LSDA PPS CCS
DEBUG: roothub.portstatus [1] = 0x00100103 PRSC PPS PES CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x0
usb_ohci.c: cmd(8): a3 00 00 00 02 00 04 00
usb_ohci.c: data(0/4):
portstatus 103, change 10, High Speed
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 1
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x2
length 0x
0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 14 00 02 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 14 00 02 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000123 0014 0002 0000
INFO: WR:portstatus[1] 0x100000
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000301 LSDA PPS CCS
DEBUG: roothub.portstatus [1] = 0x00000103 PPS PES CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 23 01 14 00 02 00 00 00
New Device 2
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0
length 0
x8
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000
DEBUG: SUB URB:[ d] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000
hc_interrupt regs->intrstatus=68;regs->intrenable=83;ints=64
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
DEBUG: %
DEBUG: hc_interrupt: returning..
submit_common_msg hc_interrupt():stat = 255
ERROR: CTL:TIMEOUT
DEBUG: submit_common_msg: TO status ff
DEBUG: RET(ctlr) URB:[ d] dev: 0,ep: 0-I,type:CTRL,len:0/8 stat:0x20
USB device not responding, giving up (status=20)
hub: disabling port 2
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x1 index 0x2 length
0x0
INFO: submit_control_msg
DEBUG: SUB URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 01 00 02 00 00 00
DEBUG: SUB(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000
usb_ohci.c: cmd(8): 23 01 01 00 02 00 00 00
INFO: Root-Hub: adr: 1 cmd(8): 00000123 0001 0002 0000
INFO: WR:portstatus[1] 0x1
DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2
DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000
DEBUG: roothub.status: 00000000
DEBUG: roothub.portstatus [0] = 0x00000301 LSDA PPS CCS
DEBUG: roothub.portstatus [1] = 0x00000101 PPS CCS
DEBUG: RET(rh) URB:[ d] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0
usb_ohci.c: cmd(8): 23 01 01 00 02 00 00 00
3 USB Device(s) found
scanning bus for storage devices... Storage Device(s) found
Thank you a lot.
Best regards,
--
View this message in context: http://www.nabble.com/-T-Engine--UBoot-configuration-for-T-Engine-SH7727-MS7727CP02-DevKit-tp18868090p19411908.html
Sent from the Uboot - Users mailing list archive at Nabble.com.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-09-10 11:51 ` thaoth
@ 2008-09-10 12:13 ` Nobuhiro Iwamatsu
2008-09-11 2:17 ` Yoshihiro Shimoda
0 siblings, 1 reply; 20+ messages in thread
From: Nobuhiro Iwamatsu @ 2008-09-10 12:13 UTC (permalink / raw)
To: u-boot
Hi, thaoth.
Shimoda-san is USB developper on U-Boot in Renesas.
Shimoda-san, please give us comments this problem.
Best regards,
Nobuhiro
On Wed, 10 Sep 2008 04:51:40 -0700 (PDT)
thaoth <thaoth@cybersoft-vn.com> wrote:
>
> Hi,
>
> I got USB issue and here is an error message:
>
> ERROR: CTL:TIMEOUT
> USB device not responding, giving up (status=20)
> 3 USB Device(s) found
> scanning bus for storage devices...
> 0 Storage Device(s) found
>
> For detail, TEngine/SH7727 has one USB host controller, when I plugged USB
> Flash Memory there were 3 devices. And No unplugged USB device, they said 2
> devices.
--
Nobuhiro Iwamatsu
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-09-10 12:13 ` Nobuhiro Iwamatsu
@ 2008-09-11 2:17 ` Yoshihiro Shimoda
2008-09-11 7:41 ` thaoth
0 siblings, 1 reply; 20+ messages in thread
From: Yoshihiro Shimoda @ 2008-09-11 2:17 UTC (permalink / raw)
To: u-boot
Hi, thaoth.
I think that your board cannot communicate with USB device at all.
SH7727 has EXCPGCR register. Do you set this register?
When I used this CPU before, I did the following setting.
STCBR3 = 0x18;
SRSTR = 0x18;
wait_10msec();
EXCPGCR = 0x28;
wait_10msec();
SRSTR = 0x00;
STCBR3 = 0x00;
Best regards,
Yoshihiro Shimoda
Nobuhiro Iwamatsu wrote:
> Hi, thaoth.
>
> Shimoda-san is USB developper on U-Boot in Renesas.
>
> Shimoda-san, please give us comments this problem.
>
> Best regards,
> Nobuhiro
>
> On Wed, 10 Sep 2008 04:51:40 -0700 (PDT)
> thaoth <thaoth@cybersoft-vn.com> wrote:
>
>> Hi,
>>
>> I got USB issue and here is an error message:
>>
>> ERROR: CTL:TIMEOUT
>> USB device not responding, giving up (status=20)
>> 3 USB Device(s) found
>> scanning bus for storage devices...
>> 0 Storage Device(s) found
>>
>> For detail, TEngine/SH7727 has one USB host controller, when I plugged USB
>> Flash Memory there were 3 devices. And No unplugged USB device, they said 2
>> devices.
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-09-11 2:17 ` Yoshihiro Shimoda
@ 2008-09-11 7:41 ` thaoth
2008-09-11 12:00 ` Yoshihiro Shimoda
0 siblings, 1 reply; 20+ messages in thread
From: thaoth @ 2008-09-11 7:41 UTC (permalink / raw)
To: u-boot
Yoshihiro Shimoda wrote:
>
> Hi, thaoth.
>
> I think that your board cannot communicate with USB device at all.
> SH7727 has EXCPGCR register. Do you set this register?
> When I used this CPU before, I did the following setting.
>
> STCBR3 = 0x18;
> SRSTR = 0x18;
> wait_10msec();
>
> EXCPGCR = 0x28;
> wait_10msec();
>
> SRSTR = 0x00;
> STCBR3 = 0x00;
>
Thank you very much,
Following your instruction, I did
int usb_board_init(void)
{
printf("usb_board_init\n");
outw(0x18, STBCR3);
outw(0x18, SRSTR);
udelay(10);
outw(0x28, EXCPGCR);
udelay(10);
outw(0x00, STBCR3);
outw(0x00, SRSTR);
return 0;
}
> STCBR3 = 0x18;
>
I couldn't see this register "STCBR3 ", I only saw STBCR3. Is it correct?
But UBoot didn't work, Would you please tell me more detail ?
Thank you alot :)
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-09-11 7:41 ` thaoth
@ 2008-09-11 12:00 ` Yoshihiro Shimoda
2008-09-12 5:46 ` thaoth
0 siblings, 1 reply; 20+ messages in thread
From: Yoshihiro Shimoda @ 2008-09-11 12:00 UTC (permalink / raw)
To: u-boot
Hi, thaoth.
thaoth wrote:
>
>
> Yoshihiro Shimoda wrote:
>> Hi, thaoth.
>>
>> I think that your board cannot communicate with USB device at all.
>> SH7727 has EXCPGCR register. Do you set this register?
>> When I used this CPU before, I did the following setting.
< snip >
>>
> Thank you very much,
You are welcome :)
>
> Following your instruction, I did
> int usb_board_init(void)
> {
> printf("usb_board_init\n");
>
> outw(0x18, STBCR3);
> outw(0x18, SRSTR);
> udelay(10);
>
> outw(0x28, EXCPGCR);
> udelay(10);
>
> outw(0x00, STBCR3);
> outw(0x00, SRSTR);
> return 0;
> }
These registers are 8-bit width. So please use outb() macro.
>
>> STCBR3 = 0x18;
>>
> I couldn't see this register "STCBR3 ", I only saw STBCR3. Is it correct?
Oh, I am sorry. That's correct.
> But UBoot didn't work, Would you please tell me more detail ?
> Thank you alot :)
I am sorry, my explanation was short. This EXCPGCR value was for an another board.
In the case of your board, it may be necessary to make it a defferent value.
And I used my board, I set 0x1500 in PKCR.
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-09-11 12:00 ` Yoshihiro Shimoda
@ 2008-09-12 5:46 ` thaoth
2008-09-12 6:44 ` Yoshihiro Shimoda
0 siblings, 1 reply; 20+ messages in thread
From: thaoth @ 2008-09-12 5:46 UTC (permalink / raw)
To: u-boot
Hi,
>
> Following your instruction, I did
> int usb_board_init(void)
> {
> printf("usb_board_init\n");
>
> outw(0x18, STBCR3);
> outw(0x18, SRSTR);
> udelay(10);
>
> outw(0x28, EXCPGCR);
> udelay(10);
>
> outw(0x00, STBCR3);
> outw(0x00, SRSTR);
> return 0;
> }
>> These registers are 8-bit width. So please use outb() macro.
They are the same. It is still problem.
> I am sorry, my explanation was short. This EXCPGCR value was for an
> another board.
> In the case of your board, it may be necessary to make it a defferent
> value.
As specification of SH7727, value of EXCPGCR is 0x28 and this means
""
The SH7727 has an on-chip USB interface (USB) which requires a fixed 48-MHz
clock source.
The extend clock pulse generator (EXCPG) generates a divided clock from the
internal clock (I?),
the bus clock (B?), or the external clock (UCLK).
Because the clock sources, which can be a candidate to be used by EXCPG,
vary from CPG
setting or external clock source, user of SH7727 must adjust the divided
clock, carefully to be 48
MHz.
""
* Bits 5 to 3?Clock Select (USBCKSEL2 to USBCKSEL0):
000: Peripheral Clock (P?) (Initial value)
100: Internal Clock (I?)
101: Bus Clock (B?)
110: External clock (UCLK)
***: Another value Reserved (setting prohibited)
* Bits 2 to 0?: Divider Select (USBDIVSEL2 to USBDIVSEL0):
000: 1/1 -> Dividing Ratio Selection
001: 1/2
010: 1/3
1**: Internal clock (I?), bus clock (B?), external clock (UCLK) halted
0x28: 00101000 -> 00 101 000 ->
* 101: Using bus clock
* 000: Dividing Ratio Selection is 1/1
I know
* Internal clock: 96Mhz
* Peripheral Clock: 24Mhz
* CPU Block: 144Mhz
http://www.nabble.com/file/p19449833/a.JPG a.JPG
Please let me know the correct value of EXCPGCR ? Is 0x28 correct initialize
value of USB clock?
> And I used my board, I set 0x1500 in PKCR.
I don't understand PKCR - Port control register so I don't know correct
initialize value of this register.
0x1500 = 0001 0101 0000 0000
-> PK6 is port output
-> PK5 is port output
-> PK4 is port output
I don't know this value could be set for my board - TEngine/SH7727.
I am appreciating your helping :)
--
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-09-12 5:46 ` thaoth
@ 2008-09-12 6:44 ` Yoshihiro Shimoda
2008-09-12 10:05 ` thaoth
0 siblings, 1 reply; 20+ messages in thread
From: Yoshihiro Shimoda @ 2008-09-12 6:44 UTC (permalink / raw)
To: u-boot
Hi, thaoth.
thaoth wrote:
>
> 0x28: 00101000 -> 00 101 000 ->
> * 101: Using bus clock
> * 000: Dividing Ratio Selection is 1/1
>
> I know
> * Internal clock: 96Mhz
> * Peripheral Clock: 24Mhz
> * CPU Block: 144Mhz
>
> http://www.nabble.com/file/p19449833/a.JPG a.JPG
>
> Please let me know the correct value of EXCPGCR ? Is 0x28 correct initialize
> value of USB clock?
I think that 0x21 is correct value of EXCPGCR for your board.
0x21: 00101000 -> 00 100 001 ->
* 100: Using Internal Clock
* 001: Dividing Ratio Selection is 1/2
(96MHz / 2 = 48MHz)
>> And I used my board, I set 0x1500 in PKCR.
> I don't understand PKCR - Port control register so I don't know correct
> initialize value of this register.
>
> 0x1500 = 0001 0101 0000 0000
> -> PK6 is port output
> -> PK5 is port output
> -> PK4 is port output
> I don't know this value could be set for my board - TEngine/SH7727.
Oh, I am very sorry. This is PECR.
This setting enable USB1_pwr_en and USB2_pwr_en pin.
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-09-12 6:44 ` Yoshihiro Shimoda
@ 2008-09-12 10:05 ` thaoth
2008-09-12 10:53 ` Yoshihiro Shimoda
0 siblings, 1 reply; 20+ messages in thread
From: thaoth @ 2008-09-12 10:05 UTC (permalink / raw)
To: u-boot
Hi Yoshihiro Shimoda,
* Strategy 1:
I add usb_cpu_init following your tutorial:
int usb_cpu_init(void)
{
*STCBR3 = 0x18;
*SRSTR = 0x18;
cpu_wait_ms(50);
*EXCPGCR = 0x21;//0x28;
*PECR = 0x1500;
cpu_wait_ms(50);
*SRSTR = 0x00;
*STCBR3 = 0x00;
return 0;
}
now, I plug the USB2.0(mass storage) into board T-Engine(sh7727) and run
command "usb start", the u-boot can't get decription of usb device with the
errror following:
New Device 1
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0
length 0
x8
set address 2
usb_control_msg: request: 0x5, requesttype: 0x0, value 0x2 index 0x0 length
0x0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0
length 0
x12
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0
length 0
x8
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0
length 0
x20
get_conf_no 0 Result 32, wLength 32
if 0, ep 0
if 0, ep 1
##EP epmaxpacketin[1] = 64
* Strategy 2:
I add usb_cpu_init the same strategy 1, I only add instruction "printf("&ep
= %x\n",&ep);" into function usb_set_maxpacket of usb.c
int usb_set_maxpacket(struct usb_device *dev)
{
.................................................
...................................................
ep = &dev->config.if_desc[i].ep_desc[ii];
b=ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
printf("&ep = %x\n",&ep);
.....................................................
......................................................
}
in this strategy, when I run command "usb start", now I can get information
of USB device:
Manufacturer
Product USB_DRIVE
SerialNumber 000000000000001000006886
2 USB Device(s) found
scanning bus for storage devices... usb_control_msg: request: 0xFF,
reque
sttype: 0x21, value 0x0 index 0x0 length 0x0
usb_control_msg: request: 0x1, requesttype: 0x2, value 0x0 index 0x81 length
0x0
usb_control_msg: request: 0x1, requesttype: 0x2, value 0x0 index 0x2 length
0x0
1 Storage Device(s) found
I don't know what is problem?why when I add instruction "printf("&ep =
%x\n",&ep);", u-boot can get description of USB device
*Strategy 3:
I try replace the insctruction "printf("&ep = %x\n",&ep);" with one of these
instructions
- instruction 1: wait_ms(10)
- instruction 2:void * pointer = &ep;
- instruction 3: "printf("ep = %x\n",ep);"
But the result when run command "usb start" the same strategy 1, I can't get
information of USB2.0(mass storage)
Can you help me to resolve this bug?
Thank you very much for your supports!
Yoshihiro Shimoda wrote:
>
> Hi, thaoth.
>
> thaoth wrote:
>>
>> 0x28: 00101000 -> 00 101 000 ->
>> * 101: Using bus clock
>> * 000: Dividing Ratio Selection is 1/1
>>
>> I know
>> * Internal clock: 96Mhz
>> * Peripheral Clock: 24Mhz
>> * CPU Block: 144Mhz
>>
>> http://www.nabble.com/file/p19449833/a.JPG a.JPG
>>
>> Please let me know the correct value of EXCPGCR ? Is 0x28 correct
>> initialize
>> value of USB clock?
>
> I think that 0x21 is correct value of EXCPGCR for your board.
>
> 0x21: 00101000 -> 00 100 001 ->
> * 100: Using Internal Clock
> * 001: Dividing Ratio Selection is 1/2
> (96MHz / 2 = 48MHz)
>
>>> And I used my board, I set 0x1500 in PKCR.
>> I don't understand PKCR - Port control register so I don't know correct
>> initialize value of this register.
>>
>> 0x1500 = 0001 0101 0000 0000
>> -> PK6 is port output
>> -> PK5 is port output
>> -> PK4 is port output
>> I don't know this value could be set for my board - TEngine/SH7727.
>
> Oh, I am very sorry. This is PECR.
> This setting enable USB1_pwr_en and USB2_pwr_en pin.
>
> Best regards,
> Yoshihiro Shimoda
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-09-12 10:05 ` thaoth
@ 2008-09-12 10:53 ` Yoshihiro Shimoda
2008-09-12 10:58 ` thaoth
0 siblings, 1 reply; 20+ messages in thread
From: Yoshihiro Shimoda @ 2008-09-12 10:53 UTC (permalink / raw)
To: u-boot
Hi, thaoth
thaoth wrote:
> Can you help me to resolve this bug?
I think that it is a problem of the unalignment access.
Please change your compiler or change a source code as follows:
diff --git a/common/usb.c b/common/usb.c
index 9502f39..1acf51d 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -250,7 +250,10 @@ int usb_set_maxpacket(struct usb_device *dev)
for(i=0; i<dev->config.bNumInterfaces;i++) {
for(ii=0; ii<dev->config.if_desc[i].bNumEndpoints; ii++) {
- ep = &dev->config.if_desc[i].ep_desc[ii];
+ struct usb_endpoint_descriptor tmp;
+ memcpy(&tmp, &dev->config.if_desc[i].ep_desc[ii],
+ sizeof(struct usb_endpoint_descriptor));
+ ep = &tmp;
b=ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
if((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)==USB_ENDPOINT_XFER_CONTROL) { /* Control => bidirectional */
> Thank you very much for your supports!
You're welcome! :)
Best regards,
Yoshihiro Shimoda
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
2008-09-12 10:53 ` Yoshihiro Shimoda
@ 2008-09-12 10:58 ` thaoth
0 siblings, 0 replies; 20+ messages in thread
From: thaoth @ 2008-09-12 10:58 UTC (permalink / raw)
To: u-boot
Hi,
Yoshihiro Shimoda wrote:
>
>
> diff --git a/common/usb.c b/common/usb.c
> index 9502f39..1acf51d 100644
> --- a/common/usb.c
> +++ b/common/usb.c
> @@ -250,7 +250,10 @@ int usb_set_maxpacket(struct usb_device *dev)
>
> for(i=0; i<dev->config.bNumInterfaces;i++) {
> for(ii=0; ii<dev->config.if_desc[i].bNumEndpoints; ii++) {
> - ep = &dev->config.if_desc[i].ep_desc[ii];
> + struct usb_endpoint_descriptor tmp;
> + memcpy(&tmp, &dev->config.if_desc[i].ep_desc[ii],
> + sizeof(struct usb_endpoint_descriptor));
> + ep = &tmp;
> b=ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
>
> if((ep->bmAttributes &
> USB_ENDPOINT_XFERTYPE_MASK)==USB_ENDPOINT_XFER_CONTROL) { /* Control =>
> bidirectional */
>
Thank you a lot, it worked well. :jumping::jumping::jumping::jumping:
Thank you for good instruction.
Best regards,
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end of thread, other threads:[~2008-09-12 10:58 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-08-07 11:03 [U-Boot-Users] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit thaoth
2008-08-08 1:35 ` Nobuhiro Iwamatsu
2008-08-08 7:51 ` thaoth
2008-08-08 8:59 ` Nobuhiro Iwamatsu
2008-08-20 4:02 ` [U-Boot] " thaoth
2008-08-20 7:40 ` Nobuhiro Iwamatsu
2008-08-21 7:26 ` thaoth
2008-08-21 9:54 ` thaoth
2008-08-21 11:27 ` thaoth
2008-09-03 3:48 ` thaoth
2008-09-10 11:51 ` thaoth
2008-09-10 12:13 ` Nobuhiro Iwamatsu
2008-09-11 2:17 ` Yoshihiro Shimoda
2008-09-11 7:41 ` thaoth
2008-09-11 12:00 ` Yoshihiro Shimoda
2008-09-12 5:46 ` thaoth
2008-09-12 6:44 ` Yoshihiro Shimoda
2008-09-12 10:05 ` thaoth
2008-09-12 10:53 ` Yoshihiro Shimoda
2008-09-12 10:58 ` thaoth
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