[U-Boot] Malformed ARP packets

[Jerry Van Baren <gvb.uboot@gmail.com>]

Remi Lefevre wrote:
> Hello,
> 
> I ported U-Boot on my custom MPC8270 board.
> Everything seems to go well but my ARP packets are malformed:

[snip]

> [60 bytes on wire]                                            <- correct
>           correct broadcast  correct mac addr   ARP type
>           ----------------- ------------------ -----------
> 00000000  ff ff ff ff ff ff da b0  4e 0f 0a 26 08 06 00 01  | <- correct
> 00000010  4e 0f 0a 26 08 06 00 01  4e 0f 0a 26 08 06 00 01  | <- malformed
> 00000020  00 00 00 00 00 00 c0 a8  00 01 00 00 00 00 00 00  | <- correct
> 00000030  c0 a8 00 01 00 00 00 00  00 00 00 01              | <- malformed
> 0000003c
> 
> The source mac address seems incorrectly and partially duplicated at
> byte 16. Data is not random, but duplicated or mispositioned.
> 
> I saw the following thread:
> http://lists.denx.de/pipermail/u-boot/2008-January/028159.html
> 
> So I checked and double-checked my SDRAM configuration but cannot
> find anything wrong. I also get the same results in BBI or PBI.

Is this DIMM memory sticks with using SPD configuration or are the SDRAM 
chips soldered to the board?

This really smells of misconfigured SDRAM where your SDRAM *timing* is 
wrong.  It really looks like your DMA engine is latching the "next" bus 
cycle while your SDRAM is still presenting the previous data.  IOW, your 
memory is slower than your SDRAM controller is configured for.

Did you verify the SDRAM databook timing vs. what you configured your 
SDRAM controller to do?  Did the hardware engineer that made the board 
verify your configuration?  Did he give you a good configuration?  If 
so, are you sure it is good??? (never trust the hardware weenies ;-)

Did you read and understand <http://www.denx.de/wiki/view/DULG/SDRAM> ?

If you are sure of the timing, I would suggest you write a simple test 
application that DMAs from flash to RAM and verifies it, DMAs from RAM 
to RAM and verifies it, if possible do two simultaneous DMAs from A->B 
and C->D so that you are exercising the SDRAM pipelining vigorously.

> MII monitoring works correctly:
> => mii dump

This is meaningless for the problem at hand.  The problem is the DMA 
from SDRAM into the ethernet MAC is messed up.  You are messed up before 
the PHY gets in the picture.

[snip]

> Anything I could have forgotten to check ?
> 
> Best regards,
> R?mi Lefevre

In real estate the three most important things are "location, location, 
location."  In engineering, they are "timing, timing, timing."

HTH,
gvb