[U-Boot] [PATCH 0/3] ADS5121: PATA support

[U-Boot] [PATCH 0/3] ADS5121: PATA support

[Wolfgang Denk]

The following patches add P-ATA support to the ADS5121 board.

Ralph Kondziella wrote the code, I cleaned it up, and fixed some
obvious problems.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is clear that the individual who persecutes a  man,  his  brother,
because he is not of the same opinion, is a monster.       - Voltaire

[U-Boot] [PATCH 1/3] ADS5121: add LPC clock support

[Wolfgang Denk]

From: Ralph Kondziella <rk@argos-messtechnik.de>

(needed for PATA support)

Signed-off-by: Ralph Kondziella <rk@argos-messtechnik.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 cpu/mpc512x/speed.c           |   13 ++++++++++++-
 include/asm-ppc/global_data.h |    1 +
 include/mpc512x.h             |    4 ++++
 3 files changed, 17 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c
index e62477b..24ec062 100644
--- a/cpu/mpc512x/speed.c
+++ b/cpu/mpc512x/speed.c
@@ -68,6 +68,7 @@ int get_clocks (void)
 	u8 sys_div;
 	u8 ips_div;
 	u8 pci_div;
+	u8 lpc_div;
 	u32 ref_clk = CFG_MPC512X_CLKIN;
 	u32 spll;
 	u32 sys_clk;
@@ -75,6 +76,7 @@ int get_clocks (void)
 	u32 csb_clk;
 	u32 ips_clk;
 	u32 pci_clk;
+	u32 lpc_clk;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
@@ -101,15 +103,23 @@ int get_clocks (void)
 	if (pci_div != 0) {
 		pci_clk = csb_clk / pci_div;
 	} else {
-		/* in case we cannot get a sane IPS divisor, fail gracefully */
+		/* in case we cannot get a sane PCI divisor, fail gracefully */
 		pci_clk = 333333;
 	}
+	lpc_div = (im->clk.scfr[0] & SCFR1_LPC_DIV_MASK) >> SCFR1_LPC_DIV_SHIFT;
+	if (lpc_div != 0) {
+		lpc_clk = ips_clk / lpc_div;
+	} else {
+		/* in case we cannot get a sane LPC divisor, fail gracefully */
+		lpc_clk = 0;
+	}
 
 	gd->ips_clk = ips_clk;
 	gd->pci_clk = pci_clk;
 	gd->csb_clk = csb_clk;
 	gd->cpu_clk = core_clk;
 	gd->bus_clk = csb_clk;
+	gd->lpc_clk = lpc_clk;
 	return 0;
 
 }
@@ -130,6 +140,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
 	printf("  IPS Bus:             %4d MHz\n", gd->ips_clk / 1000000);
 	printf("  PCI:                 %4d MHz\n", gd->pci_clk / 1000000);
+	printf("  LPC:                 %4d MHz\n", gd->lpc_clk / 1000000);
 	printf("  DDR:                 %4d MHz\n", 2 * gd->csb_clk / 1000000);
 	return 0;
 }
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 4331a15..d1d075f 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -110,6 +110,7 @@ typedef	struct	global_data {
 	u32 ips_clk;
 	u32 csb_clk;
 	u32 pci_clk;
+	u32 lpc_clk;
 #endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC8220)
 	unsigned long   bExtUart;
diff --git a/include/mpc512x.h b/include/mpc512x.h
index cb418d1..1f808ca 100644
--- a/include/mpc512x.h
+++ b/include/mpc512x.h
@@ -191,6 +191,10 @@
 #define SCFR1_IPS_DIV_MASK		0x03800000
 #define SCFR1_IPS_DIV_SHIFT		23
 
+#define SCFR1_LPC_DIV			0x2
+#define SCFR1_LPC_DIV_MASK		0x00003800
+#define SCFR1_LPC_DIV_SHIFT		11
+
 #define SCFR1_PCI_DIV			0x6
 #define SCFR1_PCI_DIV_MASK		0x00700000
 #define SCFR1_PCI_DIV_SHIFT		20
-- 
1.5.5.1

[U-Boot] [PATCH 2/3] ADS5121: add PATA support

[Wolfgang Denk]

From: Ralph Kondziella <rk@argos-messtechnik.de>

Signed-off-by: Ralph Kondziella <rk@argos-messtechnik.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 board/ads5121/ads5121.c      |  103 ++++++++++++++++++++++++++++++++++++++++++
 common/cmd_ide.c             |    4 ++
 include/asm-ppc/immap_512x.h |   29 +++++++++++-
 include/configs/ads5121.h    |   52 +++++++++++++++++++++
 include/mpc512x.h            |    1 +
 5 files changed, 188 insertions(+), 1 deletions(-)

diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index deaa292..1e19f32 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -31,6 +31,8 @@
 #include <i2c.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Clocks in use */
 #define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
 			 CLOCK_SCCR1_LPC_EN |				\
@@ -38,6 +40,7 @@
 			 CLOCK_SCCR1_PSCFIFO_EN |			\
 			 CLOCK_SCCR1_DDR_EN |				\
 			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_PATA_EN |				\
 			 CLOCK_SCCR1_PCI_EN |				\
 			 CLOCK_SCCR1_TPR_EN)
 
@@ -312,3 +315,104 @@ void ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	debug ("init_ide_reset\n");
+
+	/*
+	 * Clear the reset bit to reset the interface
+	 * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
+	 */
+	immr->pata.pata_ata_control = 0;
+	udelay(100);
+	/* Assert the reset bit to enable the interface */
+	immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
+	udelay(100);
+
+}
+
+void ide_set_reset (int idereset)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	debug ("ide_set_reset(%d)\n", idereset);
+
+	if (idereset) {
+		immr->pata.pata_ata_control = 0;
+		udelay(100);
+	} else {
+		immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
+		udelay(100);
+	}
+}
+
+#define CALC_TIMING(t) (t + period - 1) / period
+
+int ide_preinit (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	long t;
+	const struct {
+		short t0;
+		short t1;
+		short t2_8;
+		short t2_16;
+		short t2i;
+		short t4;
+		short t9;
+		short tA;
+	} pio_specs = {
+		.t0    = 600,
+		.t1    =  70,
+		.t2_8  = 290,
+		.t2_16 = 165,
+		.t2i   =   0,
+		.t4    =  30,
+		.t9    =  20,
+		.tA    =  50,
+	};
+	union {
+		u32 config;
+		struct {
+			u8 field1;
+			u8 field2;
+			u8 field3;
+			u8 field4;
+		}bytes;
+	}cfg;
+
+	debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
+		(u32)&immr->pata);
+
+	/* Set the reset bit to 1 to enable the interface */
+	immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
+
+	/* Init timings : we use PIO mode 0 timings */
+	t = 1000000000 / gd->lpc_clk;	/* period in ns */
+	cfg.bytes.field1 = 3;
+	cfg.bytes.field2 = 3;
+	cfg.bytes.field3 = (pio_specs.t1 + t) / t;
+	cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
+
+	immr->pata.pata_time1 = cfg.config;
+
+	cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
+	cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
+	cfg.bytes.field3 = 1;
+	cfg.bytes.field4 = (pio_specs.t4 + t) / t;
+
+	immr->pata.pata_time2 = cfg.config;
+
+	cfg.config = immr->pata.pata_time3;
+	cfg.bytes.field1 = (pio_specs.t9 + t) / t;
+
+	immr->pata.pata_time3 = cfg.config;
+	debug ("PATA preinit complete.\n");
+
+	return 0;
+}
+
+#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index 2fcaff8..0eb5366 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -45,6 +45,10 @@
 #include <mpc5xxx.h>
 #endif
 
+#ifdef CONFIG_MPC512X
+#include <mpc512x.h>
+#endif
+
 #include <ide.h>
 #include <ata.h>
 
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index cd90945..489dbe4 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -451,7 +451,34 @@ typedef struct lpc512x {
  * PATA
  */
 typedef struct pata512x {
-	u8 fixme[0x100];
+	/* LOCAL Registers */
+	u32 pata_time1;		/* Time register 1: PIO and tx timing parameter */
+	u32 pata_time2;		/* Time register 2: PIO timing parameter */
+	u32 pata_time3;		/* Time register 3: PIO and MDMA timing parameter */
+	u32 pata_time4;		/* Time register 4: MDMA and UDMA timing parameter */
+	u32 pata_time5;		/* Time register 5: UDMA timing parameter */
+	u32 pata_time6;		/* Time register 6: UDMA timing parameter */
+	u32 pata_fifo_data32;   /* 32bit wide dataport to/from FIFO */
+	u32 pata_fifo_data16;   /* 16bit wide dataport to/from FIFO */
+	u32 pata_fifo_fill;	/* FIFO filling in halfwords (READONLY)*/
+	u32 pata_ata_control;   /* ATA Interface control register */
+	u32 pata_irq_pending;   /* Interrupt pending register (READONLY) */
+	u32 pata_irq_enable;	/* Interrupt enable register */
+	u32 pata_irq_clear;	/* Interrupt clear register (WRITEONLY)*/
+	u32 pata_fifo_alarm;	/* fifo alarm threshold */
+	u32 res1[0x1A];
+	/* DRIVE Registers */
+	u32 pata_drive_data;	/* drive data register*/
+	u32 pata_drive_features;/* drive features register */
+	u32 pata_drive_sectcnt; /* drive sector count register */
+	u32 pata_drive_sectnum; /* drive sector number register */
+	u32 pata_drive_cyllow;  /* drive cylinder low register */
+	u32 pata_drive_cylhigh; /* drive cylinder high register */
+	u32 pata_drive_dev_head;/* drive device head register */
+	u32 pata_drive_command; /* write = drive command, read = drive status reg */
+	u32 res2[0x06];
+	u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
+	u32 res3[0x09];
 } pata512x_t;
 
 /*
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index d6f7e02..d9fe795 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -348,11 +348,19 @@
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DATE
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #endif
 
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#endif /* defined(CONFIG_CMD_IDE) */
+
 /*
  * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
  * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
@@ -489,4 +497,48 @@
 #define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH		"/soc at 80000000/serial at 11300"
 
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	MPC512X_PATA
+
+/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
+#define CFG_ATA_DATA_OFFSET	(0x00A0)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
+#define CFG_ATA_ALT_OFFSET	(0x00D8)
+
+/* Interval between registers	*/
+#define CFG_ATA_STRIDE		4
+
+#define ATA_BASE_ADDR		MPC512X_PATA
+
+/*
+ * Control register bit definitions
+ */
+#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
+#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
+#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
+#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
+#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
+#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
+#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
+#define FSL_ATA_CTRL_IORDY_EN		0x01000000
+
 #endif	/* __CONFIG_H */
diff --git a/include/mpc512x.h b/include/mpc512x.h
index 1f808ca..3ba70f8 100644
--- a/include/mpc512x.h
+++ b/include/mpc512x.h
@@ -577,6 +577,7 @@ void iopin_initialize(iopin_t *,int);
 
  /* Register Offset Base */
 #define MPC512X_FEC		(CFG_IMMR + 0x02800)
+#define MPC512X_PATA		(CFG_IMMR + 0x10200)
 
 /* Number of I2C buses */
 #define I2C_BUS_CNT	3
-- 
1.5.5.1

[U-Boot] [PATCH 3/3] ADS5121: Code cleanup

[Wolfgang Denk]

From: Ralph Kondziella <rk@argos-messtechnik.de>

Fix compiler warnings, sort lists, update (C) entries.

Signed-off-by: Ralph Kondziella <rk@argos-messtechnik.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 board/ads5121/ads5121.c       |   34 +++++++++++++++++-----------------
 common/cmd_ide.c              |    2 +-
 cpu/mpc512x/speed.c           |    2 +-
 include/asm-ppc/global_data.h |    2 +-
 include/asm-ppc/immap_512x.h  |    2 +-
 include/configs/ads5121.h     |   12 ++++++------
 6 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index 1e19f32..8bf862d 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 DENX Software Engineering
+ * (C) Copyright 2007-2008 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -34,20 +34,20 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* Clocks in use */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
-			 CLOCK_SCCR1_DDR_EN |				\
-			 CLOCK_SCCR1_FEC_EN |				\
-			 CLOCK_SCCR1_PATA_EN |				\
-			 CLOCK_SCCR1_PCI_EN |				\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN)
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN	| \
+			 CLOCK_SCCR1_DDR_EN	| \
+			 CLOCK_SCCR1_FEC_EN	| \
+			 CLOCK_SCCR1_LPC_EN	| \
+			 CLOCK_SCCR1_PATA_EN	| \
+			 CLOCK_SCCR1_PCI_EN	| \
+			 CLOCK_SCCR1_PSCFIFO_EN	| \
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+			 CLOCK_SCCR1_TPR_EN	)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_DIU_EN	| \
+			 CLOCK_SCCR2_I2C_EN	| \
+			 CLOCK_SCCR2_MEM_EN	| \
+			 CLOCK_SCCR2_SPDIF_EN	)
 
 #define CSAW_START(start)	((start) & 0xFFFF0000)
 #define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
@@ -225,14 +225,14 @@ int misc_init_r(void)
 	/* Verify if enabled */
 	tmp_val = 0;
 	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
-	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
 
 	tmp_val = 0x10;
 	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 	/* Verify if enabled */
 	tmp_val = 0;
 	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
-	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
 
 #ifdef CONFIG_FSL_DIU_FB
 #if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index 0eb5366..bf8f7f9 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
  *
  * See file CREDITS for list of people who contributed to this
diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c
index 24ec062..d6b7001 100644
--- a/cpu/mpc512x/speed.c
+++ b/cpu/mpc512x/speed.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2007
+ * (C) Copyright 2000-2008
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
  *
  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index d1d075f..c7346b9 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2008
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
  *
  * See file CREDITS for list of people who contributed to this
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index 489dbe4..d63ef6d 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 DENX Software Engineering
+ * (C) Copyright 2007-2008 DENX Software Engineering
  *
  * MPC512x Internal Memory Map
  *
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index d9fe795..c200335 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -340,16 +340,16 @@
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_EXT2
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
@@ -378,9 +378,9 @@
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #ifdef CONFIG_CMD_KGDB
-	#define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+# define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+# define CFG_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
 
-- 
1.5.5.1

[U-Boot] [PATCH 1/3] ADS5121: add LPC clock support

[John Rigby]

This confused me a little bit. I didn't know that the PATA had anything 
to do with the LPC clock. The table in the clock chapter says that the 
PATA clock comes from the IPS clock. I think the confusion is from PATA 
chapter section 28.2.2.1:

    Table 28-4 shows various timing parameters affected by internal and
    external factors to the MPC5121e.
    One parameter, T, is the PATA bus clock period. This is the same as
    the LPC_CLK frequency. Some
    parameters (ti_ds, tco, tskew2, etc.) are a function of the MPC5121e
    and the microcontroller top-level
    design controls them. Characteristics of the transceiver or
    isolation buffer between the MPC5121e and the
    external ATA device control other parameters. Also, characteristics
    of the ATA cable connecting the
    MPC5121e and the external ATA device controls other parameters.
    Most of the timing parameters controlling the various PATA bus
    signals are programmed in increments of
    the ATA bus clock period, which is the same as the LocalPlus bus
    clock period. PATA bus timing
    parameters are programmed in increments of the ATA bus frequency,
    which is the same as the LocalPlus
    bus frequency. A standard ATA bus clock frequency is 66 MHz, which
    has a period of 15 ns.

This is confusing to me. The new rev2 silicon manual says:

    Table 27-3 shows various timing parameters affected by internal and
    external factors to the MPC5121e.
    One parameter, T, is the PATA bus clock period. This is the same as
    the LPC_CLK frequency when
    LPC_DIV of SCFR register in clock block is set to 3?b001. See
    section 6.4.1.4. Some parameters (ti_ds,
    tco, tskew2, etc.) are a function of the MPC5121e and the
    microcontroller top-level design controls them.
    Characteristics of the transceiver or isolation buffer between the
    MPC5121e and the external ATA device
    control other parameters. Also, characteristics of the ATA cable
    connecting the MPC5121e and the
    external ATA device controls other parameters.
    Most of the timing parameters controlling the various PATA bus
    signals are programmed in increments of
    the ATA bus clock period. A standard ATA bus clock frequency is 66
    MHz, which has a period of 15 ns.

I'm going to followup with the HW guys and see what the truth is. I know 
my linux PATA driver uses the PATA bus clk for timing calculation and it 
works fine.

John

Wolfgang Denk wrote:
> From: Ralph Kondziella <rk@argos-messtechnik.de>
>
> (needed for PATA support)
>
> Signed-off-by: Ralph Kondziella <rk@argos-messtechnik.de>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> ---
>  cpu/mpc512x/speed.c           |   13 ++++++++++++-
>  include/asm-ppc/global_data.h |    1 +
>  include/mpc512x.h             |    4 ++++
>  3 files changed, 17 insertions(+), 1 deletions(-)
>
> diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c
> index e62477b..24ec062 100644
> --- a/cpu/mpc512x/speed.c
> +++ b/cpu/mpc512x/speed.c
> @@ -68,6 +68,7 @@ int get_clocks (void)
>  	u8 sys_div;
>  	u8 ips_div;
>  	u8 pci_div;
> +	u8 lpc_div;
>  	u32 ref_clk = CFG_MPC512X_CLKIN;
>  	u32 spll;
>  	u32 sys_clk;
> @@ -75,6 +76,7 @@ int get_clocks (void)
>  	u32 csb_clk;
>  	u32 ips_clk;
>  	u32 pci_clk;
> +	u32 lpc_clk;
>  
>  	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
>  		return -1;
> @@ -101,15 +103,23 @@ int get_clocks (void)
>  	if (pci_div != 0) {
>  		pci_clk = csb_clk / pci_div;
>  	} else {
> -		/* in case we cannot get a sane IPS divisor, fail gracefully */
> +		/* in case we cannot get a sane PCI divisor, fail gracefully */
>  		pci_clk = 333333;
>  	}
> +	lpc_div = (im->clk.scfr[0] & SCFR1_LPC_DIV_MASK) >> SCFR1_LPC_DIV_SHIFT;
> +	if (lpc_div != 0) {
> +		lpc_clk = ips_clk / lpc_div;
> +	} else {
> +		/* in case we cannot get a sane LPC divisor, fail gracefully */
> +		lpc_clk = 0;
> +	}
>  
>  	gd->ips_clk = ips_clk;
>  	gd->pci_clk = pci_clk;
>  	gd->csb_clk = csb_clk;
>  	gd->cpu_clk = core_clk;
>  	gd->bus_clk = csb_clk;
> +	gd->lpc_clk = lpc_clk;
>  	return 0;
>  
>  }
> @@ -130,6 +140,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
>  	printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
>  	printf("  IPS Bus:             %4d MHz\n", gd->ips_clk / 1000000);
>  	printf("  PCI:                 %4d MHz\n", gd->pci_clk / 1000000);
> +	printf("  LPC:                 %4d MHz\n", gd->lpc_clk / 1000000);
>  	printf("  DDR:                 %4d MHz\n", 2 * gd->csb_clk / 1000000);
>  	return 0;
>  }
> diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
> index 4331a15..d1d075f 100644
> --- a/include/asm-ppc/global_data.h
> +++ b/include/asm-ppc/global_data.h
> @@ -110,6 +110,7 @@ typedef	struct	global_data {
>  	u32 ips_clk;
>  	u32 csb_clk;
>  	u32 pci_clk;
> +	u32 lpc_clk;
>  #endif /* CONFIG_MPC512X */
>  #if defined(CONFIG_MPC8220)
>  	unsigned long   bExtUart;
> diff --git a/include/mpc512x.h b/include/mpc512x.h
> index cb418d1..1f808ca 100644
> --- a/include/mpc512x.h
> +++ b/include/mpc512x.h
> @@ -191,6 +191,10 @@
>  #define SCFR1_IPS_DIV_MASK		0x03800000
>  #define SCFR1_IPS_DIV_SHIFT		23
>  
> +#define SCFR1_LPC_DIV			0x2
> +#define SCFR1_LPC_DIV_MASK		0x00003800
> +#define SCFR1_LPC_DIV_SHIFT		11
> +
>  #define SCFR1_PCI_DIV			0x6
>  #define SCFR1_PCI_DIV_MASK		0x00700000
>  #define SCFR1_PCI_DIV_SHIFT		20
>   

[U-Boot] [PATCH 1/3] ADS5121: add LPC clock support

[John Rigby]

Ralph, Wolfgang:

I have checked with the 5121 validation code for PATA and it uses the 
IPS clock for all the timing.  I think the old rev1 manual is wrong and 
the new rev2 manual is misleading.  The PATA clock is the same speed as 
the IPS clock.  Don't use the LPC clock.

John

John Rigby wrote:
> This confused me a little bit. I didn't know that the PATA had 
> anything to do with the LPC clock. The table in the clock chapter says 
> that the PATA clock comes from the IPS clock. I think the confusion is 
> from PATA chapter section 28.2.2.1:
>
>    Table 28-4 shows various timing parameters affected by internal and
>    external factors to the MPC5121e.
>    One parameter, T, is the PATA bus clock period. This is the same as
>    the LPC_CLK frequency. Some
>    parameters (ti_ds, tco, tskew2, etc.) are a function of the MPC5121e
>    and the microcontroller top-level
>    design controls them. Characteristics of the transceiver or
>    isolation buffer between the MPC5121e and the
>    external ATA device control other parameters. Also, characteristics
>    of the ATA cable connecting the
>    MPC5121e and the external ATA device controls other parameters.
>    Most of the timing parameters controlling the various PATA bus
>    signals are programmed in increments of
>    the ATA bus clock period, which is the same as the LocalPlus bus
>    clock period. PATA bus timing
>    parameters are programmed in increments of the ATA bus frequency,
>    which is the same as the LocalPlus
>    bus frequency. A standard ATA bus clock frequency is 66 MHz, which
>    has a period of 15 ns.
>
> This is confusing to me. The new rev2 silicon manual says:
>
>    Table 27-3 shows various timing parameters affected by internal and
>    external factors to the MPC5121e.
>    One parameter, T, is the PATA bus clock period. This is the same as
>    the LPC_CLK frequency when
>    LPC_DIV of SCFR register in clock block is set to 3?b001. See
>    section 6.4.1.4. Some parameters (ti_ds,
>    tco, tskew2, etc.) are a function of the MPC5121e and the
>    microcontroller top-level design controls them.
>    Characteristics of the transceiver or isolation buffer between the
>    MPC5121e and the external ATA device
>    control other parameters. Also, characteristics of the ATA cable
>    connecting the MPC5121e and the
>    external ATA device controls other parameters.
>    Most of the timing parameters controlling the various PATA bus
>    signals are programmed in increments of
>    the ATA bus clock period. A standard ATA bus clock frequency is 66
>    MHz, which has a period of 15 ns.
>
> I'm going to followup with the HW guys and see what the truth is. I 
> know my linux PATA driver uses the PATA bus clk for timing calculation 
> and it works fine.
>
> John
>
> Wolfgang Denk wrote:
>> From: Ralph Kondziella <rk@argos-messtechnik.de>
>>
>> (needed for PATA support)
>>
>> Signed-off-by: Ralph Kondziella <rk@argos-messtechnik.de>
>> Signed-off-by: Wolfgang Denk <wd@denx.de>
>> ---
>>  cpu/mpc512x/speed.c           |   13 ++++++++++++-
>>  include/asm-ppc/global_data.h |    1 +
>>  include/mpc512x.h             |    4 ++++
>>  3 files changed, 17 insertions(+), 1 deletions(-)
>>
>> diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c
>> index e62477b..24ec062 100644
>> --- a/cpu/mpc512x/speed.c
>> +++ b/cpu/mpc512x/speed.c
>> @@ -68,6 +68,7 @@ int get_clocks (void)
>>      u8 sys_div;
>>      u8 ips_div;
>>      u8 pci_div;
>> +    u8 lpc_div;
>>      u32 ref_clk = CFG_MPC512X_CLKIN;
>>      u32 spll;
>>      u32 sys_clk;
>> @@ -75,6 +76,7 @@ int get_clocks (void)
>>      u32 csb_clk;
>>      u32 ips_clk;
>>      u32 pci_clk;
>> +    u32 lpc_clk;
>>  
>>      if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
>>          return -1;
>> @@ -101,15 +103,23 @@ int get_clocks (void)
>>      if (pci_div != 0) {
>>          pci_clk = csb_clk / pci_div;
>>      } else {
>> -        /* in case we cannot get a sane IPS divisor, fail gracefully */
>> +        /* in case we cannot get a sane PCI divisor, fail gracefully */
>>          pci_clk = 333333;
>>      }
>> +    lpc_div = (im->clk.scfr[0] & SCFR1_LPC_DIV_MASK) >> 
>> SCFR1_LPC_DIV_SHIFT;
>> +    if (lpc_div != 0) {
>> +        lpc_clk = ips_clk / lpc_div;
>> +    } else {
>> +        /* in case we cannot get a sane LPC divisor, fail gracefully */
>> +        lpc_clk = 0;
>> +    }
>>  
>>      gd->ips_clk = ips_clk;
>>      gd->pci_clk = pci_clk;
>>      gd->csb_clk = csb_clk;
>>      gd->cpu_clk = core_clk;
>>      gd->bus_clk = csb_clk;
>> +    gd->lpc_clk = lpc_clk;
>>      return 0;
>>  
>>  }
>> @@ -130,6 +140,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int 
>> argc, char *argv[])
>>      printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
>>      printf("  IPS Bus:             %4d MHz\n", gd->ips_clk / 1000000);
>>      printf("  PCI:                 %4d MHz\n", gd->pci_clk / 1000000);
>> +    printf("  LPC:                 %4d MHz\n", gd->lpc_clk / 1000000);
>>      printf("  DDR:                 %4d MHz\n", 2 * gd->csb_clk / 
>> 1000000);
>>      return 0;
>>  }
>> diff --git a/include/asm-ppc/global_data.h 
>> b/include/asm-ppc/global_data.h
>> index 4331a15..d1d075f 100644
>> --- a/include/asm-ppc/global_data.h
>> +++ b/include/asm-ppc/global_data.h
>> @@ -110,6 +110,7 @@ typedef    struct    global_data {
>>      u32 ips_clk;
>>      u32 csb_clk;
>>      u32 pci_clk;
>> +    u32 lpc_clk;
>>  #endif /* CONFIG_MPC512X */
>>  #if defined(CONFIG_MPC8220)
>>      unsigned long   bExtUart;
>> diff --git a/include/mpc512x.h b/include/mpc512x.h
>> index cb418d1..1f808ca 100644
>> --- a/include/mpc512x.h
>> +++ b/include/mpc512x.h
>> @@ -191,6 +191,10 @@
>>  #define SCFR1_IPS_DIV_MASK        0x03800000
>>  #define SCFR1_IPS_DIV_SHIFT        23
>>  
>> +#define SCFR1_LPC_DIV            0x2
>> +#define SCFR1_LPC_DIV_MASK        0x00003800
>> +#define SCFR1_LPC_DIV_SHIFT        11
>> +
>>  #define SCFR1_PCI_DIV            0x6
>>  #define SCFR1_PCI_DIV_MASK        0x00700000
>>  #define SCFR1_PCI_DIV_SHIFT        20
>>   
>
>

[U-Boot] [PATCH 1/3] ADS5121: add LPC clock support

[Wolfgang Denk]

Dear Ralph,

in message <48DEC94D.4090403@freescale.com> John Rigby wrote:
> This confused me a little bit. I didn't know that the PATA had anything 
> to do with the LPC clock. The table in the clock chapter says that the 
> PATA clock comes from the IPS clock. I think the confusion is from PATA 
> chapter section 28.2.2.1:
...
> I'm going to followup with the HW guys and see what the truth is. I know 
> my linux PATA driver uses the PATA bus clk for timing calculation and it 
> works fine.

Do you happen to have an update for your P-ATA patch?

Best regards,

Wolfgang Denk

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