[U-Boot] [PATCH 1/3] ADS5121: add LPC clock support

[John Rigby <jrigby@freescale.com>]

Ralph, Wolfgang:

I have checked with the 5121 validation code for PATA and it uses the 
IPS clock for all the timing.  I think the old rev1 manual is wrong and 
the new rev2 manual is misleading.  The PATA clock is the same speed as 
the IPS clock.  Don't use the LPC clock.

John

John Rigby wrote:
> This confused me a little bit. I didn't know that the PATA had 
> anything to do with the LPC clock. The table in the clock chapter says 
> that the PATA clock comes from the IPS clock. I think the confusion is 
> from PATA chapter section 28.2.2.1:
>
>    Table 28-4 shows various timing parameters affected by internal and
>    external factors to the MPC5121e.
>    One parameter, T, is the PATA bus clock period. This is the same as
>    the LPC_CLK frequency. Some
>    parameters (ti_ds, tco, tskew2, etc.) are a function of the MPC5121e
>    and the microcontroller top-level
>    design controls them. Characteristics of the transceiver or
>    isolation buffer between the MPC5121e and the
>    external ATA device control other parameters. Also, characteristics
>    of the ATA cable connecting the
>    MPC5121e and the external ATA device controls other parameters.
>    Most of the timing parameters controlling the various PATA bus
>    signals are programmed in increments of
>    the ATA bus clock period, which is the same as the LocalPlus bus
>    clock period. PATA bus timing
>    parameters are programmed in increments of the ATA bus frequency,
>    which is the same as the LocalPlus
>    bus frequency. A standard ATA bus clock frequency is 66 MHz, which
>    has a period of 15 ns.
>
> This is confusing to me. The new rev2 silicon manual says:
>
>    Table 27-3 shows various timing parameters affected by internal and
>    external factors to the MPC5121e.
>    One parameter, T, is the PATA bus clock period. This is the same as
>    the LPC_CLK frequency when
>    LPC_DIV of SCFR register in clock block is set to 3?b001. See
>    section 6.4.1.4. Some parameters (ti_ds,
>    tco, tskew2, etc.) are a function of the MPC5121e and the
>    microcontroller top-level design controls them.
>    Characteristics of the transceiver or isolation buffer between the
>    MPC5121e and the external ATA device
>    control other parameters. Also, characteristics of the ATA cable
>    connecting the MPC5121e and the
>    external ATA device controls other parameters.
>    Most of the timing parameters controlling the various PATA bus
>    signals are programmed in increments of
>    the ATA bus clock period. A standard ATA bus clock frequency is 66
>    MHz, which has a period of 15 ns.
>
> I'm going to followup with the HW guys and see what the truth is. I 
> know my linux PATA driver uses the PATA bus clk for timing calculation 
> and it works fine.
>
> John
>
> Wolfgang Denk wrote:
>> From: Ralph Kondziella <rk@argos-messtechnik.de>
>>
>> (needed for PATA support)
>>
>> Signed-off-by: Ralph Kondziella <rk@argos-messtechnik.de>
>> Signed-off-by: Wolfgang Denk <wd@denx.de>
>> ---
>>  cpu/mpc512x/speed.c           |   13 ++++++++++++-
>>  include/asm-ppc/global_data.h |    1 +
>>  include/mpc512x.h             |    4 ++++
>>  3 files changed, 17 insertions(+), 1 deletions(-)
>>
>> diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c
>> index e62477b..24ec062 100644
>> --- a/cpu/mpc512x/speed.c
>> +++ b/cpu/mpc512x/speed.c
>> @@ -68,6 +68,7 @@ int get_clocks (void)
>>      u8 sys_div;
>>      u8 ips_div;
>>      u8 pci_div;
>> +    u8 lpc_div;
>>      u32 ref_clk = CFG_MPC512X_CLKIN;
>>      u32 spll;
>>      u32 sys_clk;
>> @@ -75,6 +76,7 @@ int get_clocks (void)
>>      u32 csb_clk;
>>      u32 ips_clk;
>>      u32 pci_clk;
>> +    u32 lpc_clk;
>>  
>>      if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
>>          return -1;
>> @@ -101,15 +103,23 @@ int get_clocks (void)
>>      if (pci_div != 0) {
>>          pci_clk = csb_clk / pci_div;
>>      } else {
>> -        /* in case we cannot get a sane IPS divisor, fail gracefully */
>> +        /* in case we cannot get a sane PCI divisor, fail gracefully */
>>          pci_clk = 333333;
>>      }
>> +    lpc_div = (im->clk.scfr[0] & SCFR1_LPC_DIV_MASK) >> 
>> SCFR1_LPC_DIV_SHIFT;
>> +    if (lpc_div != 0) {
>> +        lpc_clk = ips_clk / lpc_div;
>> +    } else {
>> +        /* in case we cannot get a sane LPC divisor, fail gracefully */
>> +        lpc_clk = 0;
>> +    }
>>  
>>      gd->ips_clk = ips_clk;
>>      gd->pci_clk = pci_clk;
>>      gd->csb_clk = csb_clk;
>>      gd->cpu_clk = core_clk;
>>      gd->bus_clk = csb_clk;
>> +    gd->lpc_clk = lpc_clk;
>>      return 0;
>>  
>>  }
>> @@ -130,6 +140,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int 
>> argc, char *argv[])
>>      printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
>>      printf("  IPS Bus:             %4d MHz\n", gd->ips_clk / 1000000);
>>      printf("  PCI:                 %4d MHz\n", gd->pci_clk / 1000000);
>> +    printf("  LPC:                 %4d MHz\n", gd->lpc_clk / 1000000);
>>      printf("  DDR:                 %4d MHz\n", 2 * gd->csb_clk / 
>> 1000000);
>>      return 0;
>>  }
>> diff --git a/include/asm-ppc/global_data.h 
>> b/include/asm-ppc/global_data.h
>> index 4331a15..d1d075f 100644
>> --- a/include/asm-ppc/global_data.h
>> +++ b/include/asm-ppc/global_data.h
>> @@ -110,6 +110,7 @@ typedef    struct    global_data {
>>      u32 ips_clk;
>>      u32 csb_clk;
>>      u32 pci_clk;
>> +    u32 lpc_clk;
>>  #endif /* CONFIG_MPC512X */
>>  #if defined(CONFIG_MPC8220)
>>      unsigned long   bExtUart;
>> diff --git a/include/mpc512x.h b/include/mpc512x.h
>> index cb418d1..1f808ca 100644
>> --- a/include/mpc512x.h
>> +++ b/include/mpc512x.h
>> @@ -191,6 +191,10 @@
>>  #define SCFR1_IPS_DIV_MASK        0x03800000
>>  #define SCFR1_IPS_DIV_SHIFT        23
>>  
>> +#define SCFR1_LPC_DIV            0x2
>> +#define SCFR1_LPC_DIV_MASK        0x00003800
>> +#define SCFR1_LPC_DIV_SHIFT        11
>> +
>>  #define SCFR1_PCI_DIV            0x6
>>  #define SCFR1_PCI_DIV_MASK        0x00700000
>>  #define SCFR1_PCI_DIV_SHIFT        20
>>   
>
>