* [U-Boot] [PATCH 01/12 v2] ARM: OMAP3: Add pin mux, clock and cpu headers
@ 2008-10-03 10:37 dirk.behme at googlemail.com
2008-10-03 10:37 ` [U-Boot] [PATCH 02/12 v2] ARM: OMAP3: Add i2c, memory and additional pin mux headers dirk.behme at googlemail.com
0 siblings, 1 reply; 6+ messages in thread
From: dirk.behme at googlemail.com @ 2008-10-03 10:37 UTC (permalink / raw)
To: u-boot
Subject: [PATCH 01/12 v2] ARM: OMAP3: Add pin mux, clock and cpu headers
From: Dirk Behme <dirk.behme@gmail.com>
Add pin mux, clock and cpu header files for OMAP3.
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
---
include/asm-arm/arch-omap3/bits.h | 48 +++
include/asm-arm/arch-omap3/clocks.h | 62 ++++
include/asm-arm/arch-omap3/clocks_omap3.h | 101 +++++++
include/asm-arm/arch-omap3/cpu.h | 250 ++++++++++++++++++
include/asm-arm/arch-omap3/mux.h | 407 ++++++++++++++++++++++++++++++
5 files changed, 868 insertions(+)
Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/mux.h
@@ -0,0 +1,407 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_H_
+#define _MUX_H_
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ */
+
+#define IEN (1 << 8)
+
+#define IDIS (0 << 8)
+#define PTU (1 << 4)
+#define PTD (0 << 4)
+#define EN (1 << 3)
+#define DIS (0 << 3)
+
+#define M0 0
+#define M1 1
+#define M2 2
+#define M3 3
+#define M4 4
+#define M5 5
+#define M6 6
+#define M7 7
+
+/*
+ * To get the actual address the offset has to added
+ * with OMAP34XX_CTRL_BASE to get the actual address
+ */
+
+ /*SDRC*/
+#define CONTROL_PADCONF_SDRC_D0 0x0030
+#define CONTROL_PADCONF_SDRC_D1 0x0032
+#define CONTROL_PADCONF_SDRC_D2 0x0034
+#define CONTROL_PADCONF_SDRC_D3 0x0036
+#define CONTROL_PADCONF_SDRC_D4 0x0038
+#define CONTROL_PADCONF_SDRC_D5 0x003A
+#define CONTROL_PADCONF_SDRC_D6 0x003C
+#define CONTROL_PADCONF_SDRC_D7 0x003E
+#define CONTROL_PADCONF_SDRC_D8 0x0040
+#define CONTROL_PADCONF_SDRC_D9 0x0042
+#define CONTROL_PADCONF_SDRC_D10 0x0044
+#define CONTROL_PADCONF_SDRC_D11 0x0046
+#define CONTROL_PADCONF_SDRC_D12 0x0048
+#define CONTROL_PADCONF_SDRC_D13 0x004A
+#define CONTROL_PADCONF_SDRC_D14 0x004C
+#define CONTROL_PADCONF_SDRC_D15 0x004E
+#define CONTROL_PADCONF_SDRC_D16 0x0050
+#define CONTROL_PADCONF_SDRC_D17 0x0052
+#define CONTROL_PADCONF_SDRC_D18 0x0054
+#define CONTROL_PADCONF_SDRC_D19 0x0056
+#define CONTROL_PADCONF_SDRC_D20 0x0058
+#define CONTROL_PADCONF_SDRC_D21 0x005A
+#define CONTROL_PADCONF_SDRC_D22 0x005C
+#define CONTROL_PADCONF_SDRC_D23 0x005E
+#define CONTROL_PADCONF_SDRC_D24 0x0060
+#define CONTROL_PADCONF_SDRC_D25 0x0062
+#define CONTROL_PADCONF_SDRC_D26 0x0064
+#define CONTROL_PADCONF_SDRC_D27 0x0066
+#define CONTROL_PADCONF_SDRC_D28 0x0068
+#define CONTROL_PADCONF_SDRC_D29 0x006A
+#define CONTROL_PADCONF_SDRC_D30 0x006C
+#define CONTROL_PADCONF_SDRC_D31 0x006E
+#define CONTROL_PADCONF_SDRC_CLK 0x0070
+#define CONTROL_PADCONF_SDRC_DQS0 0x0072
+#define CONTROL_PADCONF_SDRC_DQS1 0x0074
+#define CONTROL_PADCONF_SDRC_DQS2 0x0076
+#define CONTROL_PADCONF_SDRC_DQS3 0x0078
+ /*GPMC*/
+#define CONTROL_PADCONF_GPMC_A1 0x007A
+#define CONTROL_PADCONF_GPMC_A2 0x007C
+#define CONTROL_PADCONF_GPMC_A3 0x007E
+#define CONTROL_PADCONF_GPMC_A4 0x0080
+#define CONTROL_PADCONF_GPMC_A5 0x0082
+#define CONTROL_PADCONF_GPMC_A6 0x0084
+#define CONTROL_PADCONF_GPMC_A7 0x0086
+#define CONTROL_PADCONF_GPMC_A8 0x0088
+#define CONTROL_PADCONF_GPMC_A9 0x008A
+#define CONTROL_PADCONF_GPMC_A10 0x008C
+#define CONTROL_PADCONF_GPMC_D0 0x008E
+#define CONTROL_PADCONF_GPMC_D1 0x0090
+#define CONTROL_PADCONF_GPMC_D2 0x0092
+#define CONTROL_PADCONF_GPMC_D3 0x0094
+#define CONTROL_PADCONF_GPMC_D4 0x0096
+#define CONTROL_PADCONF_GPMC_D5 0x0098
+#define CONTROL_PADCONF_GPMC_D6 0x009A
+#define CONTROL_PADCONF_GPMC_D7 0x009C
+#define CONTROL_PADCONF_GPMC_D8 0x009E
+#define CONTROL_PADCONF_GPMC_D9 0x00A0
+#define CONTROL_PADCONF_GPMC_D10 0x00A2
+#define CONTROL_PADCONF_GPMC_D11 0x00A4
+#define CONTROL_PADCONF_GPMC_D12 0x00A6
+#define CONTROL_PADCONF_GPMC_D13 0x00A8
+#define CONTROL_PADCONF_GPMC_D14 0x00AA
+#define CONTROL_PADCONF_GPMC_D15 0x00AC
+#define CONTROL_PADCONF_GPMC_nCS0 0x00AE
+#define CONTROL_PADCONF_GPMC_nCS1 0x00B0
+#define CONTROL_PADCONF_GPMC_nCS2 0x00B2
+#define CONTROL_PADCONF_GPMC_nCS3 0x00B4
+#define CONTROL_PADCONF_GPMC_nCS4 0x00B6
+#define CONTROL_PADCONF_GPMC_nCS5 0x00B8
+#define CONTROL_PADCONF_GPMC_nCS6 0x00BA
+#define CONTROL_PADCONF_GPMC_nCS7 0x00BC
+#define CONTROL_PADCONF_GPMC_CLK 0x00BE
+#define CONTROL_PADCONF_GPMC_nADV_ALE 0x00C0
+#define CONTROL_PADCONF_GPMC_nOE 0x00C2
+#define CONTROL_PADCONF_GPMC_nWE 0x00C4
+#define CONTROL_PADCONF_GPMC_nBE0_CLE 0x00C6
+#define CONTROL_PADCONF_GPMC_nBE1 0x00C8
+#define CONTROL_PADCONF_GPMC_nWP 0x00CA
+#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC
+#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE
+#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0
+#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2
+ /*DSS*/
+#define CONTROL_PADCONF_DSS_PCLK 0x00D4
+#define CONTROL_PADCONF_DSS_HSYNC 0x00D6
+#define CONTROL_PADCONF_DSS_VSYNC 0x00D8
+#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA
+#define CONTROL_PADCONF_DSS_DATA0 0x00DC
+#define CONTROL_PADCONF_DSS_DATA1 0x00DE
+#define CONTROL_PADCONF_DSS_DATA2 0x00E0
+#define CONTROL_PADCONF_DSS_DATA3 0x00E2
+#define CONTROL_PADCONF_DSS_DATA4 0x00E4
+#define CONTROL_PADCONF_DSS_DATA5 0x00E6
+#define CONTROL_PADCONF_DSS_DATA6 0x00E8
+#define CONTROL_PADCONF_DSS_DATA7 0x00EA
+#define CONTROL_PADCONF_DSS_DATA8 0x00EC
+#define CONTROL_PADCONF_DSS_DATA9 0x00EE
+#define CONTROL_PADCONF_DSS_DATA10 0x00F0
+#define CONTROL_PADCONF_DSS_DATA11 0x00F2
+#define CONTROL_PADCONF_DSS_DATA12 0x00F4
+#define CONTROL_PADCONF_DSS_DATA13 0x00F6
+#define CONTROL_PADCONF_DSS_DATA14 0x00F8
+#define CONTROL_PADCONF_DSS_DATA15 0x00FA
+#define CONTROL_PADCONF_DSS_DATA16 0x00FC
+#define CONTROL_PADCONF_DSS_DATA17 0x00FE
+#define CONTROL_PADCONF_DSS_DATA18 0x0100
+#define CONTROL_PADCONF_DSS_DATA19 0x0102
+#define CONTROL_PADCONF_DSS_DATA20 0x0104
+#define CONTROL_PADCONF_DSS_DATA21 0x0106
+#define CONTROL_PADCONF_DSS_DATA22 0x0108
+#define CONTROL_PADCONF_DSS_DATA23 0x010A
+ /*CAMERA*/
+#define CONTROL_PADCONF_CAM_HS 0x010C
+#define CONTROL_PADCONF_CAM_VS 0x010E
+#define CONTROL_PADCONF_CAM_XCLKA 0x0110
+#define CONTROL_PADCONF_CAM_PCLK 0x0112
+#define CONTROL_PADCONF_CAM_FLD 0x0114
+#define CONTROL_PADCONF_CAM_D0 0x0116
+#define CONTROL_PADCONF_CAM_D1 0x0118
+#define CONTROL_PADCONF_CAM_D2 0x011A
+#define CONTROL_PADCONF_CAM_D3 0x011C
+#define CONTROL_PADCONF_CAM_D4 0x011E
+#define CONTROL_PADCONF_CAM_D5 0x0120
+#define CONTROL_PADCONF_CAM_D6 0x0122
+#define CONTROL_PADCONF_CAM_D7 0x0124
+#define CONTROL_PADCONF_CAM_D8 0x0126
+#define CONTROL_PADCONF_CAM_D9 0x0128
+#define CONTROL_PADCONF_CAM_D10 0x012A
+#define CONTROL_PADCONF_CAM_D11 0x012C
+#define CONTROL_PADCONF_CAM_XCLKB 0x012E
+#define CONTROL_PADCONF_CAM_WEN 0x0130
+#define CONTROL_PADCONF_CAM_STROBE 0x0132
+#define CONTROL_PADCONF_CSI2_DX0 0x0134
+#define CONTROL_PADCONF_CSI2_DY0 0x0136
+#define CONTROL_PADCONF_CSI2_DX1 0x0138
+#define CONTROL_PADCONF_CSI2_DY1 0x013A
+/*Audio Interface */
+#define CONTROL_PADCONF_McBSP2_FSX 0x013C
+#define CONTROL_PADCONF_McBSP2_CLKX 0x013E
+#define CONTROL_PADCONF_McBSP2_DR 0x0140
+#define CONTROL_PADCONF_McBSP2_DX 0x0142
+#define CONTROL_PADCONF_MMC1_CLK 0x0144
+#define CONTROL_PADCONF_MMC1_CMD 0x0146
+#define CONTROL_PADCONF_MMC1_DAT0 0x0148
+#define CONTROL_PADCONF_MMC1_DAT1 0x014A
+#define CONTROL_PADCONF_MMC1_DAT2 0x014C
+#define CONTROL_PADCONF_MMC1_DAT3 0x014E
+#define CONTROL_PADCONF_MMC1_DAT4 0x0150
+#define CONTROL_PADCONF_MMC1_DAT5 0x0152
+#define CONTROL_PADCONF_MMC1_DAT6 0x0154
+#define CONTROL_PADCONF_MMC1_DAT7 0x0156
+/*Wireless LAN */
+#define CONTROL_PADCONF_MMC2_CLK 0x0158
+#define CONTROL_PADCONF_MMC2_CMD 0x015A
+#define CONTROL_PADCONF_MMC2_DAT0 0x015C
+#define CONTROL_PADCONF_MMC2_DAT1 0x015E
+#define CONTROL_PADCONF_MMC2_DAT2 0x0160
+#define CONTROL_PADCONF_MMC2_DAT3 0x0162
+#define CONTROL_PADCONF_MMC2_DAT4 0x0164
+#define CONTROL_PADCONF_MMC2_DAT5 0x0166
+#define CONTROL_PADCONF_MMC2_DAT6 0x0168
+#define CONTROL_PADCONF_MMC2_DAT7 0x016A
+/*Bluetooth*/
+#define CONTROL_PADCONF_McBSP3_DX 0x016C
+#define CONTROL_PADCONF_McBSP3_DR 0x016E
+#define CONTROL_PADCONF_McBSP3_CLKX 0x0170
+#define CONTROL_PADCONF_McBSP3_FSX 0x0172
+#define CONTROL_PADCONF_UART2_CTS 0x0174
+#define CONTROL_PADCONF_UART2_RTS 0x0176
+#define CONTROL_PADCONF_UART2_TX 0x0178
+#define CONTROL_PADCONF_UART2_RX 0x017A
+/*Modem Interface */
+#define CONTROL_PADCONF_UART1_TX 0x017C
+#define CONTROL_PADCONF_UART1_RTS 0x017E
+#define CONTROL_PADCONF_UART1_CTS 0x0180
+#define CONTROL_PADCONF_UART1_RX 0x0182
+#define CONTROL_PADCONF_McBSP4_CLKX 0x0184
+#define CONTROL_PADCONF_McBSP4_DR 0x0186
+#define CONTROL_PADCONF_McBSP4_DX 0x0188
+#define CONTROL_PADCONF_McBSP4_FSX 0x018A
+#define CONTROL_PADCONF_McBSP1_CLKR 0x018C
+#define CONTROL_PADCONF_McBSP1_FSR 0x018E
+#define CONTROL_PADCONF_McBSP1_DX 0x0190
+#define CONTROL_PADCONF_McBSP1_DR 0x0192
+#define CONTROL_PADCONF_McBSP_CLKS 0x0194
+#define CONTROL_PADCONF_McBSP1_FSX 0x0196
+#define CONTROL_PADCONF_McBSP1_CLKX 0x0198
+/*Serial Interface*/
+#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A
+#define CONTROL_PADCONF_UART3_RTS_SD 0x019C
+#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E
+#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0
+#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2
+#define CONTROL_PADCONF_HSUSB0_STP 0x01A4
+#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6
+#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8
+#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA
+#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC
+#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE
+#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0
+#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2
+#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4
+#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6
+#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8
+#define CONTROL_PADCONF_I2C1_SCL 0x01BA
+#define CONTROL_PADCONF_I2C1_SDA 0x01BC
+#define CONTROL_PADCONF_I2C2_SCL 0x01BE
+#define CONTROL_PADCONF_I2C2_SDA 0x01C0
+#define CONTROL_PADCONF_I2C3_SCL 0x01C2
+#define CONTROL_PADCONF_I2C3_SDA 0x01C4
+#define CONTROL_PADCONF_I2C4_SCL 0x0A00
+#define CONTROL_PADCONF_I2C4_SDA 0x0A02
+#define CONTROL_PADCONF_HDQ_SIO 0x01C6
+#define CONTROL_PADCONF_McSPI1_CLK 0x01C8
+#define CONTROL_PADCONF_McSPI1_SIMO 0x01CA
+#define CONTROL_PADCONF_McSPI1_SOMI 0x01CC
+#define CONTROL_PADCONF_McSPI1_CS0 0x01CE
+#define CONTROL_PADCONF_McSPI1_CS1 0x01D0
+#define CONTROL_PADCONF_McSPI1_CS2 0x01D2
+#define CONTROL_PADCONF_McSPI1_CS3 0x01D4
+#define CONTROL_PADCONF_McSPI2_CLK 0x01D6
+#define CONTROL_PADCONF_McSPI2_SIMO 0x01D8
+#define CONTROL_PADCONF_McSPI2_SOMI 0x01DA
+#define CONTROL_PADCONF_McSPI2_CS0 0x01DC
+#define CONTROL_PADCONF_McSPI2_CS1 0x01DE
+/*Control and debug */
+#define CONTROL_PADCONF_SYS_32K 0x0A04
+#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06
+#define CONTROL_PADCONF_SYS_nIRQ 0x01E0
+#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A
+#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C
+#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E
+#define CONTROL_PADCONF_SYS_BOOT3 0x0A10
+#define CONTROL_PADCONF_SYS_BOOT4 0x0A12
+#define CONTROL_PADCONF_SYS_BOOT5 0x0A14
+#define CONTROL_PADCONF_SYS_BOOT6 0x0A16
+#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
+#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
+#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
+#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C
+#define CONTROL_PADCONF_JTAG_TCK 0x0A1E
+#define CONTROL_PADCONF_JTAG_TMS 0x0A20
+#define CONTROL_PADCONF_JTAG_TDI 0x0A22
+#define CONTROL_PADCONF_JTAG_EMU0 0x0A24
+#define CONTROL_PADCONF_JTAG_EMU1 0x0A26
+#define CONTROL_PADCONF_ETK_CLK 0x0A28
+#define CONTROL_PADCONF_ETK_CTL 0x0A2A
+#define CONTROL_PADCONF_ETK_D0 0x0A2C
+#define CONTROL_PADCONF_ETK_D1 0x0A2E
+#define CONTROL_PADCONF_ETK_D2 0x0A30
+#define CONTROL_PADCONF_ETK_D3 0x0A32
+#define CONTROL_PADCONF_ETK_D4 0x0A34
+#define CONTROL_PADCONF_ETK_D5 0x0A36
+#define CONTROL_PADCONF_ETK_D6 0x0A38
+#define CONTROL_PADCONF_ETK_D7 0x0A3A
+#define CONTROL_PADCONF_ETK_D8 0x0A3C
+#define CONTROL_PADCONF_ETK_D9 0x0A3E
+#define CONTROL_PADCONF_ETK_D10 0x0A40
+#define CONTROL_PADCONF_ETK_D11 0x0A42
+#define CONTROL_PADCONF_ETK_D12 0x0A44
+#define CONTROL_PADCONF_ETK_D13 0x0A46
+#define CONTROL_PADCONF_ETK_D14 0x0A48
+#define CONTROL_PADCONF_ETK_D15 0x0A4A
+#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8
+#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA
+#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC
+#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE
+#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0
+#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2
+#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4
+#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6
+#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8
+#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA
+#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC
+#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE
+#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0
+#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2
+#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4
+#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
+#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
+#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
+/*Die to Die */
+#define CONTROL_PADCONF_d2d_mcad0 0x01E4
+#define CONTROL_PADCONF_d2d_mcad1 0x01E6
+#define CONTROL_PADCONF_d2d_mcad2 0x01E8
+#define CONTROL_PADCONF_d2d_mcad3 0x01EA
+#define CONTROL_PADCONF_d2d_mcad4 0x01EC
+#define CONTROL_PADCONF_d2d_mcad5 0x01EE
+#define CONTROL_PADCONF_d2d_mcad6 0x01F0
+#define CONTROL_PADCONF_d2d_mcad7 0x01F2
+#define CONTROL_PADCONF_d2d_mcad8 0x01F4
+#define CONTROL_PADCONF_d2d_mcad9 0x01F6
+#define CONTROL_PADCONF_d2d_mcad10 0x01F8
+#define CONTROL_PADCONF_d2d_mcad11 0x01FA
+#define CONTROL_PADCONF_d2d_mcad12 0x01FC
+#define CONTROL_PADCONF_d2d_mcad13 0x01FE
+#define CONTROL_PADCONF_d2d_mcad14 0x0200
+#define CONTROL_PADCONF_d2d_mcad15 0x0202
+#define CONTROL_PADCONF_d2d_mcad16 0x0204
+#define CONTROL_PADCONF_d2d_mcad17 0x0206
+#define CONTROL_PADCONF_d2d_mcad18 0x0208
+#define CONTROL_PADCONF_d2d_mcad19 0x020A
+#define CONTROL_PADCONF_d2d_mcad20 0x020C
+#define CONTROL_PADCONF_d2d_mcad21 0x020E
+#define CONTROL_PADCONF_d2d_mcad22 0x0210
+#define CONTROL_PADCONF_d2d_mcad23 0x0212
+#define CONTROL_PADCONF_d2d_mcad24 0x0214
+#define CONTROL_PADCONF_d2d_mcad25 0x0216
+#define CONTROL_PADCONF_d2d_mcad26 0x0218
+#define CONTROL_PADCONF_d2d_mcad27 0x021A
+#define CONTROL_PADCONF_d2d_mcad28 0x021C
+#define CONTROL_PADCONF_d2d_mcad29 0x021E
+#define CONTROL_PADCONF_d2d_mcad30 0x0220
+#define CONTROL_PADCONF_d2d_mcad31 0x0222
+#define CONTROL_PADCONF_d2d_mcad32 0x0224
+#define CONTROL_PADCONF_d2d_mcad33 0x0226
+#define CONTROL_PADCONF_d2d_mcad34 0x0228
+#define CONTROL_PADCONF_d2d_mcad35 0x022A
+#define CONTROL_PADCONF_d2d_mcad36 0x022C
+#define CONTROL_PADCONF_d2d_clk26mi 0x022E
+#define CONTROL_PADCONF_d2d_nrespwron 0x0230
+#define CONTROL_PADCONF_d2d_nreswarm 0x0232
+#define CONTROL_PADCONF_d2d_arm9nirq 0x0234
+#define CONTROL_PADCONF_d2d_uma2p6fiq 0x0236
+#define CONTROL_PADCONF_d2d_spint 0x0238
+#define CONTROL_PADCONF_d2d_frint 0x023A
+#define CONTROL_PADCONF_d2d_dmareq0 0x023C
+#define CONTROL_PADCONF_d2d_dmareq1 0x023E
+#define CONTROL_PADCONF_d2d_dmareq2 0x0240
+#define CONTROL_PADCONF_d2d_dmareq3 0x0242
+#define CONTROL_PADCONF_d2d_n3gtrst 0x0244
+#define CONTROL_PADCONF_d2d_n3gtdi 0x0246
+#define CONTROL_PADCONF_d2d_n3gtdo 0x0248
+#define CONTROL_PADCONF_d2d_n3gtms 0x024A
+#define CONTROL_PADCONF_d2d_n3gtck 0x024C
+#define CONTROL_PADCONF_d2d_n3grtck 0x024E
+#define CONTROL_PADCONF_d2d_mstdby 0x0250
+#define CONTROL_PADCONF_d2d_swakeup 0x0A4C
+#define CONTROL_PADCONF_d2d_idlereq 0x0252
+#define CONTROL_PADCONF_d2d_idleack 0x0254
+#define CONTROL_PADCONF_d2d_mwrite 0x0256
+#define CONTROL_PADCONF_d2d_swrite 0x0258
+#define CONTROL_PADCONF_d2d_mread 0x025A
+#define CONTROL_PADCONF_d2d_sread 0x025C
+#define CONTROL_PADCONF_d2d_mbusflag 0x025E
+#define CONTROL_PADCONF_d2d_sbusflag 0x0260
+#define CONTROL_PADCONF_sdrc_cke0 0x0262
+#define CONTROL_PADCONF_sdrc_cke1 0x0264
+
+#endif
Index: u-boot-arm/include/asm-arm/arch-omap3/bits.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/bits.h
@@ -0,0 +1,48 @@
+/* bits.h
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * This package is free software; you can redistribute it and/or
+ * modify it under the terms of the license found in the file
+ * named COPYING that should have accompanied this file.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef __bits_h
+#define __bits_h 1
+
+#define BIT0 (1<<0)
+#define BIT1 (1<<1)
+#define BIT2 (1<<2)
+#define BIT3 (1<<3)
+#define BIT4 (1<<4)
+#define BIT5 (1<<5)
+#define BIT6 (1<<6)
+#define BIT7 (1<<7)
+#define BIT8 (1<<8)
+#define BIT9 (1<<9)
+#define BIT10 (1<<10)
+#define BIT11 (1<<11)
+#define BIT12 (1<<12)
+#define BIT13 (1<<13)
+#define BIT14 (1<<14)
+#define BIT15 (1<<15)
+#define BIT16 (1<<16)
+#define BIT17 (1<<17)
+#define BIT18 (1<<18)
+#define BIT19 (1<<19)
+#define BIT20 (1<<20)
+#define BIT21 (1<<21)
+#define BIT22 (1<<22)
+#define BIT23 (1<<23)
+#define BIT24 (1<<24)
+#define BIT25 (1<<25)
+#define BIT26 (1<<26)
+#define BIT27 (1<<27)
+#define BIT28 (1<<28)
+#define BIT29 (1<<29)
+#define BIT30 (1<<30)
+#define BIT31 (1<<31)
+
+#endif
Index: u-boot-arm/include/asm-arm/arch-omap3/clocks.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/clocks.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_H_
+#define _CLOCKS_H_
+
+#define LDELAY 12000000
+
+#define S12M 12000000
+#define S13M 13000000
+#define S19_2M 19200000
+#define S24M 24000000
+#define S26M 26000000
+#define S38_4M 38400000
+
+#define FCK_IVA2_ON 0x00000001
+#define FCK_CORE1_ON 0x03fffe29
+#define ICK_CORE1_ON 0x3ffffffb
+#define ICK_CORE2_ON 0x0000001f
+#define FCK_WKUP_ON 0x000000e9
+#define ICK_WKUP_ON 0x0000003f
+#define FCK_DSS_ON 0x00000005
+#define ICK_DSS_ON 0x00000001
+#define FCK_CAM_ON 0x00000001
+#define ICK_CAM_ON 0x00000001
+#define FCK_PER_ON 0x0003ffff
+#define ICK_PER_ON 0x0003ffff
+
+/* Used to index into DPLL parameter tables */
+typedef struct {
+ unsigned int m;
+ unsigned int n;
+ unsigned int fsel;
+ unsigned int m2;
+} dpll_param;
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param *get_mpu_dpll_param(void);
+extern dpll_param *get_iva_dpll_param(void);
+extern dpll_param *get_core_dpll_param(void);
+extern dpll_param *get_per_dpll_param(void);
+
+extern void *_end_vect, *_start;
+
+#endif
Index: u-boot-arm/include/asm-arm/arch-omap3/clocks_omap3.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/clocks_omap3.h
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP3_H_
+#define _CLOCKS_OMAP3_H_
+
+#define PLL_STOP 1 /* PER & IVA */
+#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
+#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
+#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
+
+/* The following configurations are OPP and SysClk value independant
+ * and hence are defined here. All the other DPLL related values are
+ * tabulated in lowlevel_init.S.
+ */
+
+/* CORE DPLL */
+# define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
+# define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
+# define CORE_FUSB_DIV 2 /* 41.5MHz: */
+# define CORE_L4_DIV 2 /* 83MHz : L4 */
+# define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
+# define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
+# define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
+
+/* PER DPLL */
+# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
+# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
+# define PER_M4X2 2 /* 432MHz : CM_CLKSEL_DSS-dss1 */
+# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
+
+# define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50))
+
+# define M_12 0xA6
+# define N_12 0x05
+# define FSEL_12 0x07
+# define M2_12 0x01 /* M3 of 2 */
+
+# define M_12_ES1 0x19F
+# define N_12_ES1 0x0E
+# define FSL_12_ES1 0x03
+# define M2_12_ES1 0x1 /* M3 of 2 */
+
+# define M_13 0x14C
+# define N_13 0x0C
+# define FSEL_13 0x03
+# define M2_13 0x01 /* M3 of 2 */
+
+# define M_13_ES1 0x1B2
+# define N_13_ES1 0x10
+# define FSL_13_ES1 0x03
+# define M2_13_ES1 0x01 /* M3 of 2 */
+
+# define M_19p2 0x19F
+# define N_19p2 0x17
+# define FSEL_19p2 0x03
+# define M2_19p2 0x01 /* M3 of 2 */
+
+# define M_19p2_ES1 0x19F
+# define N_19p2_ES1 0x17
+# define FSL_19p2_ES1 0x03
+# define M2_19p2_ES1 0x01 /* M3 of 2 */
+
+# define M_26 0xA6
+# define N_26 0x0C
+# define FSEL_26 0x07
+# define M2_26 0x01 /* M3 of 2 */
+
+# define M_26_ES1 0x1B2
+# define N_26_ES1 0x21
+# define FSL_26_ES1 0x03
+# define M2_26_ES1 0x01 /* M3 of 2 */
+
+# define M_38p4 0x19F
+# define N_38p4 0x2F
+# define FSEL_38p4 0x03
+# define M2_38p4 0x01 /* M3 of 2 */
+
+# define M_38p4_ES1 0x19F
+# define N_38p4_ES1 0x2F
+# define FSL_38p4_ES1 0x03
+# define M2_38p4_ES1 0x01 /* M3 of 2 */
+
+#endif /* endif _CLOCKS_OMAP3_H_ */
Index: u-boot-arm/include/asm-arm/arch-omap3/cpu.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/cpu.h
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+/* Register offsets of common modules */
+/* Control */
+#define CONTROL_STATUS (OMAP34XX_CTRL_BASE + 0x2F0)
+#define OMAP34XX_MCR (OMAP34XX_CTRL_BASE + 0x8C)
+#define CONTROL_SCALABLE_OMAP_STATUS (OMAP34XX_CTRL_BASE + 0x44C)
+#define CONTROL_SCALABLE_OMAP_OCP (OMAP34XX_CTRL_BASE + 0x534)
+
+/* Tap Information */
+#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE+0x204)
+#define PRODUCTION_ID (OMAP34XX_TAP_BASE+0x208)
+
+/* device type */
+#define DEVICE_MASK (BIT8|BIT9|BIT10)
+#define TST_DEVICE 0x0
+#define EMU_DEVICE 0x1
+#define HS_DEVICE 0x2
+#define GP_DEVICE 0x3
+
+/* GPMC CS3/cs4/cs6 not avaliable */
+#define GPMC_BASE (OMAP34XX_GPMC_BASE)
+#define GPMC_SYSCONFIG (OMAP34XX_GPMC_BASE+0x10)
+#define GPMC_IRQSTATUS (OMAP34XX_GPMC_BASE+0x18)
+#define GPMC_IRQENABLE (OMAP34XX_GPMC_BASE+0x1C)
+#define GPMC_TIMEOUT_CONTROL (OMAP34XX_GPMC_BASE+0x40)
+#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50)
+#define GPMC_STATUS (OMAP34XX_GPMC_BASE+0x54)
+
+#define GPMC_CONFIG_CS0 (OMAP34XX_GPMC_BASE+0x60)
+#define GPMC_CONFIG_WIDTH (0x30)
+
+#define GPMC_CONFIG1 (0x00)
+#define GPMC_CONFIG2 (0x04)
+#define GPMC_CONFIG3 (0x08)
+#define GPMC_CONFIG4 (0x0C)
+#define GPMC_CONFIG5 (0x10)
+#define GPMC_CONFIG6 (0x14)
+#define GPMC_CONFIG7 (0x18)
+#define GPMC_NAND_CMD (0x1C)
+#define GPMC_NAND_ADR (0x20)
+#define GPMC_NAND_DAT (0x24)
+
+#define GPMC_ECC_CONFIG (0x1F4)
+#define GPMC_ECC_CONTROL (0x1F8)
+#define GPMC_ECC_SIZE_CONFIG (0x1FC)
+#define GPMC_ECC1_RESULT (0x200)
+#define GPMC_ECC2_RESULT (0x204)
+#define GPMC_ECC3_RESULT (0x208)
+#define GPMC_ECC4_RESULT (0x20C)
+#define GPMC_ECC5_RESULT (0x210)
+#define GPMC_ECC6_RESULT (0x214)
+#define GPMC_ECC7_RESULT (0x218)
+#define GPMC_ECC8_RESULT (0x21C)
+#define GPMC_ECC9_RESULT (0x220)
+
+/* GPMC Mapping */
+# define FLASH_BASE 0x10000000 /* NOR flash, */
+ /* aligned to 256 Meg */
+# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
+ /* aligned to 64 Meg */
+# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
+ /* aligned to 256 Meg */
+# define DEBUG_BASE 0x08000000 /* debug board */
+# define NAND_BASE 0x30000000 /* NAND addr */
+ /* (actual size small port) */
+# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
+# define ONENAND_MAP 0x20000000 /* OneNand addr */
+ /* (actual size small port) */
+
+/* SMS */
+#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10)
+#define SMS_RG_ATT0 (OMAP34XX_SMS_BASE+0x48)
+#define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE+0xD0)
+#define BURSTCOMPLETE_GROUP7 BIT31
+
+/* SDRC */
+#define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE+0x10)
+#define SDRC_STATUS (OMAP34XX_SDRC_BASE+0x14)
+#define SDRC_CS_CFG (OMAP34XX_SDRC_BASE+0x40)
+#define SDRC_SHARING (OMAP34XX_SDRC_BASE+0x44)
+#define SDRC_DLLA_CTRL (OMAP34XX_SDRC_BASE+0x60)
+#define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE+0x64)
+#define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE+0x68)
+#define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE+0x6C)
+#define DLLPHASE BIT1
+#define LOADDLL BIT2
+#define DLL_DELAY_MASK 0xFF00
+#define DLL_NO_FILTER_MASK (BIT8|BIT9)
+
+#define SDRC_POWER (OMAP34XX_SDRC_BASE+0x70)
+#define WAKEUPPROC BIT26
+
+#define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE+0x80)
+#define SDRC_MR_0 (OMAP34XX_SDRC_BASE+0x84)
+#define SDRC_ACTIM_CTRLA_0 (OMAP34XX_SDRC_BASE+0x9C)
+#define SDRC_ACTIM_CTRLB_0 (OMAP34XX_SDRC_BASE+0xA0)
+#define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE+0xC4)
+#define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE+0xC8)
+#define SDRC_RFR_CTRL (OMAP34XX_SDRC_BASE+0xA4)
+#define SDRC_RFR_CTRL (OMAP34XX_SDRC_BASE+0xA4)
+#define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE+0xA8)
+#define OMAP34XX_SDRC_CS0 0x80000000
+#define OMAP34XX_SDRC_CS1 0xA0000000
+#define CMD_NOP 0x0
+#define CMD_PRECHARGE 0x1
+#define CMD_AUTOREFRESH 0x2
+#define CMD_ENTR_PWRDOWN 0x3
+#define CMD_EXIT_PWRDOWN 0x4
+#define CMD_ENTR_SRFRSH 0x5
+#define CMD_CKE_HIGH 0x6
+#define CMD_CKE_LOW 0x7
+#define SOFTRESET BIT1
+#define SMART_IDLE (0x2 << 3)
+#define REF_ON_IDLE (0x1 << 6)
+
+/* timer regs offsets (32 bit regs) */
+#define TIDR 0x0 /* r */
+#define TIOCP_CFG 0x10 /* rw */
+#define TISTAT 0x14 /* r */
+#define TISR 0x18 /* rw */
+#define TIER 0x1C /* rw */
+#define TWER 0x20 /* rw */
+#define TCLR 0x24 /* rw */
+#define TCRR 0x28 /* rw */
+#define TLDR 0x2C /* rw */
+#define TTGR 0x30 /* rw */
+#define TWPS 0x34 /* r */
+#define TMAR 0x38 /* rw */
+#define TCAR1 0x3c /* r */
+#define TSICR 0x40 /* rw */
+#define TCAR2 0x44 /* r */
+ /* enable sys_clk NO-prescale /1 */
+#define GPT_EN ((0<<2)|BIT1|BIT0)
+
+/* Watchdog */
+#define WWPS 0x34 /* r */
+#define WSPR 0x48 /* rw */
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+/* PRCM */
+#define CM_FCLKEN_IVA2 0x48004000
+#define CM_CLKEN_PLL_IVA2 0x48004004
+#define CM_IDLEST_PLL_IVA2 0x48004024
+#define CM_CLKSEL1_PLL_IVA2 0x48004040
+#define CM_CLKSEL2_PLL_IVA2 0x48004044
+#define CM_CLKEN_PLL_MPU 0x48004904
+#define CM_IDLEST_PLL_MPU 0x48004924
+#define CM_CLKSEL1_PLL_MPU 0x48004940
+#define CM_CLKSEL2_PLL_MPU 0x48004944
+#define CM_FCLKEN1_CORE 0x48004a00
+#define CM_ICLKEN1_CORE 0x48004a10
+#define CM_ICLKEN2_CORE 0x48004a14
+#define CM_CLKSEL_CORE 0x48004a40
+#define CM_FCLKEN_GFX 0x48004b00
+#define CM_ICLKEN_GFX 0x48004b10
+#define CM_CLKSEL_GFX 0x48004b40
+#define CM_FCLKEN_WKUP 0x48004c00
+#define CM_ICLKEN_WKUP 0x48004c10
+#define CM_CLKSEL_WKUP 0x48004c40
+#define CM_IDLEST_WKUP 0x48004c20
+#define CM_CLKEN_PLL 0x48004d00
+#define CM_IDLEST_CKGEN 0x48004d20
+#define CM_CLKSEL1_PLL 0x48004d40
+#define CM_CLKSEL2_PLL 0x48004d44
+#define CM_CLKSEL3_PLL 0x48004d48
+#define CM_FCLKEN_DSS 0x48004e00
+#define CM_ICLKEN_DSS 0x48004e10
+#define CM_CLKSEL_DSS 0x48004e40
+#define CM_FCLKEN_CAM 0x48004f00
+#define CM_ICLKEN_CAM 0x48004f10
+#define CM_CLKSEL_CAM 0x48004F40
+#define CM_FCLKEN_PER 0x48005000
+#define CM_ICLKEN_PER 0x48005010
+#define CM_CLKSEL_PER 0x48005040
+#define CM_CLKSEL1_EMU 0x48005140
+
+#define PRM_CLKSEL 0x48306d40
+#define PRM_RSTCTRL 0x48307250
+#define PRM_CLKSRC_CTRL 0x48307270
+
+/* SMX-APE */
+#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
+#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
+#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
+#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00)
+#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
+
+#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68)
+#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50)
+#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58)
+#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60)
+
+#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48)
+#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50)
+#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58)
+
+#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48)
+#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50)
+#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58)
+#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80)
+
+#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48)
+#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50)
+#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58)
+
+#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68)
+#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70)
+#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78)
+
+#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88)
+#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90)
+#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98)
+
+#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8)
+#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0)
+#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8)
+
+/* I2C base */
+#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
+#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
+#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
+
+#endif /* _CPU_H */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 02/12 v2] ARM: OMAP3: Add i2c, memory and additional pin mux headers
@ 2008-10-03 10:37 ` dirk.behme at googlemail.com
2008-10-03 10:38 ` [U-Boot] [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers dirk.behme at googlemail.com
2008-10-05 1:18 ` [U-Boot] [PATCH 02/12 v2] ARM: OMAP3: Add i2c, memory and additional pin mux headers Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 2 replies; 6+ messages in thread
From: dirk.behme at googlemail.com @ 2008-10-03 10:37 UTC (permalink / raw)
To: u-boot
Subject: [PATCH 02/12 v2] ARM: OMAP3: Add i2c, memory and additional pin mux headers
From: Dirk Behme <dirk.behme@gmail.com>
Add OMAP3 I2C, memory and additional pin mux headers
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
---
include/asm-arm/arch-omap3/i2c.h | 128 ++++++++++++++
include/asm-arm/arch-omap3/mem.h | 220 ++++++++++++++++++++++++
include/asm-arm/arch-omap3/mux.h | 350 +++++++++++++++++++++++++++++++++++++++
3 files changed, 698 insertions(+)
Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h
===================================================================
--- u-boot-arm.orig/include/asm-arm/arch-omap3/mux.h
+++ u-boot-arm/include/asm-arm/arch-omap3/mux.h
@@ -404,4 +404,354 @@
#define CONTROL_PADCONF_sdrc_cke0 0x0262
#define CONTROL_PADCONF_sdrc_cke1 0x0264
+#define MUX_VAL(OFFSET,VALUE)\
+ __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+
+#define CP(x) (CONTROL_PADCONF_##x)
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT_ES2() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
+ /* For Beagle Rev 2 boards*/\
+ MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1))\
+ MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1))\
+ MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0))\
+ /* till here */ \
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ /* - CAM_RESET*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(McBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(McBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(McBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
+ MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
+ MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
+ MUX_VAL(CP(McBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
+ MUX_VAL(CP(McBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(McBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
+ /* - BT_WAKEUP*/\
+ MUX_VAL(CP(McBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(McBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(McBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(McBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_*/\
+ /* RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
+ MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
+ MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
+ MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
+ MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ /* - NOR_DPD*/\
+ MUX_VAL(CP(McSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\
+ MUX_VAL(CP(McSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(McSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(McSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(McSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(McSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ /* - PEN_IRQ */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
+ /* - MMC1_WP */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ /* - LCD_ENVDD*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ /* - LAN_INTR0*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ /* - MMC2_WP*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+ /* - LCD_ENBKL*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D15), (IEN | PTU | EN | M4)) /*GPIO_29*/\
+ MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(d2d_nrespwron), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(d2d_uma2p6fiq), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+
#endif
Index: u-boot-arm/include/asm-arm/arch-omap3/i2c.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/i2c.h
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _I2C_H_
+#define _I2C_H_
+
+#define I2C_DEFAULT_BASE I2C_BASE1
+
+#define I2C_REV (I2C_DEFAULT_BASE + 0x00)
+#define I2C_IE (I2C_DEFAULT_BASE + 0x04)
+#define I2C_STAT (I2C_DEFAULT_BASE + 0x08)
+#define I2C_IV (I2C_DEFAULT_BASE + 0x0c)
+#define I2C_BUF (I2C_DEFAULT_BASE + 0x14)
+#define I2C_CNT (I2C_DEFAULT_BASE + 0x18)
+#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c)
+#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20)
+#define I2C_CON (I2C_DEFAULT_BASE + 0x24)
+#define I2C_OA (I2C_DEFAULT_BASE + 0x28)
+#define I2C_SA (I2C_DEFAULT_BASE + 0x2c)
+#define I2C_PSC (I2C_DEFAULT_BASE + 0x30)
+#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34)
+#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38)
+#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c)
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE (1 << 5)
+#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD (1 << 15) /* Single byte data */
+#define I2C_STAT_BB (1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS (1 << 9) /* Address as slave */
+#define I2C_STAT_GC (1 << 5)
+#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
+#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
+#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
+#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK 7
+#define I2C_INTCODE_NONE 0
+#define I2C_INTCODE_AL 1 /* Arbitration lost */
+#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY 3 /* Register access ready */
+#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
+#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
+#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN (1 << 15) /* I2C module enable */
+#define I2C_CON_BE (1 << 14) /* Big endian mode */
+#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
+#define I2C_CON_MST (1 << 10) /* Master/slave mode */
+#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
+ /* (master mode only) */
+#define I2C_CON_XA (1 << 8) /* Expand address */
+#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
+#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
+#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
+#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
+#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
+
+#define I2C_SCLL_SCLL (0)
+#define I2C_SCLL_SCLL_M (0xFF)
+#define I2C_SCLL_HSSCLL (8)
+#define I2C_SCLH_HSSCLL_M (0xFF)
+#define I2C_SCLH_SCLH (0)
+#define I2C_SCLH_SCLH_M (0xFF)
+#define I2C_SCLH_HSSCLH (8)
+#define I2C_SCLH_HSSCLH_M (0xFF)
+
+#define OMAP_I2C_STANDARD 100
+#define OMAP_I2C_FAST_MODE 400
+#define OMAP_I2C_HIGH_SPEED 3400
+
+#define SYSTEM_CLOCK_12 12000
+#define SYSTEM_CLOCK_13 13000
+#define SYSTEM_CLOCK_192 19200
+#define SYSTEM_CLOCK_96 96000
+
+#define I2C_IP_CLK SYSTEM_CLOCK_96
+#define I2C_PSC_MAX (0x0f)
+#define I2C_PSC_MIN (0x00)
+
+#endif /* _I2C_H_ */
Index: u-boot-arm/include/asm-arm/arch-omap3/mem.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/mem.h
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+#define SDRC_CS0_OSET 0x0
+#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
+
+#ifndef __ASSEMBLY__
+
+typedef enum {
+ STACKED = 0,
+ IP_DDR = 1,
+ COMBO_DDR = 2,
+ IP_SDR = 3,
+} mem_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define EARLY_INIT 1
+
+/* Slower full frequency range default timings for x32 operation*/
+#define SDP_SDRC_SHARING 0x00000100
+#define SDP_SDRC_MR_0_SDR 0x00000031
+
+/* optimized timings good for current shipping parts */
+#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+
+#define DLL_OFFSET 0
+#define DLL_WRITEDDRCLKX2DIS 1
+#define DLL_ENADLL 1
+#define DLL_LOCKDLL 0
+#define DLL_DLLPHASE_72 0
+#define DLL_DLLPHASE_90 1
+
+/* rkw - need to find of 90/72 degree recommendation for speed like before */
+#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
+ (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
+
+/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
+ * ACTIMA
+ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
+ * TDPL (Twr) = 15/6 = 2.5 -> 3
+ * TRRD = 12/6 = 2
+ * TRCD = 18/6 = 3
+ * TRP = 18/6 = 3
+ * TRAS = 42/6 = 7
+ * TRC = 60/6 = 10
+ * TRFC = 72/6 = 12
+ * ACTIMB
+ * TCKE = 2
+ * XSR = 120/6 = 20
+ */
+#define TDAL_165 6
+#define TDPL_165 3
+#define TRRD_165 2
+#define TRCD_165 3
+#define TRP_165 3
+#define TRAS_165 7
+#define TRC_165 10
+#define TRFC_165 12
+#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) \
+ | (TRP_165 << 15) | (TRCD_165 << 12) | (TRRD_165 << 9) | \
+ (TDPL_165 << 6) | (TDAL_165))
+
+#define TWTR_165 1
+#define TCKE_165 2
+#define TXP_165 2
+#define XSR_165 20
+#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
+ (TXP_165 << 8) | (TWTR_165 << 16))
+
+# define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
+# define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
+# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * # define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * STNOR - Intel Strata Flash
+ * SMNAND - Samsung NAND
+ * MPDB - H4 MPDB board
+ * SBNOR - Sibley NOR
+ * MNAND - Micron Large page x16 NAND
+ * ONNAND - Samsung One NAND
+ *
+ * include/configs/file.h contains the defn - for all CS we are interested
+ * #define OMAP34XX_GPMC_CSx PART
+ * #define OMAP34XX_GPMC_CSx_SIZE Size
+ * #define OMAP34XX_GPMC_CSx_MAP Map
+ * Where:
+ * x - CS number
+ * PART - Part Name as defined above
+ * SIZE - how big is the mapping to be
+ * GPMC_SIZE_128M - 0x8
+ * GPMC_SIZE_64M - 0xC
+ * GPMC_SIZE_32M - 0xE
+ * GPMC_SIZE_16M - 0xF
+ * MAP - Map this CS to which address(GPMC address space)- Absolute address
+ * >>24 before being used.
+ */
+#define GPMC_SIZE_128M 0x8
+#define GPMC_SIZE_64M 0xC
+#define GPMC_SIZE_32M 0xE
+#define GPMC_SIZE_16M 0xF
+
+# define SMNAND_GPMC_CONFIG1 0x00000800
+# define SMNAND_GPMC_CONFIG2 0x00141400
+# define SMNAND_GPMC_CONFIG3 0x00141400
+# define SMNAND_GPMC_CONFIG4 0x0F010F01
+# define SMNAND_GPMC_CONFIG5 0x010C1414
+# define SMNAND_GPMC_CONFIG6 0x1F0F0A80
+# define SMNAND_GPMC_CONFIG7 0x00000C44
+
+# define M_NAND_GPMC_CONFIG1 0x00001800
+# define M_NAND_GPMC_CONFIG2 0x00141400
+# define M_NAND_GPMC_CONFIG3 0x00141400
+# define M_NAND_GPMC_CONFIG4 0x0F010F01
+# define M_NAND_GPMC_CONFIG5 0x010C1414
+# define M_NAND_GPMC_CONFIG6 0x1f0f0A80
+# define M_NAND_GPMC_CONFIG7 0x00000C44
+
+# define STNOR_GPMC_CONFIG1 0x3
+# define STNOR_GPMC_CONFIG2 0x00151501
+# define STNOR_GPMC_CONFIG3 0x00060602
+# define STNOR_GPMC_CONFIG4 0x11091109
+# define STNOR_GPMC_CONFIG5 0x01141F1F
+# define STNOR_GPMC_CONFIG6 0x000004c4
+
+# define SIBNOR_GPMC_CONFIG1 0x1200
+# define SIBNOR_GPMC_CONFIG2 0x001f1f00
+# define SIBNOR_GPMC_CONFIG3 0x00080802
+# define SIBNOR_GPMC_CONFIG4 0x1C091C09
+# define SIBNOR_GPMC_CONFIG5 0x01131F1F
+# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
+
+# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
+# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
+# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
+# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
+# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
+# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
+
+# define MPDB_GPMC_CONFIG1 0x00011000
+# define MPDB_GPMC_CONFIG2 0x001f1f01
+# define MPDB_GPMC_CONFIG3 0x00080803
+# define MPDB_GPMC_CONFIG4 0x1c0b1c0a
+# define MPDB_GPMC_CONFIG5 0x041f1F1F
+# define MPDB_GPMC_CONFIG6 0x1F0F04C4
+
+# define P2_GPMC_CONFIG1 0x0
+# define P2_GPMC_CONFIG2 0x0
+# define P2_GPMC_CONFIG3 0x0
+# define P2_GPMC_CONFIG4 0x0
+# define P2_GPMC_CONFIG5 0x0
+# define P2_GPMC_CONFIG6 0x0
+
+# define ONENAND_GPMC_CONFIG1 0x00001200
+# define ONENAND_GPMC_CONFIG2 0x000F0F01
+# define ONENAND_GPMC_CONFIG3 0x00030301
+# define ONENAND_GPMC_CONFIG4 0x0F040F04
+# define ONENAND_GPMC_CONFIG5 0x010F1010
+# define ONENAND_GPMC_CONFIG6 0x1F060000
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS 8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG 7
+
+#define PISMO1_NOR 1
+#define PISMO1_NAND 2
+#define PISMO2_CS0 3
+#define PISMO2_CS1 4
+#define PISMO1_ONENAND 5
+#define DBG_MPDB 6
+#define PISMO2_NAND_CS0 7
+#define PISMO2_NAND_CS1 8
+
+/* make it readable for the gpmc_init */
+#define PISMO1_NOR_BASE FLASH_BASE
+#define PISMO1_NAND_BASE NAND_BASE
+#define PISMO2_CS0_BASE PISMO2_MAP1
+#define PISMO1_ONEN_BASE ONENAND_MAP
+#define DBG_MPDB_BASE DEBUG_BASE
+
+#endif /* endif _MEM_H_ */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers
@ 2008-10-03 10:38 ` dirk.behme at googlemail.com
2008-10-05 1:23 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 6+ messages in thread
From: dirk.behme at googlemail.com @ 2008-10-03 10:38 UTC (permalink / raw)
To: u-boot
Subject: [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers
From: Dirk Behme <dirk.behme@gmail.com>
Add overo pin mux, omap3 and prototype headers
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
---
Changes in version v2:
- Update Overo pin mux to add and pull down X_GATE, by Steve Sakoman.
include/asm-arm/arch-omap3/mux.h | 337 +++++++++++++++++++++++++++++++++
include/asm-arm/arch-omap3/omap3.h | 135 +++++++++++++
include/asm-arm/arch-omap3/sys_proto.h | 71 ++++++
3 files changed, 543 insertions(+)
Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h
===================================================================
--- u-boot-arm.orig/include/asm-arm/arch-omap3/mux.h
+++ u-boot-arm/include/asm-arm/arch-omap3/mux.h
@@ -754,4 +754,341 @@
MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+#define MUX_DEFAULT_OVERO() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_nCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
+ /* - MMC1_WP*/\
+ MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
+ MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTU | EN | M4)) /*GPIO_115*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(McBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(McBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(McBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(McBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
+ MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144*/\
+ /* - LCD_EN*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150*/ \
+ /* - MMC3_WP*/\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
+ MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
+ MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\
+ MUX_VAL(CP(McBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
+ MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\
+ MUX_VAL(CP(McBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\
+ MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\
+ MUX_VAL(CP(McBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\
+ MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(McBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\
+ MUX_VAL(CP(McBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_*/\
+ /* RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
+ /* BT_NRESET*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
+ /* - USBH_CPEN*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ /* - USBH_RESET*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
+ MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
+ MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
+ MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
+ MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ MUX_VAL(CP(McSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(McSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(McSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(McSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(McSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(McSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
+ /* - MMC1_WP */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT4*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15*/\
+ /* - X_GATE*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\
+ /* - W2W_NRESET*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT7*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT6*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT5*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | EN | M3)) /*HSUSB2_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\
+ /* die to die */\
+ MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(d2d_nrespwron), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(d2d_uma2p6fiq), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+
#endif
Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/omap3.h
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP3_H_
+#define _OMAP3_H_
+
+/* Stuff on L3 Interconnect */
+#define SMX_APE_BASE 0x68000000
+
+/* GPMC */
+#define OMAP34XX_GPMC_BASE (0x6E000000)
+
+/* SMS */
+#define OMAP34XX_SMS_BASE 0x6C000000
+
+/* SDRC */
+#define OMAP34XX_SDRC_BASE 0x6D000000
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
+#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
+#define OMAP34XX_L4_PER 0x49000000
+#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
+
+/* CONTROL */
+#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE+0x2000)
+
+/* UART */
+#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE+0x6a000)
+#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE+0x6c000)
+#define OMAP34XX_UART3 (OMAP34XX_L4_PER+0x20000)
+
+/* General Purpose Timers */
+#define OMAP34XX_GPT1 0x48318000
+#define OMAP34XX_GPT2 0x49032000
+#define OMAP34XX_GPT3 0x49034000
+#define OMAP34XX_GPT4 0x49036000
+#define OMAP34XX_GPT5 0x49038000
+#define OMAP34XX_GPT6 0x4903A000
+#define OMAP34XX_GPT7 0x4903C000
+#define OMAP34XX_GPT8 0x4903E000
+#define OMAP34XX_GPT9 0x49040000
+#define OMAP34XX_GPT10 0x48086000
+#define OMAP34XX_GPT11 0x48088000
+#define OMAP34XX_GPT12 0x48304000
+
+/* WatchDog Timers (1 secure, 3 GP) */
+#define WD1_BASE (0x4830C000)
+#define WD2_BASE (0x48314000)
+#define WD3_BASE (0x49030000)
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE (0x48320000)
+#define S32K_CR (SYNC_32KTIMER_BASE+0x10)
+
+/* omap3 GPIO registers */
+#define OMAP34XX_GPIO1_BASE 0x48310000
+#define OMAP34XX_GPIO2_BASE 0x49050000
+#define OMAP34XX_GPIO3_BASE 0x49052000
+#define OMAP34XX_GPIO4_BASE 0x49054000
+#define OMAP34XX_GPIO5_BASE 0x49056000
+#define OMAP34XX_GPIO6_BASE 0x49058000
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0 0x40000000
+#define SRAM_OFFSET1 0x00200000
+#define SRAM_OFFSET2 0x0000F800
+#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|\
+ SRAM_OFFSET2)
+
+#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
+
+#define DEBUG_LED1 149 /* gpio */
+#define DEBUG_LED2 150 /* gpio */
+
+#define XDR_POP 5 /* package on package part */
+#define SDR_DISCRETE 4 /* 128M memory SDR module */
+#define DDR_STACKED 3 /* stacked part on 2422 */
+#define DDR_COMBO 2 /* combo part on cpu daughter card */
+#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
+
+#define DDR_100 100 /* type found on most mem d-boards */
+#define DDR_111 111 /* some combo parts */
+#define DDR_133 133 /* most combo, some mem d-boards */
+#define DDR_165 165 /* future parts */
+
+#define CPU_3430 0x3430
+
+/* 343x real hardware:
+ * ES1 = rev 0
+ */
+
+/* 343x code defines:
+ * ES1 = 0+1 = 1
+ * ES1 = 1+1 = 1
+ */
+#define CPU_3430_ES1 1
+#define CPU_3430_ES2 2
+
+#define WIDTH_8BIT 0x0000
+#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
+
+/* SDP definitions according to FPGA Rev. Is this OK?? */
+#define SDP_3430_V1 0x1
+#define SDP_3430_V2 0x2
+
+/* EVM definitions */
+#define OMAP3EVM_V1 0x1
+#define OMAP3EVM_V2 0x2
+
+#endif
Index: u-boot-arm/include/asm-arm/arch-omap3/sys_proto.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/sys_proto.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+typedef struct {
+ u32 board_type_v1;
+ u32 board_type_v2;
+ char *cpu_string;
+ char *board_string;
+} omap3_sysinfo;
+
+void prcm_init(void);
+void per_clocks_enable(void);
+
+void memif_init(void);
+void sdrc_init(void);
+void do_sdrc_init(u32, u32);
+void gpmc_init(void);
+
+void watchdog_init(void);
+void set_muxconf_regs(void);
+
+u32 get_cpu_type(void);
+u32 get_cpu_rev(void);
+u32 get_mem_type(void);
+u32 get_sysboot_value(void);
+u32 get_gpmc0_base(void);
+u32 is_gpmc_muxed(void);
+u32 get_gpmc0_type(void);
+u32 get_gpmc0_width(void);
+u32 get_board_type(void);
+void display_board_info(u32);
+u32 get_sdr_cs_size(u32 offset);
+u32 running_in_sdram(void);
+u32 running_in_sram(void);
+u32 running_in_flash(void);
+u32 running_from_internal_boot(void);
+u32 get_device_type(void);
+void l2cache_enable(void);
+void secureworld_exit(void);
+void setup_auxcr(void);
+void try_unlock_memory(void);
+u32 get_boot_type(void);
+void audio_init(void);
+void dss_init(void);
+void arm_cache_flush(void);
+void v7_flush_dcache_all(u32);
+void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
+void sdelay(unsigned long loops);
+
+#endif
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 02/12 v2] ARM: OMAP3: Add i2c, memory and additional pin mux headers
2008-10-03 10:37 ` [U-Boot] [PATCH 02/12 v2] ARM: OMAP3: Add i2c, memory and additional pin mux headers dirk.behme at googlemail.com
2008-10-03 10:38 ` [U-Boot] [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers dirk.behme at googlemail.com
@ 2008-10-05 1:18 ` Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 0 replies; 6+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-10-05 1:18 UTC (permalink / raw)
To: u-boot
On 12:37 Fri 03 Oct , dirk.behme at googlemail.com wrote:
> Subject: [PATCH 02/12 v2] ARM: OMAP3: Add i2c, memory and additional pin mux headers
>
> From: Dirk Behme <dirk.behme@gmail.com>
>
> Add OMAP3 I2C, memory and additional pin mux headers
>
> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
>
> ---
> include/asm-arm/arch-omap3/i2c.h | 128 ++++++++++++++
> include/asm-arm/arch-omap3/mem.h | 220 ++++++++++++++++++++++++
> include/asm-arm/arch-omap3/mux.h | 350 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 698 insertions(+)
>
> Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h
> ===================================================================
> --- u-boot-arm.orig/include/asm-arm/arch-omap3/mux.h
> +++ u-boot-arm/include/asm-arm/arch-omap3/mux.h
> @@ -404,4 +404,354 @@
> #define CONTROL_PADCONF_sdrc_cke0 0x0262
^^^^^
please use tab instead of space
please do it in all of patch
> #define CONTROL_PADCONF_sdrc_cke1 0x0264
^^^^^
Ditto and etc...
Best Regards
J.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers
2008-10-03 10:38 ` [U-Boot] [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers dirk.behme at googlemail.com
@ 2008-10-05 1:23 ` Jean-Christophe PLAGNIOL-VILLARD
2008-10-05 6:56 ` Dirk Behme
0 siblings, 1 reply; 6+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-10-05 1:23 UTC (permalink / raw)
To: u-boot
On 12:38 Fri 03 Oct , dirk.behme at googlemail.com wrote:
> Subject: [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers
>
> From: Dirk Behme <dirk.behme@gmail.com>
>
> Add overo pin mux, omap3 and prototype headers
>
> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
>
> ---
> Changes in version v2:
>
> - Update Overo pin mux to add and pull down X_GATE, by Steve Sakoman.
>
> include/asm-arm/arch-omap3/mux.h | 337 +++++++++++++++++++++++++++++++++
> include/asm-arm/arch-omap3/omap3.h | 135 +++++++++++++
> include/asm-arm/arch-omap3/sys_proto.h | 71 ++++++
> 3 files changed, 543 insertions(+)
>
> Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h
> ===================================================================
> --- u-boot-arm.orig/include/asm-arm/arch-omap3/mux.h
> +++ u-boot-arm/include/asm-arm/arch-omap3/mux.h
> @@ -754,4 +754,341 @@
> MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
Same as before
please use tab instead of space
and please be carefull of 80 chards limit
Best Regaards,
J.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers
2008-10-05 1:23 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2008-10-05 6:56 ` Dirk Behme
0 siblings, 0 replies; 6+ messages in thread
From: Dirk Behme @ 2008-10-05 6:56 UTC (permalink / raw)
To: u-boot
Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 12:38 Fri 03 Oct , dirk.behme at googlemail.com wrote:
>
>>Subject: [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers
>>
>>From: Dirk Behme <dirk.behme@gmail.com>
>>
>>Add overo pin mux, omap3 and prototype headers
>>
>>Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
>>
>>---
>>Changes in version v2:
>>
>>- Update Overo pin mux to add and pull down X_GATE, by Steve Sakoman.
>>
>> include/asm-arm/arch-omap3/mux.h | 337 +++++++++++++++++++++++++++++++++
>> include/asm-arm/arch-omap3/omap3.h | 135 +++++++++++++
>> include/asm-arm/arch-omap3/sys_proto.h | 71 ++++++
>> 3 files changed, 543 insertions(+)
>>
>>Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h
>>===================================================================
>>--- u-boot-arm.orig/include/asm-arm/arch-omap3/mux.h
>>+++ u-boot-arm/include/asm-arm/arch-omap3/mux.h
>>@@ -754,4 +754,341 @@
>> MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
>
> Same as before
> please use tab instead of space
Thanks for review. Will do so (for 02/12, too).
> and please be carefull of 80 chards limit
Do you mean now or after replacing spaces with tabs?
I carefully checked and think that at the moment (so the space
version) has everything < 80 chars. If not, please let me know where
you found violation.
Well, with tab instead of space most probably it will become hard to
stay < 80 chars. But I will see what I can do.
Thanks for looking@it,
Dirk
P.S.: When we fix space/tab and the nand issue, will you apply this
patchset to u-boot-arm next, then?
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2008-10-05 6:56 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2008-10-03 10:37 [U-Boot] [PATCH 01/12 v2] ARM: OMAP3: Add pin mux, clock and cpu headers dirk.behme at googlemail.com
2008-10-03 10:37 ` [U-Boot] [PATCH 02/12 v2] ARM: OMAP3: Add i2c, memory and additional pin mux headers dirk.behme at googlemail.com
2008-10-03 10:38 ` [U-Boot] [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers dirk.behme at googlemail.com
2008-10-05 1:23 ` Jean-Christophe PLAGNIOL-VILLARD
2008-10-05 6:56 ` Dirk Behme
2008-10-05 1:18 ` [U-Boot] [PATCH 02/12 v2] ARM: OMAP3: Add i2c, memory and additional pin mux headers Jean-Christophe PLAGNIOL-VILLARD
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