From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jon Loeliger <jdl@freescale.com>
Date: Tue, 07 Oct 2008 17:26:28 -0500
Subject: [U-Boot] [PATCH 1/6] Make DDR interleaving mode work correctly
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	<2acbd3e40810071438k6108c8bg6a4202994a613115@mail.gmail.com>
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Andy Fleming wrote:
> If Kim and Jon approve, I'll pull these 6 patches into my 85xx-next branch.
> 
> On Fri, Oct 3, 2008 at 11:36 AM, Haiying Wang
> <Haiying.Wang@freescale.com> wrote:
>> Fix some bugs:
>>  1. Correctly set intlv_ctl in cs_config.
>>  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
>>  3. Set base_address and total memory for each ddr controller in memory
>>     controller interleaving mode.
>>
>> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>


Sounds good by me.

ACK.

jdl