From mboxrd@z Thu Jan  1 00:00:00 1970
From: Wolfgang Grandegger <wg@grandegger.com>
Date: Fri, 10 Oct 2008 17:16:21 +0200
Subject: [U-Boot] [PATCH] 85xx: Using proper I2C source clock divider
 for MPC8544
In-Reply-To: <3972ECD0-E62A-4213-B225-484A9A5DDDA8@kernel.crashing.org>
References: <48E1E99D.2000401@grandegger.com>	<6E1F524F-919E-4ADC-AD48-E6C0ECABA5B1@kernel.crashing.org>	<48EF0474.4080409@grandegger.com>
	<3972ECD0-E62A-4213-B225-484A9A5DDDA8@kernel.crashing.org>
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Kumar Gala wrote:
> On Oct 10, 2008, at 2:29 AM, Wolfgang Grandegger wrote:
> 
>> Kumar Gala wrote:
>>> On Sep 30, 2008, at 3:55 AM, Wolfgang Grandegger wrote:
>>>
>>>> Measurements with our MPC8544 board showed that the I2C bus  
>>>> frequency
>>>> is wrong by a factor of 1.5. Obviously, the interpretation of the
>>>> MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not
>>>> correct. There seems to be an error in the 8544 RM.
>>>>
>>>> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
>>>> ---
>>>> cpu/mpc85xx/speed.c |    4 ++--
>>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>> can you do me a favor and dump the value of MPC85xx_PORDEVSR2.  Also
>>> can you tell me what rev 8544 you have.
>> See below:
>>
>>  pordevsr2 at e00e0014=0x8f00007d
>>
>>  CPU:   8544E, Version: 1.1, (0x803c0111)
>>  Core:  E500, Version: 2.2, (0x80210022)
>>  Clock Configuration:
>>         CPU: 667 MHz, CCB: 334 MHz,
>>         DDR: 167 MHz (334 MT/s data rate), LBC:  41 MHz
>>  L1:    D-cache 32 kB enabled
>>         I-cache 32 kB enabled
>>  Board: Socrates
>>
>> Wolfgang.
> 
> thanks.  How did you do the measurements that got you this 1.5x factor?

Actually, this problem was reported by a customer using the I2C bus on
the MPC8544E intensively. I'm going to find out how he did the measurements.

Wolfgang.