* [U-Boot] [PATCH 0/9] MPC8641 memory map changes/cleanup/36-bit
@ 2008-11-05 20:55 Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 1/9] mpc8641: Remove extra "0" from BR2 define Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-05 20:55 UTC (permalink / raw)
To: u-boot
board/freescale/mpc8641hpcn/config.mk | 2 +-
board/freescale/mpc8641hpcn/law.c | 30 ++--
cpu/mpc86xx/cpu_init.c | 4 +
cpu/mpc86xx/start.S | 90 +++++++-----
include/configs/MPC8610HPCD.h | 9 +
include/configs/MPC8641HPCN.h | 260 ++++++++++++++++++++++-----------
include/configs/sbc8641d.h | 9 +
7 files changed, 267 insertions(+), 137 deletions(-)
This is the remainer of the patches required to get 36-bit
physical addressing working on 8641HPCN.
This patch series consists of:
- Various cleanup patches for 8641
- Getting rid of the nonexistent second flash bank
- A new 32-bit memory map to make the layout more like 85xx
- A new 36-bit memory map and the ability to enable
CONFIG_PHYS_64BIT to turn on locating devices in high
physical address space.
Note: With these changes, an updated device tree is required to
boot Linux; I will be pushing that to Linux shortly.
Cheers,
Becky
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 1/9] mpc8641: Remove extra "0" from BR2 define
2008-11-05 20:55 [U-Boot] [PATCH 0/9] MPC8641 memory map changes/cleanup/36-bit Becky Bruce
@ 2008-11-05 20:55 ` Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 2/9] mpc86xx: Move setup_bats into cpu_init_f Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-05 20:55 UTC (permalink / raw)
To: u-boot
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
include/configs/MPC8641HPCN.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 1401e15..779e9a8 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -186,7 +186,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/
#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \
- | 0x000001001) /* port size 16bit */
+ | 0x00001001) /* port size 16bit */
#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE) \
--
1.5.5.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 2/9] mpc86xx: Move setup_bats into cpu_init_f
2008-11-05 20:55 ` [U-Boot] [PATCH 1/9] mpc8641: Remove extra "0" from BR2 define Becky Bruce
@ 2008-11-05 20:55 ` Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 3/9] mpc8641: only define CONFIG_ENV_SIZE once Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-05 20:55 UTC (permalink / raw)
To: u-boot
In order to later allow for a physical relocation of the
flash, setup_bats, which sets up the final BAT mapping
for the board, needs to happen *after* init_laws().
Otherwise, there will be no window programmed for the flash
at the new physical location at the point when we change
the mmu translation.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
cpu/mpc86xx/cpu_init.c | 4 ++++
cpu/mpc86xx/start.S | 5 -----
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 06f179c..a7e6036 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -33,6 +33,8 @@
#include <asm/fsl_law.h>
#include "mp.h"
+void setup_bats(void);
+
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -57,6 +59,8 @@ void cpu_init_f(void)
init_laws();
#endif
+ setup_bats();
+
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 48f8c5a..0d30e91 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -272,11 +272,6 @@ in_flash:
GET_GOT /* initialize GOT access */
- /* setup the rest of the bats */
- bl setup_bats
- sync
-
-
/* run low-level CPU init code (from Flash) */
bl cpu_init_f
sync
--
1.5.5.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 3/9] mpc8641: only define CONFIG_ENV_SIZE once
2008-11-05 20:55 ` [U-Boot] [PATCH 2/9] mpc86xx: Move setup_bats into cpu_init_f Becky Bruce
@ 2008-11-05 20:55 ` Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 4/9] mpc8641: Drop imaginary second flash bank, map 8MB Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-05 20:55 UTC (permalink / raw)
To: u-boot
It's currently defined twice inside in an if/else block, but
both halves set the same value. Move the define outside
the if.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
include/configs/MPC8641HPCN.h | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 779e9a8..8c85881 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -522,12 +522,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
#endif
+#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 4/9] mpc8641: Drop imaginary second flash bank, map 8MB
2008-11-05 20:55 ` [U-Boot] [PATCH 3/9] mpc8641: only define CONFIG_ENV_SIZE once Becky Bruce
@ 2008-11-05 20:55 ` Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 5/9] mpc8641: make DIAG_ADDR == FLASH_BASE Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-05 20:55 UTC (permalink / raw)
To: u-boot
There's a lot of setup and foo for the second flash
bank. The problem is, this board doesn't actually have one.
Clean this up. Also, the flash is 8M in size. Get rid
of the confusing aliased overmapping, and just map 8M.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
board/freescale/mpc8641hpcn/law.c | 2 +-
include/configs/MPC8641HPCN.h | 41 ++++++++++++------------------------
2 files changed, 15 insertions(+), 28 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 1ad186c..8ec5238 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -58,7 +58,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
#endif
SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
- SET_LAW((CONFIG_SYS_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 8c85881..d77f0fc 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -159,31 +159,16 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/*
- * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
- * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
- * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
- * However, when u-boot comes up, the flash_init needs hard start addresses
- * to build its info table. For user convenience, the flash addresses is
- * fe800000 and ff800000. That way, u-boot knows where the flash is
- * and the user can download u-boot code from promjet to fef00000, a
- * more intuitive location than fe700000.
- *
- * Note that, on switching the boot location, fef00000 becomes fff00000.
- */
-#define CONFIG_SYS_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
-#define CONFIG_SYS_FLASH_BASE2 0xff800000
+#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
/* Convert an address into the right format for the BR registers */
#define BR_PHYS_ADDR(x) (x & 0xffff8000)
-#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/
-
-#define CONFIG_SYS_BR1_PRELIM 0xfe001001 /* port size 16bit */
-#define CONFIG_SYS_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) \
+ | 0x00001001) /* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \
| 0x00001001) /* port size 16bit */
@@ -215,7 +200,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
#define CF_BASE (PIXIS_BASE + 0x00100000)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
@@ -501,13 +486,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
/*
- * BAT6 32M Cache-inhibited, guarded
- * 0xfe00_0000 32M FLASH
+ * BAT6 8M Cache-inhibited, guarded
+ * 0xff80_0000 8M FLASH
*/
-#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
#define CONFIG_SYS_DBAT7L 0x00000000
--
1.5.5.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 5/9] mpc8641: make DIAG_ADDR == FLASH_BASE
2008-11-05 20:55 ` [U-Boot] [PATCH 4/9] mpc8641: Drop imaginary second flash bank, map 8MB Becky Bruce
@ 2008-11-05 20:55 ` Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 6/9] mpc86xx: Use SRR0/1/rfi to enable address translation, not blr Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-05 20:55 UTC (permalink / raw)
To: u-boot
Currently, that's what it is, but it's hardcoded.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
include/configs/MPC8641HPCN.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index d77f0fc..0a6d5f9 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -40,7 +40,7 @@
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR 0xff800000
+#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
--
1.5.5.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/9] mpc86xx: Use SRR0/1/rfi to enable address translation, not blr
2008-11-05 20:55 ` [U-Boot] [PATCH 5/9] mpc8641: make DIAG_ADDR == FLASH_BASE Becky Bruce
@ 2008-11-05 20:55 ` Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 7/9] mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLY Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-05 20:55 UTC (permalink / raw)
To: u-boot
Using a mtmsr/blr means that you have to be executing at the
same virtual address once you enable translation. This is
unnecessarily restrictive, and is not really how this is
usually done. Change it to use the more common mtspr SRR0/SRR1
and rfi method.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
cpu/mpc86xx/start.S | 19 ++++++++-----------
1 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 0d30e91..7e36801 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -244,9 +244,15 @@ in_flash:
*/
/* enable address translation */
- bl enable_addr_trans
- sync
+ mfmsr r5
+ ori r5, r5, (MSR_IR | MSR_DR)
+ lis r3,addr_trans_enabled at h
+ ori r3, r3, addr_trans_enabled at l
+ mtspr SPRN_SRR0,r3
+ mtspr SPRN_SRR1,r5
+ rfi
+addr_trans_enabled:
/* enable and invalidate the data cache */
/* bl l1dcache_enable */
bl dcache_enable
@@ -423,15 +429,6 @@ tlblp:
blt tlblp
blr
- .globl enable_addr_trans
-enable_addr_trans:
- /* enable address translation */
- mfmsr r5
- ori r5, r5, (MSR_IR | MSR_DR)
- mtmsr r5
- isync
- blr
-
.globl disable_addr_trans
disable_addr_trans:
/* disable address translation */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 7/9] mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLY
2008-11-05 20:55 ` [U-Boot] [PATCH 6/9] mpc86xx: Use SRR0/1/rfi to enable address translation, not blr Becky Bruce
@ 2008-11-05 20:55 ` Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-05 20:55 UTC (permalink / raw)
To: u-boot
We define CONFIG_MONITOR_BASE_EARLY to define the initial location
of the bootpage in flash. Use this to create an early mapping
definition for the FLASH, and change the early_bats code to use this.
This change facilitates the relocation of the flash since the early
mappings are no longer tied to the final location of the flash.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
cpu/mpc86xx/start.S | 20 ++++++++++----------
include/configs/MPC8610HPCD.h | 9 +++++++++
include/configs/MPC8641HPCN.h | 12 +++++++++++-
include/configs/sbc8641d.h | 9 +++++++++
4 files changed, 39 insertions(+), 11 deletions(-)
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 7e36801..60af3dd 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -217,8 +217,8 @@ boot_warm:
/*
* Calculate absolute address in FLASH and jump there
*------------------------------------------------------*/
- lis r3, CONFIG_SYS_MONITOR_BASE at h
- ori r3, r3, CONFIG_SYS_MONITOR_BASE at l
+ lis r3, CONFIG_SYS_MONITOR_BASE_EARLY at h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY at l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
@@ -398,19 +398,19 @@ early_bats:
isync
/* IBAT 6 */
- lis r4, CONFIG_SYS_IBAT6L at h
- ori r4, r4, CONFIG_SYS_IBAT6L at l
- lis r3, CONFIG_SYS_IBAT6U at h
- ori r3, r3, CONFIG_SYS_IBAT6U at l
+ lis r4, CONFIG_SYS_IBAT6L_EARLY at h
+ ori r4, r4, CONFIG_SYS_IBAT6L_EARLY at l
+ lis r3, CONFIG_SYS_IBAT6U_EARLY at h
+ ori r3, r3, CONFIG_SYS_IBAT6U_EARLY at l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
isync
/* DBAT 6 */
- lis r4, CONFIG_SYS_DBAT6L at h
- ori r4, r4, CONFIG_SYS_DBAT6L at l
- lis r3, CONFIG_SYS_DBAT6U at h
- ori r3, r3, CONFIG_SYS_DBAT6U at l
+ lis r4, CONFIG_SYS_DBAT6L_EARLY at h
+ ori r4, r4, CONFIG_SYS_DBAT6L_EARLY at l
+ lis r3, CONFIG_SYS_DBAT6U_EARLY at h
+ ori r3, r3, CONFIG_SYS_DBAT6U_EARLY at l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
isync
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 4486763..f2fe4a6 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -187,6 +187,7 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
@@ -419,6 +420,14 @@
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
+
/*
* BAT7 4M Cache-inhibited, guarded
* 0xe800_0000 4M PIXIS
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 0a6d5f9..4925057 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -206,7 +206,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
@@ -497,6 +498,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
+
+/* Leave BAT7 free here - it is used for various things later */
#define CONFIG_SYS_DBAT7L 0x00000000
#define CONFIG_SYS_DBAT7U 0x00000000
#define CONFIG_SYS_IBAT7L 0x00000000
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index e8216ea..45d8179 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -231,6 +231,7 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
@@ -463,6 +464,14 @@
#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
+
#define CONFIG_SYS_DBAT7L 0x00000000
#define CONFIG_SYS_DBAT7U 0x00000000
#define CONFIG_SYS_IBAT7L 0x00000000
--
1.5.5.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-05 20:55 ` [U-Boot] [PATCH 7/9] mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLY Becky Bruce
@ 2008-11-05 20:55 ` Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 9/9] mpc8641: Support 36-bit physical addressing Becky Bruce
` (2 more replies)
0 siblings, 3 replies; 31+ messages in thread
From: Becky Bruce @ 2008-11-05 20:55 UTC (permalink / raw)
To: u-boot
The memory map on the 8641hpcn is modified to look more like
the 85xx boards; this is a step towards a more standardized
layout going forward. As part of this change, we now relocate
the flash.
The regions for some of the mappings were far larger than they
needed to be. I have reduced the mappings to match the
actual sizes supported by the hardware.
In addition I have removed the comments at the head
of the BAT blocks in the config file, rather than updating
them. These get horribly out of date, and it's a simple
matter to look at the defines to see what they are set to
since everything is right here in the same file.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
board/freescale/mpc8641hpcn/config.mk | 2 +-
board/freescale/mpc8641hpcn/law.c | 23 ++++++----
cpu/mpc86xx/start.S | 2 +-
include/configs/MPC8641HPCN.h | 76 +++++++++++++++++----------------
4 files changed, 54 insertions(+), 49 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/config.mk b/board/freescale/mpc8641hpcn/config.mk
index f778dcb..487a766 100644
--- a/board/freescale/mpc8641hpcn/config.mk
+++ b/board/freescale/mpc8641hpcn/config.mk
@@ -25,7 +25,7 @@
# default CCSRBAR is at 0xff700000
# assume U-Boot is less than 0.5MB
#
-TEXT_BASE = 0xfff00000
+TEXT_BASE = 0xeff00000
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 8ec5238..669a091 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -31,17 +31,20 @@
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
+ * if PCI
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
- * 0xf800_0000 0xf80f_ffff CCSRBAR 1M
- * 0xf810_0000 0xf81f_ffff PIXIS 1M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ * else if RIO
+ * 0x8000_0000 0x9fff_ffff RapidIO 512M
+ * endif
+ * 0xffc0_0000 0xffc0_ffff PCI1 IO 64K
+ * 0xffc1_0000 0xffc1_ffff PCI2 IO 64K
+ * 0xffe0_0000 0xffef_ffff CCSRBAR 1M
+ * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K
+ * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M
*
* Notes:
- * CCSRBAR don't need a configured Local Access Window.
+ * CCSRBAR doesn't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
@@ -52,12 +55,12 @@ struct law_entry law_table[] = {
#ifdef CONFIG_PCI
SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
#elif defined(CONFIG_RIO)
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
#endif
- SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
};
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 60af3dd..0aa8a4f 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -285,7 +285,7 @@ addr_trans_enabled:
#ifdef RUN_DIAG
/* Load PX_AUX register address in r4 */
- lis r4, 0xf810
+ lis r4, PIXIS_BASE at h
ori r4, r4, 0x6
/* Load contents of PX_AUX in r3 bits 24 to 31*/
lbz r3, 0(r4)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 4925057..ec3d112 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -96,7 +96,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
@@ -159,7 +159,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
@@ -172,15 +172,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \
| 0x00001001) /* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
+#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE) \
| 0x00000801) /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
+/*
+ * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
+ * The PIXIS and CF by themselves aren't large enough to take up the 128k
+ * required for the smallest BAT mapping, so there's a 64k hole.
+ */
+#define CONFIG_SYS_LBC_BASE 0xffde0000
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE (CONFIG_SYS_CCSRBAR + 0x00100000) /* PIXIS registers */
+#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
+#define PIXIS_SIZE 0x00008000 /* 32k */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
@@ -198,7 +205,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
-#define CF_BASE (PIXIS_BASE + 0x00100000)
+#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -287,7 +294,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */
#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
@@ -299,8 +306,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */
/* For RTL8139 */
#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
@@ -313,7 +320,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
+ CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
#if defined(CONFIG_PCI)
@@ -413,8 +420,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif /* CONFIG_TSEC_ENET */
/*
- * BAT0 2G Cacheable, non-guarded
- * 0x0000_0000 2G DDR
+ * BAT0 DDR
*/
#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
@@ -422,22 +428,20 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
/*
- * BAT1 unused
+ * BAT1 LBC (PIXIS/CF)
*/
-#define CONFIG_SYS_DBAT1L 0
-#define CONFIG_SYS_DBAT1U 0
-#define CONFIG_SYS_IBAT1L 0
-#define CONFIG_SYS_IBAT1U 0
+#define CONFIG_SYS_DBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
+ | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
/* if CONFIG_PCI:
- * BAT2 1G Cache-inhibited, guarded
- * 0x8000_0000 512M PCI-Express 1 Memory
- * 0xa000_0000 512M PCI-Express 2 Memory
- * Changed it for operating from 0xd0000000
- *
+ * BAT2 PCI1 and PCI1 MEM
* if CONFIG_RIO
- * BAT2 512M Cache-inhibited, guarded
- * 0xc000_0000 512M RapidIO Memory
+ * BAT2 Rapidio Memory
*/
#ifdef CONFIG_PCI
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
@@ -456,30 +460,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
/*
- * BAT3 4M Cache-inhibited, guarded
- * 0xf800_0000 4M CCSR
+ * BAT3 CCSR Space
*/
#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
/*
- * BAT4 32M Cache-inhibited, guarded
- * 0xe200_0000 16M PCI-Express 1 I/O
- * 0xe300_0000 16M PCI-Express 2 I/0
- * Note that this is at 0xe0000000
+ * BAT4 PCI1_IO and PCI2_IO
*/
#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_128K \
+ | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
/*
- * BAT5 128K Cacheable, non-guarded
- * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
+ * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
*/
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
@@ -487,8 +488,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
/*
- * BAT6 8M Cache-inhibited, guarded
- * 0xff80_0000 8M FLASH
+ * BAT6 FLASH
*/
#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
@@ -506,7 +506,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
-/* Leave BAT7 free here - it is used for various things later */
+/*
+ * BAT7 FREE - used later for tmp mappings
+ */
#define CONFIG_SYS_DBAT7L 0x00000000
#define CONFIG_SYS_DBAT7U 0x00000000
#define CONFIG_SYS_IBAT7L 0x00000000
--
1.5.5.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 9/9] mpc8641: Support 36-bit physical addressing
2008-11-05 20:55 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Becky Bruce
@ 2008-11-05 20:55 ` Becky Bruce
2008-11-05 21:42 ` Kumar Gala
2008-11-06 23:37 ` [U-Boot] [PATCH 9/9 V2] mpc8641: Support 36-bit physical addressing Becky Bruce
2008-11-06 19:28 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Scott Wood
2008-11-06 20:04 ` [U-Boot] [PATCH 8/9] " Jon Loeliger
2 siblings, 2 replies; 31+ messages in thread
From: Becky Bruce @ 2008-11-05 20:55 UTC (permalink / raw)
To: u-boot
This patch creates a memory map with all the devices
in 36-bit physical space, in addition to the 32-bit map.
The CCSR relocation is moved (again, sorry) to
allow for the physical address to be 36 bits - this
requires translation to be enabled. With 36-bit physical
addressing enabled, we are no longer running with VA=PA
translations. This means we have to distinguish between
the two in the config file. The existing region name is
used to indicate the virtual address, and a _PHYS variety
is created to represent the physical address.
Large physical addressing is not enabled by default.
Set CONFIG_PHYS_64BIT in the config file to turn this on.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
board/freescale/mpc8641hpcn/law.c | 13 ++--
cpu/mpc86xx/start.S | 44 ++++++++---
include/configs/MPC8641HPCN.h | 164 +++++++++++++++++++++++++++++--------
3 files changed, 168 insertions(+), 53 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 669a091..bd357b8 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -31,12 +31,13 @@
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
- * if PCI
+ * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * else if RIO
+ * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
* 0x8000_0000 0x9fff_ffff RapidIO 512M
* endif
+ * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
* 0xffc0_0000 0xffc0_ffff PCI1 IO 64K
* 0xffc1_0000 0xffc1_ffff PCI2 IO 64K
* 0xffe0_0000 0xffef_ffff CCSRBAR 1M
@@ -53,15 +54,15 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
#endif
#ifdef CONFIG_PCI
- SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
#elif defined(CONFIG_RIO)
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
#endif
- SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 0aa8a4f..efd654c 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -209,11 +209,6 @@ boot_warm:
sync
#endif
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
- /* setup ccsrbar now while we're in real mode */
- bl setup_ccsrbar
-#endif
-
/*
* Calculate absolute address in FLASH and jump there
*------------------------------------------------------*/
@@ -267,6 +262,10 @@ addr_trans_enabled:
sync
#endif
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+ bl setup_ccsrbar
+#endif
+
/* set up the stack pointer in our newly created
* cache-ram (r1) */
lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
@@ -414,6 +413,26 @@ early_bats:
mtspr DBAT6L, r4
mtspr DBAT6U, r3
isync
+
+#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+ /* IBAT 7 */
+ lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL at h
+ ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL at l
+ lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU at h
+ ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU at l
+ mtspr IBAT7L, r4
+ mtspr IBAT7U, r3
+ isync
+
+ /* DBAT 7 */
+ lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL at h
+ ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL at l
+ lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU at h
+ ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU at l
+ mtspr DBAT7L, r4
+ mtspr DBAT7U, r3
+ isync
+#endif
blr
.globl clear_tlbs
@@ -860,17 +879,20 @@ setup_ccsrbar:
lis r4, CONFIG_SYS_CCSRBAR_DEFAULT at h
ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT at l
- lis r5, CONFIG_SYS_CCSRBAR at h
- ori r5, r5, CONFIG_SYS_CCSRBAR at l
- srwi r6,r5,12
- stw r6, 0(r4)
+ lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW at h
+ ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW at l
+ srwi r5,r5,12
+ li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH at l
+ rlwimi r5,r6,20,8,11
+ stw r5, 0(r4) /* Store physical value of CCSR */
isync
- lis r5, 0xffff
- ori r5,r5,0xf000
+ lis r5, TEXT_BASE at h
+ ori r5,r5,TEXT_BASE at l
lwz r5, 0(r5)
isync
+ /* Use VA of CCSR to do read */
lis r3, CONFIG_SYS_CCSRBAR at h
lwz r5, CONFIG_SYS_CCSRBAR at l(r3)
isync
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index ec3d112..c84ae5e 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -38,6 +38,7 @@
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
#ifdef RUN_DIAG
#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
@@ -92,6 +93,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
+ * With the exception of PCI Memory and Rapid IO, most devices will simply
+ * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
+ * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
+#else
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
+#endif
+
+/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
@@ -99,6 +111,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+/* Physical addresses */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+#endif
+
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
@@ -160,23 +180,31 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \
+ | CONFIG_SYS_PHYS_ADDR_HIGH)
+
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
/* Convert an address into the right format for the BR registers */
+#ifdef CONFIG_PHYS_64BIT
+#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
+ ((x & 0x300000000ULL) >> 19)))
+#else
#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#endif
-#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) \
- | 0x00001001) /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | 0x00001001) /* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
-#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \
- | 0x00001001) /* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
+#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
+ | 0x00001001) /* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE) \
- | 0x00000801) /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
+ | 0x00000801) /* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
/*
* The LBC_BASE is the base of the region that contains the PIXIS and the CF.
@@ -184,9 +212,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* required for the smallest BAT mapping, so there's a 64k hole.
*/
#define CONFIG_SYS_LBC_BASE 0xffde0000
+#define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \
+ | CONFIG_SYS_PHYS_ADDR_HIGH)
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
+#define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
#define PIXIS_SIZE 0x00008000 /* 32k */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
@@ -206,6 +237,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
+#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -295,7 +327,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* RapidIO MMU
*/
#define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL
+#else
#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+#endif
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
/*
@@ -303,10 +339,16 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL
+#else
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#endif
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
+ | CONFIG_SYS_PHYS_ADDR_HIGH)
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */
/* For RTL8139 */
@@ -315,9 +357,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \
+ CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \
+ + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
+ + CONFIG_SYS_PCI1_IO_SIZE)
#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
+ CONFIG_SYS_PCI1_IO_SIZE)
#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
@@ -349,10 +394,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_PHYS
+#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT
/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
/* video */
#define CONFIG_VIDEO
@@ -365,7 +410,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
/*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -419,6 +464,21 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif /* CONFIG_TSEC_ENET */
+/* Contort an addr into the format needed for BATs */
+#ifdef CONFIG_PHYS_64BIT
+#define BAT_PHYS_ADDR(x) ((unsigned long) \
+ ((x & 0x00000000ffffffffULL) | \
+ ((x & 0x0000000e00000000ULL) >> 24) | \
+ ((x & 0x0000000100000000ULL) >> 30)))
+#else
+#define BAT_PHYS_ADDR(x) (x)
+#endif
+
+
+/* Put high physical address bits into the BAT format */
+#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
+#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
+
/*
* BAT0 DDR
*/
@@ -430,12 +490,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* BAT1 LBC (PIXIS/CF)
*/
-#define CONFIG_SYS_DBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
| BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+ | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
/* if CONFIG_PCI:
@@ -444,14 +505,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* BAT2 Rapidio Memory
*/
#ifdef CONFIG_PCI
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \
+#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \
| BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
#else /* CONFIG_RIO */
+#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
+ | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
@@ -461,22 +531,43 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* BAT3 CCSR Space
+ * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
+ * instead. The assembler chokes on ULL.
*/
-#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
+ | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
| BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
+ | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
/*
* BAT4 PCI1_IO and PCI2_IO
*/
-#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_128K \
+#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
| BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
/*
@@ -490,12 +581,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* BAT6 FLASH
*/
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
| BATU_VP)
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
/* Map the last 1M of flash where we're running from reset */
@@ -652,8 +744,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"ramdiskfile=your.ramdisk.u-boot\0" \
"fdtaddr=c00000\0" \
"fdtfile=mpc8641_hpcn.dtb\0" \
- "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
- "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+ "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
+ "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
"maxcpus=2"
--
1.5.5.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 9/9] mpc8641: Support 36-bit physical addressing
2008-11-05 20:55 ` [U-Boot] [PATCH 9/9] mpc8641: Support 36-bit physical addressing Becky Bruce
@ 2008-11-05 21:42 ` Kumar Gala
2008-11-06 19:04 ` [U-Boot] [PATCH] toplevel Makefile: Add MPC8641HPCN_36BIT target Becky Bruce
2008-11-06 23:37 ` [U-Boot] [PATCH 9/9 V2] mpc8641: Support 36-bit physical addressing Becky Bruce
1 sibling, 1 reply; 31+ messages in thread
From: Kumar Gala @ 2008-11-05 21:42 UTC (permalink / raw)
To: u-boot
On Nov 5, 2008, at 2:55 PM, Becky Bruce wrote:
> This patch creates a memory map with all the devices
> in 36-bit physical space, in addition to the 32-bit map.
> The CCSR relocation is moved (again, sorry) to
> allow for the physical address to be 36 bits - this
> requires translation to be enabled. With 36-bit physical
> addressing enabled, we are no longer running with VA=PA
> translations. This means we have to distinguish between
> the two in the config file. The existing region name is
> used to indicate the virtual address, and a _PHYS variety
> is created to represent the physical address.
>
> Large physical addressing is not enabled by default.
> Set CONFIG_PHYS_64BIT in the config file to turn this on.
>
> Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
> ---
> board/freescale/mpc8641hpcn/law.c | 13 ++--
> cpu/mpc86xx/start.S | 44 ++++++++---
> include/configs/MPC8641HPCN.h | 164 ++++++++++++++++++++++++++++
> +--------
> 3 files changed, 168 insertions(+), 53 deletions(-)
Can we add something to the top level Makefile like the following:
MPC8641HPCN_36BIT_config \
MPC8641HPCN_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _36BIT_,$@)" ] ; then \
$(XECHO) -n "... I Rock " ; \
echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/
config.h ;\
fi ;
@$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
(also add this to MAKEALL)
The name could be better.
- k
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH] toplevel Makefile: Add MPC8641HPCN_36BIT target
2008-11-05 21:42 ` Kumar Gala
@ 2008-11-06 19:04 ` Becky Bruce
2008-11-06 21:06 ` Scott Wood
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-06 19:04 UTC (permalink / raw)
To: u-boot
This will enable CONFIG_PHYS_36BIT for MPC8641HPCN.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
Makefile | 8 +++++++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/Makefile b/Makefile
index 983a3cd..09e671d 100644
--- a/Makefile
+++ b/Makefile
@@ -2436,8 +2436,14 @@ TQM8560_config: unconfig
MPC8610HPCD_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
+MPC8641HPCN_36BIT_config \
MPC8641HPCN_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
+ @mkdir -p $(obj)include
+ @if [ "$(findstring _36BIT_,$@)" ] ; then \
+ echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
+ $(XECHO) "... enabling 36-bit physical addressing." ; \
+ fi
+ @$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
sbc8641d_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
--
1.5.6.5
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-05 20:55 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 9/9] mpc8641: Support 36-bit physical addressing Becky Bruce
@ 2008-11-06 19:28 ` Scott Wood
2008-11-06 22:12 ` Becky Bruce
2008-11-06 20:04 ` [U-Boot] [PATCH 8/9] " Jon Loeliger
2 siblings, 1 reply; 31+ messages in thread
From: Scott Wood @ 2008-11-06 19:28 UTC (permalink / raw)
To: u-boot
Becky Bruce wrote:
> The memory map on the 8641hpcn is modified to look more like
> the 85xx boards; this is a step towards a more standardized
> layout going forward. As part of this change, we now relocate
> the flash.
>
> The regions for some of the mappings were far larger than they
> needed to be. I have reduced the mappings to match the
> actual sizes supported by the hardware.
Was this causing any actual problems? It seems to be inviting
gratuitous breakage if the device tree isn't updated at the same time,
or for any OSes not using the device tree.
-Scott
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-05 20:55 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 9/9] mpc8641: Support 36-bit physical addressing Becky Bruce
2008-11-06 19:28 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Scott Wood
@ 2008-11-06 20:04 ` Jon Loeliger
2008-11-06 22:14 ` Becky Bruce
2008-11-06 23:41 ` Becky Bruce
2 siblings, 2 replies; 31+ messages in thread
From: Jon Loeliger @ 2008-11-06 20:04 UTC (permalink / raw)
To: u-boot
On Wed, 2008-11-05 at 14:55 -0600, Becky Bruce wrote:
> The memory map on the 8641hpcn is modified to look more like
> the 85xx boards; this is a step towards a more standardized
> layout going forward. As part of this change, we now relocate
> the flash.
>
> The regions for some of the mappings were far larger than they
> needed to be. I have reduced the mappings to match the
> actual sizes supported by the hardware.
>
> In addition I have removed the comments at the head
> of the BAT blocks in the config file, rather than updating
> them. These get horribly out of date, and it's a simple
> matter to look at the defines to see what they are set to
> since everything is right here in the same file.
>
> Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
> ---
> board/freescale/mpc8641hpcn/config.mk | 2 +-
> board/freescale/mpc8641hpcn/law.c | 23 ++++++----
> cpu/mpc86xx/start.S | 2 +-
> include/configs/MPC8641HPCN.h | 76 +++++++++++++++++----------------
> 4 files changed, 54 insertions(+), 49 deletions(-)
Does this affect any flash addresses mentioned in
the README.mpc86xx too?
jdl
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH] toplevel Makefile: Add MPC8641HPCN_36BIT target
2008-11-06 19:04 ` [U-Boot] [PATCH] toplevel Makefile: Add MPC8641HPCN_36BIT target Becky Bruce
@ 2008-11-06 21:06 ` Scott Wood
2008-11-06 21:40 ` Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Scott Wood @ 2008-11-06 21:06 UTC (permalink / raw)
To: u-boot
Becky Bruce wrote:
> This will enable CONFIG_PHYS_36BIT for MPC8641HPCN.
>
> Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
> ---
> Makefile | 8 +++++++-
> 1 files changed, 7 insertions(+), 1 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 983a3cd..09e671d 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -2436,8 +2436,14 @@ TQM8560_config: unconfig
> MPC8610HPCD_config: unconfig
> @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
>
> +MPC8641HPCN_36BIT_config \
> MPC8641HPCN_config: unconfig
> - @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
> + @mkdir -p $(obj)include
> + @if [ "$(findstring _36BIT_,$@)" ] ; then \
> + echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
> + $(XECHO) "... enabling 36-bit physical addressing." ; \
> + fi
> + @$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
>
> sbc8641d_config: unconfig
> @$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
When would you ever not turn this on?
-Scott
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH] toplevel Makefile: Add MPC8641HPCN_36BIT target
2008-11-06 21:06 ` Scott Wood
@ 2008-11-06 21:40 ` Becky Bruce
2008-11-06 21:59 ` Scott Wood
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-06 21:40 UTC (permalink / raw)
To: u-boot
On Nov 6, 2008, at 3:06 PM, Scott Wood wrote:
> Becky Bruce wrote:
>> This will enable CONFIG_PHYS_36BIT for MPC8641HPCN.
>> Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
>> ---
>> Makefile | 8 +++++++-
>> 1 files changed, 7 insertions(+), 1 deletions(-)
>> diff --git a/Makefile b/Makefile
>> index 983a3cd..09e671d 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -2436,8 +2436,14 @@ TQM8560_config: unconfig
>> MPC8610HPCD_config: unconfig
>> @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
>> +MPC8641HPCN_36BIT_config \
>> MPC8641HPCN_config: unconfig
>> - @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
>> + @mkdir -p $(obj)include
>> + @if [ "$(findstring _36BIT_,$@)" ] ; then \
>> + echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
>> + $(XECHO) "... enabling 36-bit physical addressing." ; \
>> + fi
>> + @$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
>> sbc8641d_config: unconfig
>> @$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
>
> When would you ever not turn this on?
>
We don't want PHYS_64BIT on unconditionally. It has the effect of
moving all the devices into high physical memory, which means you need
a different Linux/dts. I expect the normal case to be that it is
off. Just those few customers that actually want to do this will use
the PHYS_64BIT version.
Cheers,
B
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH] toplevel Makefile: Add MPC8641HPCN_36BIT target
2008-11-06 21:40 ` Becky Bruce
@ 2008-11-06 21:59 ` Scott Wood
2008-11-06 22:07 ` Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Scott Wood @ 2008-11-06 21:59 UTC (permalink / raw)
To: u-boot
Becky Bruce wrote:
> We don't want PHYS_64BIT on unconditionally. It has the effect of
> moving all the devices into high physical memory, which means you need a
> different Linux/dts.
Another reason we should really be packaging the device trees with u-boot.
> I expect the normal case to be that it is off.
> Just those few customers that actually want to do this will use the
> PHYS_64BIT version.
OK, though ideally it could be chosen dynamically based on how much
memory there is (in u-boot) or #address-cells (in linux).
-Scott
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH] toplevel Makefile: Add MPC8641HPCN_36BIT target
2008-11-06 21:59 ` Scott Wood
@ 2008-11-06 22:07 ` Becky Bruce
0 siblings, 0 replies; 31+ messages in thread
From: Becky Bruce @ 2008-11-06 22:07 UTC (permalink / raw)
To: u-boot
On Nov 6, 2008, at 3:59 PM, Scott Wood wrote:
> Becky Bruce wrote:
>> We don't want PHYS_64BIT on unconditionally. It has the effect of
>> moving all the devices into high physical memory, which means you
>> need a different Linux/dts.
>
> Another reason we should really be packaging the device trees with u-
> boot.
>
>> I expect the normal case to be that it is off. Just those few
>> customers that actually want to do this will use the PHYS_64BIT
>> version.
>
> OK, though ideally it could be chosen dynamically based on how much
> memory there is (in u-boot) or #address-cells (in linux).
>
Well, in an ideal world, I'd have an IOMMU ;-) I left this build-time
configurable because turning on PHYS_64BIT makes u-boot bigger, and
there are always people who shout about that. There are also
scenarios where you want to run with it enabled, and you don't have a
lot of RAM. And, last but not least, I want to be consistent with
linux, where 36-bit is a build-time configurable thing. Going to 36-
bit requires that you know what you're doing - you need a 36b enabled
kernel and .dts in order to boot - I don't want u-boot silently
turning it on. At least not for a while.
-Becky
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-06 19:28 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Scott Wood
@ 2008-11-06 22:12 ` Becky Bruce
2008-11-06 22:16 ` Scott Wood
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-06 22:12 UTC (permalink / raw)
To: u-boot
On Nov 6, 2008, at 1:28 PM, Scott Wood wrote:
> Becky Bruce wrote:
>> The memory map on the 8641hpcn is modified to look more like
>> the 85xx boards; this is a step towards a more standardized
>> layout going forward. As part of this change, we now relocate
>> the flash.
>> The regions for some of the mappings were far larger than they
>> needed to be. I have reduced the mappings to match the
>> actual sizes supported by the hardware.
>
> Was this causing any actual problems? It seems to be inviting
> gratuitous breakage if the device tree isn't updated at the same
> time, or for any OSes not using the device tree.
>
Was it causing any problems for anybody running it? Only minor
stuff. Was it causing maintenance to be a god-awful nightmare?
Definitely. The map for 86xx was a real mess, and really needed to be
cleaned up - trying to make sense of the previous code was a real
pain, and the whole structure of it was very fragile - any attempt to
make a change resulted in random breakage because it was such a house
of cards (which I ran into repeatedly while doing the 36b stuff). The
decision to change the map was also made for ease of code maintenance
- having a similar map to 85xx makes it much easier now to port the
36b changes over to that platform which is the next major task. The
boot sequences for the 2 platforms are also a lot more similar now, so
I'm hoping that a little bit of pain now will save us a lot more pain
in the future.
I agree that there's potential for breakage, but in the case of Linux,
which is the vast majority of u-boot users, I think it's minimal. For
the non-linux cases, changing an OS to accomodate the new map should
be a minor task.
The device tree changes are in hand, and as soon as this goes into the
u-boot tree, I will push those to Linux.
We *do* need a comment in the release notes for this revision of u-
boot that the map for 8641 has changed so it doesn't catch anyone by
surprise.
-B
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-06 20:04 ` [U-Boot] [PATCH 8/9] " Jon Loeliger
@ 2008-11-06 22:14 ` Becky Bruce
2008-11-06 23:41 ` Becky Bruce
1 sibling, 0 replies; 31+ messages in thread
From: Becky Bruce @ 2008-11-06 22:14 UTC (permalink / raw)
To: u-boot
On Nov 6, 2008, at 2:04 PM, Jon Loeliger wrote:
> On Wed, 2008-11-05 at 14:55 -0600, Becky Bruce wrote:
>> The memory map on the 8641hpcn is modified to look more like
>> the 85xx boards; this is a step towards a more standardized
>> layout going forward. As part of this change, we now relocate
>> the flash.
>>
>> The regions for some of the mappings were far larger than they
>> needed to be. I have reduced the mappings to match the
>> actual sizes supported by the hardware.
>>
>> In addition I have removed the comments at the head
>> of the BAT blocks in the config file, rather than updating
>> them. These get horribly out of date, and it's a simple
>> matter to look at the defines to see what they are set to
>> since everything is right here in the same file.
>>
>> Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
>> ---
>> board/freescale/mpc8641hpcn/config.mk | 2 +-
>> board/freescale/mpc8641hpcn/law.c | 23 ++++++----
>> cpu/mpc86xx/start.S | 2 +-
>> include/configs/MPC8641HPCN.h | 76 ++++++++++++++++
>> +----------------
>> 4 files changed, 54 insertions(+), 49 deletions(-)
>
> Does this affect any flash addresses mentioned in
> the README.mpc86xx too?
Yes, it does. It affects a lot of stuff in that file which I was,
until now, unaware of. Will fix. Thanks!
-Becky
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-06 22:12 ` Becky Bruce
@ 2008-11-06 22:16 ` Scott Wood
2008-11-06 22:24 ` Becky Bruce
2008-11-06 22:30 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Jon Loeliger
0 siblings, 2 replies; 31+ messages in thread
From: Scott Wood @ 2008-11-06 22:16 UTC (permalink / raw)
To: u-boot
Becky Bruce wrote:
> We *do* need a comment in the release notes for this revision of u-boot
> that the map for 8641 has changed so it doesn't catch anyone by surprise.
How about a runtime check in the board fdt code to print a warning if it
finds an old device tree? Unfortunately, using new dts with old u-boot
isn't as easy to detect.
-Scott
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-06 22:16 ` Scott Wood
@ 2008-11-06 22:24 ` Becky Bruce
2008-11-06 22:26 ` Scott Wood
2008-11-06 22:30 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Jon Loeliger
1 sibling, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-06 22:24 UTC (permalink / raw)
To: u-boot
On Nov 6, 2008, at 4:16 PM, Scott Wood wrote:
> Becky Bruce wrote:
>> We *do* need a comment in the release notes for this revision of u-
>> boot that the map for 8641 has changed so it doesn't catch anyone
>> by surprise.
>
> How about a runtime check in the board fdt code to print a warning
> if it finds an old device tree? Unfortunately, using new dts with
> old u-boot isn't as easy to detect.
Where exactly were you thinking this would go? I'm not sure what to
detect - I could pretty easily do a rudimentary check, like checking
if the CCSR location in the .dts is the same as the one u-boot has,
but there's always the possiblity that someone has hacked their u-boot
to put the CCSR in the same spot.
-B
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-06 22:24 ` Becky Bruce
@ 2008-11-06 22:26 ` Scott Wood
2008-11-07 19:45 ` [U-Boot] [PATCH] mpc8641: Try to detect old .dts files Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Scott Wood @ 2008-11-06 22:26 UTC (permalink / raw)
To: u-boot
Becky Bruce wrote:
> On Nov 6, 2008, at 4:16 PM, Scott Wood wrote:
>> How about a runtime check in the board fdt code to print a warning if
>> it finds an old device tree? Unfortunately, using new dts with old
>> u-boot isn't as easy to detect.
>
> Where exactly were you thinking this would go?
ft_board_setup()
> I'm not sure what to
> detect - I could pretty easily do a rudimentary check, like checking if
> the CCSR location in the .dts is the same as the one u-boot has, but
> there's always the possiblity that someone has hacked their u-boot to
> put the CCSR in the same spot.
Well then they can hack the warning out. :-)
-Scott
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-06 22:16 ` Scott Wood
2008-11-06 22:24 ` Becky Bruce
@ 2008-11-06 22:30 ` Jon Loeliger
2008-11-06 22:39 ` Becky Bruce
1 sibling, 1 reply; 31+ messages in thread
From: Jon Loeliger @ 2008-11-06 22:30 UTC (permalink / raw)
To: u-boot
On Thu, 2008-11-06 at 16:16 -0600, Scott Wood wrote:
> Becky Bruce wrote:
> > We *do* need a comment in the release notes for this revision of u-boot
> > that the map for 8641 has changed so it doesn't catch anyone by surprise.
>
> How about a runtime check in the board fdt code to print a warning if it
> finds an old device tree? Unfortunately, using new dts with old u-boot
> isn't as easy to detect.
>
> -Scott
For the record, and admittedly not quite an answer to
your issue at all, though I feel it would mitigate the
pain dramatically, I have a version of the DTS file that
uses my new expression language to completely abstract
out the 32/36-bit differences and compile a DTB for either
with the single flip of a -DUSE_36_BIT handed to the dtc
command line.
Even if no one cares.
jdl
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-06 22:30 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Jon Loeliger
@ 2008-11-06 22:39 ` Becky Bruce
2008-11-06 23:36 ` [U-Boot] [PATCH 8/9 V2] " Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-06 22:39 UTC (permalink / raw)
To: u-boot
On Nov 6, 2008, at 4:30 PM, Jon Loeliger wrote:
> On Thu, 2008-11-06 at 16:16 -0600, Scott Wood wrote:
>> Becky Bruce wrote:
>>> We *do* need a comment in the release notes for this revision of u-
>>> boot
>>> that the map for 8641 has changed so it doesn't catch anyone by
>>> surprise.
>>
>> How about a runtime check in the board fdt code to print a warning
>> if it
>> finds an old device tree? Unfortunately, using new dts with old u-
>> boot
>> isn't as easy to detect.
>>
>> -Scott
>
>
> For the record, and admittedly not quite an answer to
> your issue at all, though I feel it would mitigate the
> pain dramatically, I have a version of the DTS file that
> uses my new expression language to completely abstract
> out the 32/36-bit differences and compile a DTB for either
> with the single flip of a -DUSE_36_BIT handed to the dtc
> command line.
>
> Even if no one cares.
I think that's something we need to talk about..... what are the plans
for switching over to the new language?
I'll push a simple patch to change the 32-bit memory map, but when we
go 36-bit in Linux, this might make sense.
-B
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9 V2] mpc8641: Change 32-bit memory map
2008-11-06 22:39 ` Becky Bruce
@ 2008-11-06 23:36 ` Becky Bruce
0 siblings, 0 replies; 31+ messages in thread
From: Becky Bruce @ 2008-11-06 23:36 UTC (permalink / raw)
To: u-boot
The memory map on the 8641hpcn is modified to look more like
the 85xx boards; this is a step towards a more standardized
layout going forward. As part of this change, we now relocate
the flash.
The regions for some of the mappings were far larger than they
needed to be. I have reduced the mappings to match the
actual sizes supported by the hardware.
In addition I have removed the comments at the head
of the BAT blocks in the config file, rather than updating
them. These get horribly out of date, and it's a simple
matter to look at the defines to see what they are set to
since everything is right here in the same file.
Documentation has been changed to reflect the new map, as this
change is user visible, and affects the OS which runs post-uboot.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
board/freescale/mpc8641hpcn/config.mk | 2 +-
board/freescale/mpc8641hpcn/law.c | 23 ++++++----
cpu/mpc86xx/start.S | 2 +-
doc/README.mpc8641hpcn | 40 +++++++++--------
include/configs/MPC8641HPCN.h | 76 +++++++++++++++++----------------
5 files changed, 75 insertions(+), 68 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/config.mk b/board/freescale/mpc8641hpcn/config.mk
index f778dcb..487a766 100644
--- a/board/freescale/mpc8641hpcn/config.mk
+++ b/board/freescale/mpc8641hpcn/config.mk
@@ -25,7 +25,7 @@
# default CCSRBAR is at 0xff700000
# assume U-Boot is less than 0.5MB
#
-TEXT_BASE = 0xfff00000
+TEXT_BASE = 0xeff00000
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 8ec5238..669a091 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -31,17 +31,20 @@
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
+ * if PCI
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
- * 0xf800_0000 0xf80f_ffff CCSRBAR 1M
- * 0xf810_0000 0xf81f_ffff PIXIS 1M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ * else if RIO
+ * 0x8000_0000 0x9fff_ffff RapidIO 512M
+ * endif
+ * 0xffc0_0000 0xffc0_ffff PCI1 IO 64K
+ * 0xffc1_0000 0xffc1_ffff PCI2 IO 64K
+ * 0xffe0_0000 0xffef_ffff CCSRBAR 1M
+ * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K
+ * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M
*
* Notes:
- * CCSRBAR don't need a configured Local Access Window.
+ * CCSRBAR doesn't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
@@ -52,12 +55,12 @@ struct law_entry law_table[] = {
#ifdef CONFIG_PCI
SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
#elif defined(CONFIG_RIO)
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
#endif
- SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
};
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 60af3dd..0aa8a4f 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -285,7 +285,7 @@ addr_trans_enabled:
#ifdef RUN_DIAG
/* Load PX_AUX register address in r4 */
- lis r4, 0xf810
+ lis r4, PIXIS_BASE at h
ori r4, r4, 0x6
/* Load contents of PX_AUX in r3 bits 24 to 31*/
lbz r3, 0(r4)
diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn
index 2c3c703..24b39f1 100644
--- a/doc/README.mpc8641hpcn
+++ b/doc/README.mpc8641hpcn
@@ -79,51 +79,53 @@ Switches:
3. Flash U-Boot
---------------
-The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
+The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
It is possible to use either half to boot using u-boot. Switch 5 bit 2
is used for this purpose.
-0xFF800000 to 0xFFBFFFFF - 4MB
-0xFFC00000 to 0xFFFFFFFF - 4MB
-When this bit is 0, U-Boot is at 0xFFF00000.
-When this bit is 1, U-Boot is at 0xFFB00000.
+0xEF800000 to 0xEFBFFFFF - 4MB
+0xEFC00000 to 0xEFFFFFFF - 4MB
+When this bit is 0, U-Boot is at 0xEFF00000.
+When this bit is 1, U-Boot is at 0xEFB00000.
Use the above mentioned flash commands to program the other half, and
use switch 5, bit 2 to alternate between the halves. Note: The booting
-version of U-Boot will always be at 0xFFF00000.
+version of U-Boot will always be at 0xEFF00000.
-To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
+To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
tftp 1000000 u-boot.bin
protect off all
- erase fff00000 +$filesize
- cp.b 1000000 fff00000 $filesize
+ erase eff00000 +$filesize
+ cp.b 1000000 eff00000 $filesize
or use tftpflash command:
run tftpflash
-To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
+To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
tftp 1000000 u-boot.bin
- erase ffb00000 +$filesize
- cp.b 1000000 ffb00000 $filesize
+ erase efb00000 +$filesize
+ cp.b 1000000 efb00000 $filesize
4. Memory Map
-------------
+NOTE: RIO and PCI are mutually exclusive, so they share an address
Memory Range Device Size
------------ ------ ----
0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x9fff_ffff RIO MEM 512M
0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
- 0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M
- 0xf800_0000 0xf80f_ffff CCSR 1M
- 0xf810_0000 0xf81f_ffff PIXIS 1M
+ 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M
+ 0xffe0_0000 0xffef_ffff CCSR 1M
+ 0xffdf_0000 0xffdf_7fff PIXIS 8K
+ 0xffdf_8000 0xffdf_ffff CF 8K
0xf840_0000 0xf840_3fff Stack space 32K
- 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 16M
- 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M
- 0xfe00_0000 0xfeff_ffff Flash(alternate)16M
- 0xff00_0000 0xffff_ffff Flash(boot bank)16M
+ 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
+ 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
+ 0xef80_0000 0xefff_ffff Flash 8M
5. pixis_reset command
--------------------
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 4925057..ec3d112 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -96,7 +96,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
@@ -159,7 +159,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
@@ -172,15 +172,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \
| 0x00001001) /* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
+#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE) \
| 0x00000801) /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
+/*
+ * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
+ * The PIXIS and CF by themselves aren't large enough to take up the 128k
+ * required for the smallest BAT mapping, so there's a 64k hole.
+ */
+#define CONFIG_SYS_LBC_BASE 0xffde0000
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE (CONFIG_SYS_CCSRBAR + 0x00100000) /* PIXIS registers */
+#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
+#define PIXIS_SIZE 0x00008000 /* 32k */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
@@ -198,7 +205,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
-#define CF_BASE (PIXIS_BASE + 0x00100000)
+#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -287,7 +294,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */
#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
@@ -299,8 +306,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */
/* For RTL8139 */
#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
@@ -313,7 +320,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
+ CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
#if defined(CONFIG_PCI)
@@ -413,8 +420,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif /* CONFIG_TSEC_ENET */
/*
- * BAT0 2G Cacheable, non-guarded
- * 0x0000_0000 2G DDR
+ * BAT0 DDR
*/
#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
@@ -422,22 +428,20 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
/*
- * BAT1 unused
+ * BAT1 LBC (PIXIS/CF)
*/
-#define CONFIG_SYS_DBAT1L 0
-#define CONFIG_SYS_DBAT1U 0
-#define CONFIG_SYS_IBAT1L 0
-#define CONFIG_SYS_IBAT1U 0
+#define CONFIG_SYS_DBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
+ | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
/* if CONFIG_PCI:
- * BAT2 1G Cache-inhibited, guarded
- * 0x8000_0000 512M PCI-Express 1 Memory
- * 0xa000_0000 512M PCI-Express 2 Memory
- * Changed it for operating from 0xd0000000
- *
+ * BAT2 PCI1 and PCI1 MEM
* if CONFIG_RIO
- * BAT2 512M Cache-inhibited, guarded
- * 0xc000_0000 512M RapidIO Memory
+ * BAT2 Rapidio Memory
*/
#ifdef CONFIG_PCI
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
@@ -456,30 +460,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
/*
- * BAT3 4M Cache-inhibited, guarded
- * 0xf800_0000 4M CCSR
+ * BAT3 CCSR Space
*/
#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
+ | BATU_VP)
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
/*
- * BAT4 32M Cache-inhibited, guarded
- * 0xe200_0000 16M PCI-Express 1 I/O
- * 0xe300_0000 16M PCI-Express 2 I/0
- * Note that this is at 0xe0000000
+ * BAT4 PCI1_IO and PCI2_IO
*/
#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_128K \
+ | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
/*
- * BAT5 128K Cacheable, non-guarded
- * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
+ * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
*/
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
@@ -487,8 +488,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
/*
- * BAT6 8M Cache-inhibited, guarded
- * 0xff80_0000 8M FLASH
+ * BAT6 FLASH
*/
#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
@@ -506,7 +506,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
-/* Leave BAT7 free here - it is used for various things later */
+/*
+ * BAT7 FREE - used later for tmp mappings
+ */
#define CONFIG_SYS_DBAT7L 0x00000000
#define CONFIG_SYS_DBAT7U 0x00000000
#define CONFIG_SYS_IBAT7L 0x00000000
--
1.5.6.5
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 9/9 V2] mpc8641: Support 36-bit physical addressing
2008-11-05 20:55 ` [U-Boot] [PATCH 9/9] mpc8641: Support 36-bit physical addressing Becky Bruce
2008-11-05 21:42 ` Kumar Gala
@ 2008-11-06 23:37 ` Becky Bruce
1 sibling, 0 replies; 31+ messages in thread
From: Becky Bruce @ 2008-11-06 23:37 UTC (permalink / raw)
To: u-boot
This patch creates a memory map with all the devices
in 36-bit physical space, in addition to the 32-bit map.
The CCSR relocation is moved (again, sorry) to
allow for the physical address to be 36 bits - this
requires translation to be enabled. With 36-bit physical
addressing enabled, we are no longer running with VA=PA
translations. This means we have to distinguish between
the two in the config file. The existing region name is
used to indicate the virtual address, and a _PHYS variety
is created to represent the physical address.
Large physical addressing is not enabled by default.
Set CONFIG_PHYS_64BIT in the config file to turn this on.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
board/freescale/mpc8641hpcn/law.c | 13 ++--
cpu/mpc86xx/start.S | 44 ++++++++---
doc/README.mpc8641hpcn | 24 ++++++
include/configs/MPC8641HPCN.h | 164 +++++++++++++++++++++++++++++--------
4 files changed, 192 insertions(+), 53 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 669a091..bd357b8 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -31,12 +31,13 @@
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
- * if PCI
+ * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * else if RIO
+ * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
* 0x8000_0000 0x9fff_ffff RapidIO 512M
* endif
+ * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
* 0xffc0_0000 0xffc0_ffff PCI1 IO 64K
* 0xffc1_0000 0xffc1_ffff PCI2 IO 64K
* 0xffe0_0000 0xffef_ffff CCSRBAR 1M
@@ -53,15 +54,15 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
#endif
#ifdef CONFIG_PCI
- SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
#elif defined(CONFIG_RIO)
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
#endif
- SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 0aa8a4f..efd654c 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -209,11 +209,6 @@ boot_warm:
sync
#endif
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
- /* setup ccsrbar now while we're in real mode */
- bl setup_ccsrbar
-#endif
-
/*
* Calculate absolute address in FLASH and jump there
*------------------------------------------------------*/
@@ -267,6 +262,10 @@ addr_trans_enabled:
sync
#endif
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+ bl setup_ccsrbar
+#endif
+
/* set up the stack pointer in our newly created
* cache-ram (r1) */
lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
@@ -414,6 +413,26 @@ early_bats:
mtspr DBAT6L, r4
mtspr DBAT6U, r3
isync
+
+#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+ /* IBAT 7 */
+ lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL at h
+ ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL at l
+ lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU at h
+ ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU at l
+ mtspr IBAT7L, r4
+ mtspr IBAT7U, r3
+ isync
+
+ /* DBAT 7 */
+ lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL at h
+ ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL at l
+ lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU at h
+ ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU at l
+ mtspr DBAT7L, r4
+ mtspr DBAT7U, r3
+ isync
+#endif
blr
.globl clear_tlbs
@@ -860,17 +879,20 @@ setup_ccsrbar:
lis r4, CONFIG_SYS_CCSRBAR_DEFAULT at h
ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT at l
- lis r5, CONFIG_SYS_CCSRBAR at h
- ori r5, r5, CONFIG_SYS_CCSRBAR at l
- srwi r6,r5,12
- stw r6, 0(r4)
+ lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW at h
+ ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW at l
+ srwi r5,r5,12
+ li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH at l
+ rlwimi r5,r6,20,8,11
+ stw r5, 0(r4) /* Store physical value of CCSR */
isync
- lis r5, 0xffff
- ori r5,r5,0xf000
+ lis r5, TEXT_BASE at h
+ ori r5,r5,TEXT_BASE at l
lwz r5, 0(r5)
isync
+ /* Use VA of CCSR to do read */
lis r3, CONFIG_SYS_CCSRBAR at h
lwz r5, CONFIG_SYS_CCSRBAR at l(r3)
isync
diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn
index 24b39f1..dbdf244 100644
--- a/doc/README.mpc8641hpcn
+++ b/doc/README.mpc8641hpcn
@@ -113,6 +113,9 @@ To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
-------------
NOTE: RIO and PCI are mutually exclusive, so they share an address
+For 32-bit u-boot, devices are mapped so that the virtual address ==
+the physical address, and the map looks liks this:
+
Memory Range Device Size
------------ ------ ----
0x0000_0000 0x7fff_ffff DDR 2G
@@ -127,6 +130,27 @@ NOTE: RIO and PCI are mutually exclusive, so they share an address
0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
0xef80_0000 0xefff_ffff Flash 8M
+For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
+However, the physical map is altered to reside in 36-bit space, as follows.
+Addresses are no longer mapped with VA == PA. All accesses from
+software use the VA; the PA is only used for setting up windows
+and mappings. Note that the low 32 bits are the same as the VA above;
+only the top 4 bits vary:
+
+ Memory Range Device Size
+ ------------ ------ ----
+ 0x0_0000_0000 0x0_7fff_ffff DDR 2G
+ 0xc_8000_0000 0xc_9fff_ffff RIO MEM 512M
+ 0xc_8000_0000 0xc_9fff_ffff PCI1/PEX1 MEM 512M
+ 0xc_a000_0000 0xc_bfff_ffff PCI2/PEX2 MEM 512M
+ 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
+ 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
+ 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
+ 0x0_f840_0000 0xf_f840_3fff Stack space 32K
+ 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K
+ 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K
+ 0xf_ef80_0000 0xf_efff_ffff Flash 8M
+
5. pixis_reset command
--------------------
A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index ec3d112..c84ae5e 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -38,6 +38,7 @@
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
#ifdef RUN_DIAG
#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
@@ -92,6 +93,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
+ * With the exception of PCI Memory and Rapid IO, most devices will simply
+ * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
+ * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
+#else
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
+#endif
+
+/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
@@ -99,6 +111,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+/* Physical addresses */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+#endif
+
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
@@ -160,23 +180,31 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \
+ | CONFIG_SYS_PHYS_ADDR_HIGH)
+
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
/* Convert an address into the right format for the BR registers */
+#ifdef CONFIG_PHYS_64BIT
+#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
+ ((x & 0x300000000ULL) >> 19)))
+#else
#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#endif
-#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) \
- | 0x00001001) /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
+#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | 0x00001001) /* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
-#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \
- | 0x00001001) /* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
+#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
+ | 0x00001001) /* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE) \
- | 0x00000801) /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
+ | 0x00000801) /* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
/*
* The LBC_BASE is the base of the region that contains the PIXIS and the CF.
@@ -184,9 +212,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* required for the smallest BAT mapping, so there's a 64k hole.
*/
#define CONFIG_SYS_LBC_BASE 0xffde0000
+#define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \
+ | CONFIG_SYS_PHYS_ADDR_HIGH)
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
+#define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
#define PIXIS_SIZE 0x00008000 /* 32k */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
@@ -206,6 +237,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
+#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -295,7 +327,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* RapidIO MMU
*/
#define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL
+#else
#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+#endif
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
/*
@@ -303,10 +339,16 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL
+#else
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#endif
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
+ | CONFIG_SYS_PHYS_ADDR_HIGH)
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */
/* For RTL8139 */
@@ -315,9 +357,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \
+ CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \
+ + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
+ + CONFIG_SYS_PCI1_IO_SIZE)
#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
+ CONFIG_SYS_PCI1_IO_SIZE)
#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
@@ -349,10 +394,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_PHYS
+#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT
/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
/* video */
#define CONFIG_VIDEO
@@ -365,7 +410,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
/*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -419,6 +464,21 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif /* CONFIG_TSEC_ENET */
+/* Contort an addr into the format needed for BATs */
+#ifdef CONFIG_PHYS_64BIT
+#define BAT_PHYS_ADDR(x) ((unsigned long) \
+ ((x & 0x00000000ffffffffULL) | \
+ ((x & 0x0000000e00000000ULL) >> 24) | \
+ ((x & 0x0000000100000000ULL) >> 30)))
+#else
+#define BAT_PHYS_ADDR(x) (x)
+#endif
+
+
+/* Put high physical address bits into the BAT format */
+#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
+#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
+
/*
* BAT0 DDR
*/
@@ -430,12 +490,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* BAT1 LBC (PIXIS/CF)
*/
-#define CONFIG_SYS_DBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
| BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
+ | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
/* if CONFIG_PCI:
@@ -444,14 +505,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* BAT2 Rapidio Memory
*/
#ifdef CONFIG_PCI
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \
+#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \
| BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
#else /* CONFIG_RIO */
+#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
+ | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
@@ -461,22 +531,43 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* BAT3 CCSR Space
+ * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
+ * instead. The assembler chokes on ULL.
*/
-#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
+ | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
| BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
+ | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
/*
* BAT4 PCI1_IO and PCI2_IO
*/
-#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_128K \
+#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
| BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
/*
@@ -490,12 +581,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* BAT6 FLASH
*/
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
| BATU_VP)
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
/* Map the last 1M of flash where we're running from reset */
@@ -652,8 +744,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"ramdiskfile=your.ramdisk.u-boot\0" \
"fdtaddr=c00000\0" \
"fdtfile=mpc8641_hpcn.dtb\0" \
- "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
- "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+ "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
+ "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
"maxcpus=2"
--
1.5.6.5
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map
2008-11-06 20:04 ` [U-Boot] [PATCH 8/9] " Jon Loeliger
2008-11-06 22:14 ` Becky Bruce
@ 2008-11-06 23:41 ` Becky Bruce
1 sibling, 0 replies; 31+ messages in thread
From: Becky Bruce @ 2008-11-06 23:41 UTC (permalink / raw)
To: u-boot
On Nov 6, 2008, at 2:04 PM, Jon Loeliger wrote:
> On Wed, 2008-11-05 at 14:55 -0600, Becky Bruce wrote:
>> The memory map on the 8641hpcn is modified to look more like
>> the 85xx boards; this is a step towards a more standardized
>> layout going forward. As part of this change, we now relocate
>> the flash.
>>
>> The regions for some of the mappings were far larger than they
>> needed to be. I have reduced the mappings to match the
>> actual sizes supported by the hardware.
>>
>> In addition I have removed the comments at the head
>> of the BAT blocks in the config file, rather than updating
>> them. These get horribly out of date, and it's a simple
>> matter to look at the defines to see what they are set to
>> since everything is right here in the same file.
>>
>> Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
>> ---
>> board/freescale/mpc8641hpcn/config.mk | 2 +-
>> board/freescale/mpc8641hpcn/law.c | 23 ++++++----
>> cpu/mpc86xx/start.S | 2 +-
>> include/configs/MPC8641HPCN.h | 76 ++++++++++++++++
>> +----------------
>> 4 files changed, 54 insertions(+), 49 deletions(-)
>
> Does this affect any flash addresses mentioned in
> the README.mpc86xx too?
I resubmitted the last 2 patches, now with the appropriate
documentation updates. That is the only change.
-Becky
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH] mpc8641: Try to detect old .dts files
2008-11-06 22:26 ` Scott Wood
@ 2008-11-07 19:45 ` Becky Bruce
2008-11-10 22:58 ` Scott Wood
0 siblings, 1 reply; 31+ messages in thread
From: Becky Bruce @ 2008-11-07 19:45 UTC (permalink / raw)
To: u-boot
Since we've changed the memory map of the board, be nice and
add some checking to try to catch out-of-date .dts files. We do
this by checking the CCSRBAR location in the .dts and comparing
it to the CCSRBAR location in u-boot. If they don't match, a
warning msg is printed. This isn't foolproof, but it's simple and
will catch most of the cases where an out-of-date .dts is present,
including all of the cases where a new u-boot is used with an old
standard MPC8641 .dts file as supplied with Linux.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
---
board/freescale/mpc8641hpcn/mpc8641hpcn.c | 27 +++++++++++++++++++++++++++
include/configs/MPC8641HPCN.h | 3 +++
2 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index d6a0a56..1f9f2a3 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -254,6 +254,10 @@ extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
void
ft_board_setup(void *blob, bd_t *bd)
{
+ int off;
+ u64 *tmp;
+ u32 *addrcells;
+
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
@@ -262,6 +266,29 @@ ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_PCI2
ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
+
+ /*
+ * Warn if it looks like the device tree doesn't match u-boot.
+ * This is just an estimation, based on the location of CCSR,
+ * which is defined by the "reg" property in the soc node.
+ */
+ off = fdt_path_offset(blob, "/soc8641");
+ addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
+ tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
+
+ if (tmp) {
+ u64 addr;
+ if (addrcells && (*addrcells == 2))
+ addr = *tmp;
+ else
+ addr = *(u32 *)tmp;
+
+ if (addr != CONFIG_SYS_CCSRBAR_PHYS)
+ printf("WARNING: The CCSRBAR address in your .dts "
+ "does not match the address of the CCSR "
+ "in u-boot. This means your .dts might "
+ "be old.\n");
+ }
}
#endif
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index c84ae5e..69b4c44 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -115,8 +115,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \
+ | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32))
#else
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
#endif
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
--
1.5.6.5
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH] mpc8641: Try to detect old .dts files
2008-11-07 19:45 ` [U-Boot] [PATCH] mpc8641: Try to detect old .dts files Becky Bruce
@ 2008-11-10 22:58 ` Scott Wood
2008-11-10 23:09 ` Becky Bruce
0 siblings, 1 reply; 31+ messages in thread
From: Scott Wood @ 2008-11-10 22:58 UTC (permalink / raw)
To: u-boot
On Fri, Nov 07, 2008 at 01:45:57PM -0600, Becky Bruce wrote:
> + if (tmp) {
> + u64 addr;
> + if (addrcells && (*addrcells == 2))
> + addr = *tmp;
> + else
> + addr = *(u32 *)tmp;
If #address-cells is missing (not that it ever should be), the default is 2, not 1.
-Scott
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH] mpc8641: Try to detect old .dts files
2008-11-10 22:58 ` Scott Wood
@ 2008-11-10 23:09 ` Becky Bruce
0 siblings, 0 replies; 31+ messages in thread
From: Becky Bruce @ 2008-11-10 23:09 UTC (permalink / raw)
To: u-boot
On Nov 10, 2008, at 4:58 PM, Scott Wood wrote:
> On Fri, Nov 07, 2008 at 01:45:57PM -0600, Becky Bruce wrote:
>> + if (tmp) {
>> + u64 addr;
>> + if (addrcells && (*addrcells == 2))
>> + addr = *tmp;
>> + else
>> + addr = *(u32 *)tmp;
>
> If #address-cells is missing (not that it ever should be), the
> default is 2, not 1.
I'll post a follow-up; Jon has already picked this up in his tree.
Thanks!
-B
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2008-11-10 23:09 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-11-05 20:55 [U-Boot] [PATCH 0/9] MPC8641 memory map changes/cleanup/36-bit Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 1/9] mpc8641: Remove extra "0" from BR2 define Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 2/9] mpc86xx: Move setup_bats into cpu_init_f Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 3/9] mpc8641: only define CONFIG_ENV_SIZE once Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 4/9] mpc8641: Drop imaginary second flash bank, map 8MB Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 5/9] mpc8641: make DIAG_ADDR == FLASH_BASE Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 6/9] mpc86xx: Use SRR0/1/rfi to enable address translation, not blr Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 7/9] mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLY Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Becky Bruce
2008-11-05 20:55 ` [U-Boot] [PATCH 9/9] mpc8641: Support 36-bit physical addressing Becky Bruce
2008-11-05 21:42 ` Kumar Gala
2008-11-06 19:04 ` [U-Boot] [PATCH] toplevel Makefile: Add MPC8641HPCN_36BIT target Becky Bruce
2008-11-06 21:06 ` Scott Wood
2008-11-06 21:40 ` Becky Bruce
2008-11-06 21:59 ` Scott Wood
2008-11-06 22:07 ` Becky Bruce
2008-11-06 23:37 ` [U-Boot] [PATCH 9/9 V2] mpc8641: Support 36-bit physical addressing Becky Bruce
2008-11-06 19:28 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Scott Wood
2008-11-06 22:12 ` Becky Bruce
2008-11-06 22:16 ` Scott Wood
2008-11-06 22:24 ` Becky Bruce
2008-11-06 22:26 ` Scott Wood
2008-11-07 19:45 ` [U-Boot] [PATCH] mpc8641: Try to detect old .dts files Becky Bruce
2008-11-10 22:58 ` Scott Wood
2008-11-10 23:09 ` Becky Bruce
2008-11-06 22:30 ` [U-Boot] [PATCH 8/9] mpc8641: Change 32-bit memory map Jon Loeliger
2008-11-06 22:39 ` Becky Bruce
2008-11-06 23:36 ` [U-Boot] [PATCH 8/9 V2] " Becky Bruce
2008-11-06 20:04 ` [U-Boot] [PATCH 8/9] " Jon Loeliger
2008-11-06 22:14 ` Becky Bruce
2008-11-06 23:41 ` Becky Bruce
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