[U-Boot] Confusion in loading of reset configuration words on MPC8360

[U-Boot] Confusion in loading of reset configuration words on MPC8360

[Elison Niven]

Hi List,

I have confusion in the manner the MPC8360 loads the reset configuration
words from FLASH. According to the datasheet, it should read from the
following locations:

0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38

But I have observed the following on my board. The LCS goes low for eight
cycles. The addresses during these cycles are as follows:

LA27     LA28     LA29     LA30     LA31
0          0          0          0          0
0          0          0          1          0
0          0          1          0          0
0          0          1          1          0
0          1          0          0          0
0          1          0          1          0
0          1          1          0          0
0          1          1          1          0

Thus, the addresses on which I need to write the reset configuration words
become 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E.

In the u-boot.bin file, the reset config words are placed not on the above
addresses but it is according to the datasheet:

0x00 : 04 04 04 04 04 04 04 04     0x08 : 04 04 04 04 04 04 04 04
0x10 : 00 00 00 00 00 00 00 00     0x18 : 06 06 06 06 06 06 06 06

0x20 : B0 B0 B0 B0 B0 B0 B0 B0     0x20 : 60 60 60 60 60 60 60 60
0x30 : 00 00 00 00 00 00 00 00     0x38 : 00 00 00 00 00 00 00 00

This file seems correct to me. Then why does the processor read from the
wrong addresses? Can anyone point out what is wrong and what needs to be
done? Has anyone encountered a similar problem?

U-boot version - 1.2.0
With patches from ltib-iso - 2007.08.12
make clean
make mpc8360_emdsconfig
make

Best Regards,
Elison

[U-Boot] Confusion in loading of reset configuration words on MPC8360

[David Hawkins]

Hi Elison,

> I have confusion in the manner the MPC8360 loads the reset configuration
> words from FLASH. According to the datasheet, it should read from the
> following locations:
> 
> 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38

http://www.ovro.caltech.edu/~dwh/carma_board/powerpc_mpc8349e.pdf

p33 has a logic analyzer capture from an MPC834EA board. It'll
be similar on the MPC8360.

The logic analyzer captures the address bits in little-endian
order due to the way the logic analyzer header was routed on
the PCB (and the inability of the logic analyzer to flip them)
so, the 5-bits get shown in bit-reversed order, i.e.,

LA[27..31] bits     logic analyzer trace
   0x00     0_0000   0x00
   0x08     0_1000   0x02
   0x10     1_0000   0x01
   0x18     1_1000   0x03

But the addresses are as per the data sheet.

> But I have observed the following on my board. The LCS goes low for eight
> cycles.

Hmm, the p33 trace show LCS# low always, and its ALE you want
to trigger off. I think I had to rework the Freescale board
to route LALE to the logic analyzer header though ...

> The addresses during these cycles are as follows:
> 
> LA27     LA28     LA29     LA30     LA31
> 0          0          0          0          0
> 0          0          0          1          0
> 0          0          1          0          0
> 0          0          1          1          0
> 0          1          0          0          0
> 0          1          0          1          0
> 0          1          1          0          0
> 0          1          1          1          0
> 
> Thus, the addresses on which I need to write the reset configuration words
> become 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E.

Check your schematic, are the signals routed correctly?

> In the u-boot.bin file, the reset config words are placed not on the above
> addresses but it is according to the datasheet:
> 
> 0x00 : 04 04 04 04 04 04 04 04     0x08 : 04 04 04 04 04 04 04 04
> 0x10 : 00 00 00 00 00 00 00 00     0x18 : 06 06 06 06 06 06 06 06
> 
> 0x20 : B0 B0 B0 B0 B0 B0 B0 B0     0x20 : 60 60 60 60 60 60 60 60
> 0x30 : 00 00 00 00 00 00 00 00     0x38 : 00 00 00 00 00 00 00 00
> 
> This file seems correct to me. Then why does the processor read from the
> wrong addresses? Can anyone point out what is wrong and what needs to be
> done? Has anyone encountered a similar problem?

I'd suspect your logic analyzer pod assignments, or your
PCB at this point.

Use your JTAG debugger to read from specific addresses
and see if the LA[] signals toggle appropriately.

Cheers,
Dave