[U-Boot] [PATCH] lib_ppc: rework the flush_cache

Scott Wood
2008-12-03T16:33:28Z

Liu Dave wrote:
> The lib_ppc version basically is as below.
> void flush_cache (ulong start_addr, ulong size)
> {
> ulong addr, end_addr = start_addr + size;
> addr = start_addr & (CONFIG_SYS_CACHELINE_SIZE - 1);
> for (addr = start_addr; addr < end_addr; addr += CONFIG_SYS_CACHELINE_SIZE) {
> asm ("dcbst 0,%0": :"r" (addr));
> }
> }
>
> so, you are not completely right, the flush is from start_addr.

Ah, right, the first addr assignment is just dead code.

>>> + start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
>>> + end = (start_addr + size) & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
>> end = start_addr + size - 1;
>>
>> The rounding is unnecessary for end, and without the - 1, if
>> start_addr + size is on a cacheline boundary, you'll flush one
>> cache line too many (which might not be mapped, or might cause end
>> to wrap around to zero if flushing at the end of the address
>> space).
>>
>
> I don't see what is the problem in my patch at here.

start_addr = 0
size = 0x1000

start will be 0
end will be 0x1000

The loop will flush the cache line at 0x1000, because it uses <= rather
than <. That is outside the area that was requested to be flushed.
Maybe it's not mapped. Or, maybe start + size = 0 and nothing gets flushed.

-Scott