From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Schwarz Date: Tue, 09 Dec 2008 19:01:53 +0100 Subject: [U-Boot] FSL DDR @ 83xx In-Reply-To: <1228765822.29252.17.camel@ld0161-tx32> References: <493D530A.8040409@matrix-vision.de> <1228765822.29252.17.camel@ld0161-tx32> Message-ID: <493EB291.4080201@matrix-vision.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Jon Loeliger schrieb: > On Mon, 2008-12-08 at 18:02 +0100, Andre Schwarz wrote: > >> Kim, >> >> I'd like to change my DDR setup code since it looks like my computed >> values are not perfectly stable on our 8343 based board. >> >> This implies using a fake SPD and the related code to set up the controller. >> >> Is the "new" common FSL DDR setup code (cpu/mpc8xxx/ddr/*) stable for >> 83xx or shall I stick to cpu/mpc83xx/spd_sdram.c for a while ? >> > > The new, common DDR code in use by the FSL boards does not > yet cover the 83xx family, though the plan is to eventually > do so. > > Patches in that direction, are, naturally, welcome... :-) > > jdl > > > Is anybody working on this ? The spd_sdram code lacks support for 3 bank adress bits and various termination schemes which are essential for tiny boards with soldered memory. Of course I could contribute for the 8343. But I don't now about the "others" (85xx/86x) in detail and don't want to scatter #ifdefs all over the code ... regards, Andr? MATRIX VISION GmbH, Talstra?e 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Gesch?ftsf?hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner