[U-Boot] FSL DDR @ 83xx

[Jon Loeliger <jdl@freescale.com>]

Andre Schwarz wrote:

> mpc83xx/spd_sdram needs some fixes to work with latest chips :
> 
> 1.
> max_data_rate seems to be mishandled. Since it's twice the physical
> clock we need much higher vaues for calculating optimum caslat ... or
> use "max_bus_clock" instead. bus_clock seems to be reasonable since the
> SPD timing values refer to clock and/or clock cycle time.
> 
> if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
> 
> This is the top-level if -> DDR-333 gives max_data_rate = 666 .... and
> goes into
> 
> else if (max_data_rate >= 323) { /* it is DDR 333 */
> 
> Additionally the caslat reduction code should use "<=" and ">=" for the
> evaluation of clk_cycle2 and clk_cycle3. Otherwise it will only work for
> a specific memory with SPD contents.
> 
> To make it short :
> DDR-II-333 will be configured with caslat = 5 @ 133MHz Controller speed
> -> It would work fine with caslat = 3.
> 
> 2.
> Actually 3 bank adress bits are quite usual. This SPD values are not yet
> evaluated.
> 
> 3.
> Termination schemes (150/75/50 Ohm) and driver characteristics are not
> handled at all.
> Most boards would need this or may only run stable with the most
> conservative timings.
> 
> 
> Does it make sense to fix these things or is the "new" DDR code the way
> to go ?

Ultimately, one way or another, at the end of the day, when all
is said and done, the old way will be removed and the new way
will prevail.  You know.

So, yeah, all of these "per board" configurations will have to
be supplied in a new file like each of the 85xx and 86xx boards
have done.

HTH,
jdl