[U-Boot] FSL DDR @ 83xx

Andre Schwarz
2008-12-11T11:06:31Z

Kumar Gala schrieb:
>
> On Dec 9, 2008, at 12:01 PM, Andre Schwarz wrote:
>
>> Jon Loeliger schrieb:
>>> On Mon, 2008-12-08 at 18:02 +0100, Andre Schwarz wrote:
>>>
>>>> Kim,
>>>>
>>>> I'd like to change my DDR setup code since it looks like my computed
>>>> values are not perfectly stable on our 8343 based board.
>>>>
>>>> This implies using a fake SPD and the related code to set up the
>>>> controller.
>>>>
>>>> Is the "new" common FSL DDR setup code (cpu/mpc8xxx/ddr/*) stable for
>>>> 83xx or shall I stick to cpu/mpc83xx/spd_sdram.c for a while ?
>>>>
>>>
>>> The new, common DDR code in use by the FSL boards does not
>>> yet cover the 83xx family, though the plan is to eventually
>>> do so.
>>>
>>> Patches in that direction, are, naturally, welcome... :-)
>>>
>>> jdl
>>>
>>>
>>>
>> Is anybody working on this ?
>> The spd_sdram code lacks support for 3 bank adress bits and various
>> termination schemes which
>> are essential for tiny boards with soldered memory.
>>
>> Of course I could contribute for the 8343.
>> But I don't now about the "others" (85xx/86x) in detail and don't want
>> to scatter #ifdefs all over the code ...
>>
>> regards,
>> Andr?
>
> I don't believe anyone is currently working on getting the new ddr
> code to be used w/83xx. Feel free to submit patches that does this
> and we will review them as they are posted.
>
> - k
mpc83xx/spd_sdram needs some fixes to work with latest chips :

1.
max_data_rate seems to be mishandled. Since it's twice the physical
clock we need much higher vaues for calculating optimum caslat ... or
use "max_bus_clock" instead. bus_clock seems to be reasonable since the
SPD timing values refer to clock and/or clock cycle time.

if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */

This is the top-level if -> DDR-333 gives max_data_rate = 666 .... and
goes into

else if (max_data_rate >= 323) { /* it is DDR 333 */

Additionally the caslat reduction code should use "<=" and ">=" for the
evaluation of clk_cycle2 and clk_cycle3. Otherwise it will only work for
a specific memory with SPD contents.

To make it short :
DDR-II-333 will be configured with caslat = 5 @ 133MHz Controller speed
-> It would work fine with caslat = 3.

2.
Actually 3 bank adress bits are quite usual. This SPD values are not yet
evaluated.

3.
Termination schemes (150/75/50 Ohm) and driver characteristics are not
handled at all.
Most boards would need this or may only run stable with the most
conservative timings.

Does it make sense to fix these things or is the "new" DDR code the way
to go ?

regards,
Andr?

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